JP2002314086A - Mosfet - Google Patents

Mosfet

Info

Publication number
JP2002314086A
JP2002314086A JP2001115265A JP2001115265A JP2002314086A JP 2002314086 A JP2002314086 A JP 2002314086A JP 2001115265 A JP2001115265 A JP 2001115265A JP 2001115265 A JP2001115265 A JP 2001115265A JP 2002314086 A JP2002314086 A JP 2002314086A
Authority
JP
Japan
Prior art keywords
sense
electrode
pad electrode
mosfet
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2001115265A
Other languages
Japanese (ja)
Other versions
JP5014534B2 (en
Inventor
Shin Oikawa
慎 及川
Madoka Nishikawa
円 西川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2001115265A priority Critical patent/JP5014534B2/en
Publication of JP2002314086A publication Critical patent/JP2002314086A/en
Application granted granted Critical
Publication of JP5014534B2 publication Critical patent/JP5014534B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PROBLEM TO BE SOLVED: To solve problems associated with MOSFETs provided with sensing terminals that a sensing pad electrode is formed on the surface of a chip in proximity to a source electrode and cells as sensing terminals are formed directly under the sensing pad electrode, and cracks are produced in the chip due to the impact of bonding during wire bonding operation, and that the sensing pad region is large in size and this leads to reduction in the size of the actual operational region and complication of wiring to IC. SOLUTION: A flat region where no cells are formed is formed in proximity to a sensing portion, and a sensing pad electrode is formed thereon. Consequently, cracks are prevented from occurring in a chip due to the impact of bonding at 2nd bond. A gate pad electrode is placed in proximity to the sensing pad electrode. As a result, wiring to IC is facilitated, and ill-timed turn-on is reduced.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明はＭＯＳＦＥＴに係
り、特にセンス端子付きＭＯＳＦＥＴの組み立て時にお
いてチップのクラックを抑制するＭＯＳＦＥＴに関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOSFET, and more particularly, to a MOSFET that suppresses chip cracks when assembling a MOSFET with a sense terminal.

【０００２】[0002]

【従来の技術】情報化社会の進展に伴い、一般家庭を含
め電子機器は著しく普及し、スイッチング電源は小型で
低損失のため、ほとんどの電子機器に利用されている。
このため、最近の電子機器の多様化は電源に対する要求
をますます複雑なものにしており、特にスイッチング電
源のワンチップ化は電源の究極の課題と考えられる。ス
イッチング電源の小型化を達成するための基本的手段と
しては、スイッチング周波数の高周波化、損失の低減、
部品数の低減と機能化がある。これらの手段により実際
に製品化を行うには、低コスト化の厳しい関門を通らな
ければならず、それには量産化に適する方式であること
が条件となる。2. Description of the Related Art With the progress of the information-oriented society, electronic devices including ordinary households have become extremely popular, and switching power supplies have been used in almost all electronic devices because of their small size and low loss.
For this reason, the recent diversification of electronic devices has made the demands for power supplies more and more complicated. In particular, the one-chip switching power supply is considered to be the ultimate task of the power supply. Basic means for achieving the miniaturization of the switching power supply include higher switching frequency, lower loss,
There is a reduction in the number of parts and functionalization. In order to actually commercialize the product by these means, it is necessary to pass through a strict barrier to cost reduction, which requires a method suitable for mass production.

【０００３】また、省エネルギーの立場から、火をいれ
たままスタンバイ状態にあるときの電力、すなわちホッ
トスタンバイ電力は小さいことが必要で、できればゼロ
が望ましい。スタンバイ電力を低減するには出力に応じ
て回路の動作電力を減少させることが必要である。これ
には間欠発振の利用が一般に用いられているが、より完
全に行うには、制御電力を出力から取る、いわゆる自励
形回路の適用が有効である。自励形回路ではＲＣＣ（Ri
nging Choke Converter）がよく知られており、ＲＣ
Ｃ方式のスイッチング電源ＩＣには、多くの場合、電流
検出用のセンス端子付きＭＯＳＦＥＴが用いられてい
る。また、近年ではＲＣＣ方式のスイッチング電源ＩＣ
とセンス端子付きＭＯＳＦＥＴを2段重ねにすることに
より小型パッケージに内蔵が可能となっている。Further, from the standpoint of energy saving, it is necessary that the electric power when in the standby state with the fire on, that is, the hot standby electric power, is small, and is desirably zero if possible. To reduce the standby power, it is necessary to reduce the operating power of the circuit according to the output. The use of intermittent oscillation is generally used for this purpose, but in order to perform the operation more completely, application of a so-called self-excited circuit that takes control power from an output is effective. RCC (Ri
nging Choke Converter) is well known and RC
In many cases, a C-type switching power supply IC uses a MOSFET with a sense terminal for current detection. In recent years, RCC switching power supply ICs
By stacking two MOSFETs with a sense terminal and a MOSFET with a sense terminal, they can be built in a small package.

【０００４】図４に従来のセンス端子付きＭＯＳＦＥＴ
の上面図を示す。センス端子付きＭＯＳＦＥＴ２００
は、ゲートパッド電極３１と、センス部３２と、センス
パッド電極３３と、ゲート連結電極３４と、実動作領域
３５と、ＭＯＳトランジスタのセル３６と、ソース電極
３７と、シールド電極３８と、ソースパッド電極３９と
で構成される。FIG. 4 shows a conventional MOSFET having a sense terminal.
FIG. MOSFET200 with sense terminal
Are a gate pad electrode 31, a sense part 32, a sense pad electrode 33, a gate connection electrode 34, an actual operation area 35, a MOS transistor cell 36, a source electrode 37, a shield electrode 38, a source pad And an electrode 39.

【０００５】ゲートパッド電極３１は、ゲート電極と連
結し、点線の丸印で示すようにＡｕ線などの径の小さい
ボンディングワイヤ２１０で電極の取り出しが行われ
る。[0005] The gate pad electrode 31 is connected to the gate electrode, and the electrode is taken out by a bonding wire 210 having a small diameter such as an Au wire as shown by a dotted circle.

【０００６】センス部３２は、過電流を保護するため
に、実動作領域３５上の複数のＭＯＳトランジスタを電
流検出用のセンス端子として使用し、センスパッド電極
３３にコンタクトしている。センス部３２を駆動するゲ
ート電極はＭＯＳＦＥＴ本体のゲート電極と共通であ
り、チップ上でポリシリコンにより連結されている。The sense section 32 uses a plurality of MOS transistors on the actual operation area 35 as sense terminals for current detection and contacts a sense pad electrode 33 in order to protect the overcurrent. The gate electrode for driving the sense unit 32 is common to the gate electrode of the MOSFET body and is connected on the chip by polysilicon.

【０００７】センスパッド電極３３は、電極の取り出し
にソースパッド電極３９のボンディングワイヤと同径の
ワイヤを用いるため、その圧着面積に合わせてセンス部
として必要な面積よりも大きく形成し、点線の丸印で示
すようにボンディングワイヤ２２０が熱圧着される。The sense pad electrode 33 uses a wire having the same diameter as the bonding wire of the source pad electrode 39 for taking out the electrode. The bonding wire 220 is thermocompression-bonded as indicated by the mark.

【０００８】ゲート連結電極３４は、各セル３６のゲー
ト電極と接続され且つ実動作領域３５の周囲に配置され
ている。The gate connection electrode 34 is connected to the gate electrode of each cell 36 and is arranged around the actual operation area 35.

【０００９】実動作領域３５は、この中にパワーＭＯＳ
ＦＥＴを構成する多数のＭＯＳトランジスタのセル３６
が配列されている。The actual operation area 35 includes a power MOS
Many MOS transistor cells 36 constituting an FET
Are arranged.

【００１０】ソース電極３７は、実動作領域３５上に設
けられ且つ各セル３６のソース領域と接続して設けられ
る。The source electrode 37 is provided on the actual operation area 35 and connected to the source area of each cell 36.

【００１１】シールド電極３８は、その下に設けられた
アニュラーリングとコンタクトして、チップ終端への空
乏層の拡がりを抑える。The shield electrode 38 is in contact with an annular ring provided thereunder to prevent the depletion layer from spreading to the end of the chip.

【００１２】ソースパッド電極３９は、ソース電極３７
に接続され、電流容量を稼ぐため、点線の丸印で示すよ
うに直径１５０μｍのアルミ線等の径の大きいボンディ
ングワイヤが熱圧着され、電極の取り出しを行う。The source pad electrode 39 is
In order to increase the current capacity, a bonding wire having a large diameter such as an aluminum wire having a diameter of 150 μm or the like is thermocompression-bonded as shown by a dotted circle to take out an electrode.

【００１３】図５に、上記のセンス端子付きＭＯＳＦＥ
Ｔ２００をコントロールＩＣ２３０と１パッケージに実
装する場合の断面図を示す。これは、主にＲＣＣ方式の
スイッチング電源ＩＣとセンス端子付きＭＯＳＦＥＴを
2段重ねにすることにより小型パッケージに内蔵できる
ようにするもので、図４の実動作領域上に破線で示すよ
うにコントロールＩＣ２３０を重ねて配置した場合のＢ
−Ｂ線の断面図である。その際、同じワイヤで配線する
ソースパッド電極３９とセンスパッド電極３３では、ボ
ンディングワイヤ２２０を往復させるように配線され
る。まず、センス端子付きＭＯＳＦＥＴ２００のソース
パッド電極３９にワイヤボンドし（１’stボンド）、矢
印Ｃ方向に延在してコントロールＩＣ２３０のワイヤボ
ンド時に擦りつけて切断する（２’nｄボンド）。次
に、コントロールＩＣ２３０にワイヤボンドし（１’st
ボンド）矢印Ｄ方向に延在してＭＯＳＦＥＴ２００のセ
ンスパッド電極３３にワイヤボンドし、擦りつけて切断
する（２’nｄボンド）。FIG. 5 shows the MOSFE with a sense terminal.
FIG. 4 shows a cross-sectional view when T200 is mounted on a control IC 230 and one package. This mainly consists of an RCC switching power supply IC and a MOSFET with a sense terminal.
By stacking the control IC 230 in a small package by stacking the control IC 230 in the actual operation area shown in FIG.
It is sectional drawing of the -B line. At this time, the source pad electrode 39 and the sense pad electrode 33 that are wired with the same wire are wired so that the bonding wire 220 reciprocates. First, a wire bond is made to the source pad electrode 39 of the MOSFET 200 with a sense terminal (1'st bond), and it extends in the direction of arrow C and is rubbed and cut at the time of wire bonding of the control IC 230 (2'nd bond). Next, wire bonding is performed on the control IC 230 (1'st
(Bond) The wire is extended in the direction of arrow D, wire-bonded to the sense pad electrode 33 of the MOSFET 200, and cut by rubbing (2'nd bond).

【００１４】図６に、トレンチ型の各セル３６の断面構
造を示す。ＮチャンネルのパワーＭＯＳＦＥＴにおいて
は、Ｎ+型の半導体基板４１の上にＮ-型のエピタキシャ
ル層からなるドレイン領域４２を設け、その上にＰ型の
チャネル層４３を設ける。チャネル層４３からドレイン
領域４２まで到達するトレンチ４４を作り、トレンチ４
４の内壁をゲート酸化膜４５で被膜し、トレンチ４４に
充填されたポリシリコンよりなるゲート電極４６を設け
て各セル３６を形成する。トレンチ４４に隣接したチャ
ネル層４３表面にはＮ+型のソース領域４８が形成さ
れ、隣り合う２つのセルのソース領域４８間のチャネル
層４３表面にはＰ+型のボディコンタクト領域４９が形
成される。さらにチャネル層４３にはソース領域４８か
らトレンチ４４に沿ってチャネル領域４７が形成され
る。トレンチ４４上は層間絶縁膜５０で覆い、ソース領
域４８およびボディコンタクト領域４９にコンタクトす
るソース電極３４を設ける。チップ全面を覆って設けた
表面保護膜５１に開口部を設けて、ゲートパッド電極お
よびセンスパッド電極、ソースパッド電極（図示せず）
を形成する。かかるセル３６は図４の実動作領域５に多
数個配列される。具体的には小さい四角で表示したもの
が１個のセルである。FIG. 6 shows a sectional structure of each trench type cell 36. In the N-channel power MOSFET, a drain region 42 made of an N − -type epitaxial layer is provided on an N + -type semiconductor substrate 41, and a P-type channel layer 43 is provided thereon. A trench 44 extending from the channel layer 43 to the drain region 42 is formed.
4 is coated with a gate oxide film 45, and a gate electrode 46 made of polysilicon filled in the trench 44 is provided to form each cell 36. An N + type source region 48 is formed on the surface of the channel layer 43 adjacent to the trench 44, and a P + type body contact region 49 is formed on the surface of the channel layer 43 between the source regions 48 of two adjacent cells. You. Further, a channel region 47 is formed in the channel layer 43 from the source region 48 along the trench 44. The trench 44 is covered with an interlayer insulating film 50, and a source electrode 34 that contacts a source region 48 and a body contact region 49 is provided. Openings are provided in the surface protection film 51 provided so as to cover the entire surface of the chip, and gate pad electrodes, sense pad electrodes, and source pad electrodes (not shown) are provided.
To form Many such cells 36 are arranged in the actual operation area 5 of FIG. Specifically, one cell is represented by a small square.

【００１５】[0015]

【発明が解決しようとする課題】かかる従来のセンス付
きパワーＭＯＳＦＥＴでは、フレームに配線する場合に
はワイヤーダイボンドは、最初にチップ側パッドに圧着
し、その後フレームのポスト側に擦りつけて切断する。
最初のワイヤボンド（１’stボンド）時は、ワイヤ先端
がボール状になっており、チップへの機械的強度が緩和
されるが、ポストへボンドし、ワイヤを擦りつけて切断
するとき（２’ndボンド）に機械的強度が強くなってし
まう。In such a conventional power MOSFET with sense, when wiring to a frame, a wire die bond is first pressed against a chip side pad and then rubbed against a post side of the frame and cut.
At the time of the first wire bond (1'st bond), the tip of the wire is in a ball shape, and the mechanical strength to the chip is reduced. However, when the wire is bonded to the post and cut by rubbing the wire (2 'nd bond) will increase the mechanical strength.

【００１６】特に、ＲＣＣ方式のスイッチング電源ＩＣ
とセンス端子付きＭＯＳＦＥＴを2段重ねにすることに
より小型パッケージに内蔵するような場合には、ソース
パッド電極とセンスパッド電極でボンディングワイヤを
同じワイヤを使用し、往復させて配線している。そのた
め、１’stボンドとなるソースパッド電極はボール状の
ワイヤの圧着でよいが、２’ndボンドとなるセンスパッ
ド電極はコントロールＩＣから延在されるワイヤを圧着
し、擦りつけて切断するため、その部分での機械的強度
が強くなってしまう。センスパッド電極の直下はセンス
部のセルが配置されている部分と配置されていない部分
があり、その間およびセンス部のセル間で、段差が生じ
てしまうため、ボンディングワイヤを圧着する際に、そ
の衝撃でチップにクラックが発生する問題があった。In particular, an RCC type switching power supply IC
In the case where a MOSFET having a sense terminal and a MOSFET with a sense terminal are stacked in two stages to be built in a small package, the same bonding wire is used for the source pad electrode and the sense pad electrode, and the bonding wire is reciprocated. Therefore, the source pad electrode serving as the 1'st bond may be formed by pressure bonding of a ball-shaped wire, but the sense pad electrode serving as the 2'nd bond is formed by pressing the wire extending from the control IC and cutting it by rubbing. However, the mechanical strength at that portion is increased. Immediately below the sense pad electrode, there are a part where the cells of the sense part are arranged and a part where the cells are not arranged, and a step occurs between them and between the cells of the sense part. There was a problem that cracks occurred in the chip due to the impact.

【００１７】また、センスパッド電極に固着するボンデ
ィングワイヤ例えば１５０μｍのアルミ線などを使用す
るため、太いボンディングワイヤを圧着するセンスパッ
ド電極は、その圧着面積に合わせて、センス端子として
使用する面積よりも必要以上に大きく形成されていた。Further, since a bonding wire fixed to the sense pad electrode, for example, an aluminum wire of 150 μm or the like is used, the sense pad electrode for crimping a thick bonding wire has an area larger than the area used as a sense terminal according to the crimping area. It was formed larger than necessary.

【００１８】更に、センスパッド電極は、ＭＯＳＦＥＴ
の組立作業効率上ソースパッド電極近くに設けられてい
る。しかし、ゲート電極とセンスパッド電極を連結する
ポリシリコンが長くなるため、そこでの抵抗成分が発生
し、センス端子としての特性を悪化させる原因となって
いた。Further, the sense pad electrode is a MOSFET.
It is provided near the source pad electrode for the efficiency of assembling work. However, since the polysilicon connecting the gate electrode and the sense pad electrode becomes longer, a resistance component is generated there, which causes deterioration of characteristics as a sense terminal.

【００１９】[0019]

【課題を解決するための手段】本発明はかかる課題に鑑
みてなされ、多数のＭＯＳトランジスタのセルを配列し
た実動作領域と、該実動作領域上に設けられ前記ＭＯＳ
トランジスタの各セルのソース領域と接続されたソース
電極と、該ソース電極と接続したソースパッド電極と、
前記ＭＯＳトランジスタの各セルのゲート電極と接続し
たゲートパッド電極と、前記ＭＯＳトランジスタのうち
の複数のセルからなるセンス部と、前記センス部に接続
し前記センス部上を覆うセンス電極と、前記セルを設け
ない領域上に設けられ前記センス電極と接続したセンス
パッド電極と、前記ソース電極、前記ゲートパッド電極
および前記センスパッド電極にそれぞれ固着するワイヤ
とを具備することを特徴とし、センス部のワイヤが固着
される部分にはセルを設けず平坦にすることにより、
2’ndボンドで擦り付けて切断する際の衝撃によるチッ
プのクラック発生を抑制するものである。SUMMARY OF THE INVENTION The present invention has been made in consideration of the above problems, and has been made in consideration of the above-mentioned problems, and has an actual operation area in which a large number of MOS transistor cells are arranged.
A source electrode connected to the source region of each cell of the transistor, a source pad electrode connected to the source electrode,
A gate pad electrode connected to a gate electrode of each cell of the MOS transistor; a sense unit including a plurality of cells of the MOS transistor; a sense electrode connected to the sense unit and covering the sense unit; A sense pad electrode provided on a region where no sense electrode is provided and connected to the sense electrode; and wires fixed to the source electrode, the gate pad electrode, and the sense pad electrode, respectively. By flattening without attaching cells to the part where
This suppresses the occurrence of cracks in the chip due to the impact when cutting by rubbing with 2'nd bond.

【００２０】さらに、ゲートパッド電極近くにセンスパ
ッド電極を形成することにより、それらを連結している
ポリシリコンでの抵抗成分を低減し、スイッチングのタ
イミングのずれを低減し、高品質なセンス部を有するＭ
ＯＳＦＥＴを提供できる。Further, by forming a sense pad electrode near the gate pad electrode, the resistance component of the polysilicon connecting them is reduced, the shift in switching timing is reduced, and a high-quality sense section is formed. Have M
An OSFET can be provided.

【００２１】[0021]

【発明の実施の形態】本発明の実施の形態を図１から図
３を参照して詳細に説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail with reference to FIGS.

【００２２】本発明のパワーＭＯＳＦＥＴの平面図を図
１に示す。FIG. 1 shows a plan view of the power MOSFET of the present invention.

【００２３】センス端子付きＭＯＳＦＥＴ１００は、ゲ
ートパッド電極１と、センス部２と、センス電極３と、
センスパッド電極３ａと、ゲート連結電極４と、実動作
領域５と、ＭＯＳトランジスタのセル６と、ソース電極
７と、シールド電極８と、ソースパッド電極９と、ボン
ディングワイヤ１１０とから構成される。The MOSFET 100 with a sense terminal includes a gate pad electrode 1, a sense part 2, a sense electrode 3,
It comprises a sense pad electrode 3a, a gate connection electrode 4, an actual operation region 5, a MOS transistor cell 6, a source electrode 7, a shield electrode 8, a source pad electrode 9, and a bonding wire 110.

【００２４】ゲートパッド電極１は、ゲート電極と連結
し、点線の丸印で示すようにＡｕ線等の径の小さいボン
ディングワイヤ１１０で電極の取り出しが行われる。The gate pad electrode 1 is connected to the gate electrode, and the electrode is taken out by a bonding wire 110 having a small diameter such as an Au wire as shown by a dotted circle.

【００２５】センス部２は、過電流を保護するために、
実動作領域５上の複数のＭＯＳトランジスタを電流検出
用のセンス端子として使用し、センス電極３にコンタク
トしている。センス端子として使用するセルと隣接した
半導体基板の一部には、セルを設けず平坦な領域とす
る。この面積はボンディングワイヤ１１０の圧着に必要
且つ十分な大きさとする。センス部２を駆動するゲート
電極はＭＯＳＦＥＴ本体のゲート電極と共通であり、チ
ップ上でポリシリコンにより連結されている。The sense unit 2 is provided to protect the overcurrent
A plurality of MOS transistors on the actual operation area 5 are used as sense terminals for current detection, and are in contact with the sense electrodes 3. A part of the semiconductor substrate adjacent to a cell used as a sense terminal is formed as a flat region without a cell. This area is necessary and sufficient for crimping the bonding wire 110. The gate electrode for driving the sense unit 2 is common to the gate electrode of the MOSFET body and is connected on the chip by polysilicon.

【００２６】センス電極３は、ゲートパッド電極１の近
くに設け、センス部２に必要且つ十分な大きさでセンス
部２を覆って形成する。The sense electrode 3 is provided near the gate pad electrode 1 and is formed to cover the sense section 2 with a size necessary and sufficient for the sense section 2.

【００２７】センスパッド電極３ａは、センス電極３に
接続し、セルを配置しない平坦な半導体基板上にセンス
電極３と同時に形成する。センスパッド電極３ａの大き
さはボンディングワイヤ１１０の圧着に必要且つ十分な
面積とし、点線の丸印で示すように、ゲートパッド電極
１と同じボンディングワイヤ１１０が熱圧着され、電極
の取り出しを行う。The sense pad electrode 3a is connected to the sense electrode 3 and is formed simultaneously with the sense electrode 3 on a flat semiconductor substrate on which no cells are arranged. The size of the sense pad electrode 3a is necessary and sufficient for the bonding of the bonding wire 110, and the same bonding wire 110 as the gate pad electrode 1 is thermocompression-bonded to take out the electrode, as indicated by a dotted circle.

【００２８】ゲート連結電極４は、各セル６のゲート電
極と接続され且つ実動作領域５の周囲に配置されてい
る。The gate connection electrode 4 is connected to the gate electrode of each cell 6 and is arranged around the actual operation area 5.

【００２９】実動作領域５は、この中にパワーＭＯＳＦ
ＥＴを構成する多数のＭＯＳトランジスタのセル６が配
列されている。The actual operation area 5 includes a power MOSF therein.
A large number of MOS transistor cells 6 constituting the ET are arranged.

【００３０】ソース電極７は、実動作領域５上に設けら
れ且つ各セル６のソース領域と接続して設けられる。The source electrode 7 is provided on the actual operation area 5 and connected to the source area of each cell 6.

【００３１】シールド電極８は、その下に設けられたア
ニュラーリングとコンタクトして、チップ終端への空乏
層の拡がりを抑える。The shield electrode 8 is in contact with an annular ring provided thereunder to prevent the depletion layer from spreading to the chip end.

【００３２】ソースパッド電極９は、ゲートパッド電極
１およびセンスパッド電極３ａと同じボンディングワイ
ヤ１１０を２〜３本使用し、点線の丸印で示すように熱
圧着され、電極の取り出しを行う。The source pad electrode 9 uses two or three bonding wires 110, which are the same as the gate pad electrode 1 and the sense pad electrode 3a, and is thermocompression-bonded as indicated by a dotted circle to take out the electrode.

【００３３】ボンディングワイヤ１１０は、直径４０μ
ｍのＡｕ線等の金属細線で、ゲートパッド電極１および
センスパッド電極３ａ、ソースパッド電極９にそれぞれ
熱圧着される。The bonding wire 110 has a diameter of 40 μm.
The gate pad electrode 1, the sense pad electrode 3 a, and the source pad electrode 9 are each thermocompression-bonded with a thin metal wire such as an Au line of m.

【００３４】図２に、上記のセンス端子付きＭＯＳＦＥ
Ｔ１００をコントロールＩＣ１２０と１パッケージに実
装する場合の断面図を示す。これは、主にＲＣＣ方式の
スイッチング電源ＩＣとセンス端子付きＭＯＳＦＥＴを
2段重ねにすることにより小型パッケージに内蔵できる
ようにするもので、図１の実動作領域上に破線で示すよ
うにコントロールＩＣ１２０を重ねて配置した場合のＡ
−Ａ線の断面図である。FIG. 2 shows the MOSFE with the sense terminal.
FIG. 4 is a cross-sectional view when T100 is mounted on a control IC 120 and one package. This mainly consists of an RCC switching power supply IC and a MOSFET with a sense terminal.
The two-stage stacking makes it possible to be built in a small package, and is shown in FIG.
It is sectional drawing of the -A line.

【００３５】その際、ソースパッド電極９、ゲートパッ
ド電極１およびセンスパッド電極３ａは同じボンディン
グワイヤ１１０で配線され、特にゲートパッド電極１と
センスパッド電極３ａは、ボンディングワイヤ１１０を
往復させるように配線される。At this time, the source pad electrode 9, the gate pad electrode 1 and the sense pad electrode 3a are wired by the same bonding wire 110. In particular, the gate pad electrode 1 and the sense pad electrode 3a are wired so as to reciprocate the bonding wire 110. Is done.

【００３６】具体的には、センス端子付きＭＯＳＦＥＴ
１００のゲートパッド電極にワイヤボンドし（１’stボ
ンド）、矢印Ａ方向に延在してコントロールＩＣ１２０
のワイヤボンド時に擦りつけて切断する（２’nｄボン
ド）。次に、コントロールＩＣ１２０にワイヤボンドし
（１’stボンド）、矢印Ｂ方向に延在してＭＯＳＦＥＴ
１００のセンスパッド電極にワイヤボンドし、擦りつけ
て切断する（２’nｄボンド）。Specifically, a MOSFET with a sense terminal
100 is bonded to the gate pad electrode 100 (1'st bond) and extends in the direction of arrow A to extend the control IC 120
(2'nd bond) at the time of wire bonding. Next, wire bonding (1'st bonding) is performed on the control IC 120, and the MOSFET is
Wire-bond to 100 sense pad electrodes, rub and cut (2'nd bond).

【００３７】このとき、１’stボンドであるゲートパッ
ド電極は、ボンディングワイヤ１１０先端がボール状に
なっており、機械的強度は緩和される。一方、2’ndボ
ンドでは、コントロールＩＣ１２０から延在されたボン
ディングワイヤ１１０がセンスパッド電極に圧着され、
擦りつけて切断されるが、その直下が平坦であるため、
チップのクラック発生を抑制することができる。At this time, the tip of the bonding wire 110 of the gate pad electrode, which is a 1'st bond, has a ball shape, and the mechanical strength is reduced. On the other hand, in the 2'nd bond, the bonding wire 110 extended from the control IC 120 is pressed against the sense pad electrode,
It is cut by rubbing, but since it is directly flat,
Crack generation of the chip can be suppressed.

【００３８】図３は本発明に用いるトレンチ型のセル６
の断面構造を示す。尚、図１に示すものと同一構成要素
は同一記号とする。Ｎ+型の半導体基板１１の上にＮ-型
のエピタキシャル層からなるドレイン領域１２を設け、
その上にＰ型のチャネル層１３を設ける。チャネル層１
３からドレイン領域１２まで到達するトレンチ１４を作
り、トレンチ１４の内壁をゲート酸化膜１５で被膜し、
トレンチ１４に充填されたポリシリコンよりなるゲート
電極１６を設けて各セル６を形成する。トレンチ１４に
隣接したチャネル層１３表面にはＮ+型のソース領域１
８が形成され、隣り合う２つのセルのソース領域１８間
のチャネル層１３表面にはＰ+型のボディコンタクト領
域１９が形成される。さらにチャネル層１３にはソース
領域１８からトレンチ１４に沿ってチャネル領域１７が
形成される。トレンチ１４上は層間絶縁膜２０で覆い、
ソース領域１８およびボディコンタクト領域１９にコン
タクトするソース電極７を設ける。チップ全面を覆って
設けた表面保護膜２１に開口部を設けて、ゲートパッド
電極、センスパッド電極、センス電極およびソースパッ
ド電極（図示せず）を形成する。かかるセル６は図１の
実動作領域５に多数個配列される。具体的には小さい四
角で表示したものが１個のセルである。FIG. 3 shows a trench type cell 6 used in the present invention.
1 shows a cross-sectional structure. The same components as those shown in FIG. A drain region 12 made of an N − type epitaxial layer is provided on an N + type semiconductor substrate 11,
A P-type channel layer 13 is provided thereon. Channel layer 1
3, a trench 14 reaching the drain region 12 is formed, and an inner wall of the trench 14 is coated with a gate oxide film 15,
Each cell 6 is formed by providing a gate electrode 16 made of polysilicon filling the trench 14. An N + type source region 1 is formed on the surface of the channel layer 13 adjacent to the trench 14.
8 are formed, and a P + type body contact region 19 is formed on the surface of the channel layer 13 between the source regions 18 of two adjacent cells. Further, a channel region 17 is formed in the channel layer 13 from the source region 18 along the trench 14. The trench 14 is covered with an interlayer insulating film 20,
Source electrode 7 is provided for contacting source region 18 and body contact region 19. An opening is provided in the surface protection film 21 provided to cover the entire surface of the chip, and a gate pad electrode, a sense pad electrode, a sense electrode, and a source pad electrode (not shown) are formed. Many such cells 6 are arranged in the actual operation area 5 of FIG. Specifically, one cell is represented by a small square.

【００３９】本発明の特徴は、センスパッド電極３ａに
ある。センスパッド電極３ａの直下にはセルを配置せ
ず、平坦になっているため、２’nｄボンドで、ワイヤ
を擦りつけて切断する際に、その衝撃でチップにクラッ
クが発生するのを抑制できる。The feature of the present invention resides in the sense pad electrode 3a. Since no cells are arranged immediately below the sense pad electrode 3a, the chip is flat, so that when a wire is rubbed and cut with 2'nd bond, cracking of the chip due to the impact can be suppressed. .

【００４０】また、センス端子を駆動するゲート電極
と、ＭＯＳＦＥＴ本体のゲート電極は共通であり、それ
らをチップ上でポリシリコンにより連結して動作させる
ため、センスパッド電極をゲートパッド電極の近くに設
けることによりセンス部２とゲート電極の距離が近くな
れば、ポリシリコンによる抵抗成分が低減されるため、
オンするタイミングの差が小さくなる。センス部２は本
体ＭＯＳＦＥＴの保護用に設けられているので、極力早
くオンする必要があり、オンするタイミングの差が縮ま
れば、センス部２としての特性も向上する。Further, the gate electrode for driving the sense terminal and the gate electrode of the MOSFET body are common. To operate them by connecting them on the chip with polysilicon, a sense pad electrode is provided near the gate pad electrode. As a result, if the distance between the sensing portion 2 and the gate electrode becomes short, the resistance component due to polysilicon is reduced,
The difference in the ON timing is reduced. Since the sense unit 2 is provided to protect the main body MOSFET, it is necessary to turn on as soon as possible. If the difference in the timing of turning on is reduced, the characteristics of the sense unit 2 are improved.

【００４１】その上、センスパッド電極３ａを設けるこ
とによる、実動作領域５の無効領域を最小限に押さえら
れるのでセル密度も向上し、オン抵抗の低減に寄与でき
る。In addition, by providing the sense pad electrode 3a, the invalid area of the actual operation area 5 can be minimized, so that the cell density can be improved and the on-resistance can be reduced.

【００４２】更に、すべての電極を同じ径のボンディン
グワイヤで配線するため、作業効率も向上する。Further, since all the electrodes are wired by bonding wires having the same diameter, the working efficiency is improved.

【００４３】[0043]

【発明の効果】本発明に依れば、第１に、平坦な領域上
にセンスパッド電極を設けることにより、２’nｄボン
ドで、ワイヤを擦りつけて切断する際の衝撃によるチッ
プのクラック発生を抑制できる。According to the present invention, firstly, by providing a sense pad electrode on a flat area, a chip crack occurs due to an impact when a wire is rubbed and cut by a 2'nd bond. Can be suppressed.

【００４４】第２に、センスパッド電極をゲートパッド
電極１の近くに設け、センス部２とゲート電極の距離を
近付けることにより、それらを連結するポリシリコンで
の抵抗成分が低減されるため、オンするタイミングの差
が小さくなる。センス部２は本体ＭＯＳＦＥＴの保護用
に設けられているので、極力早くオンする必要があり、
オンするタイミングの差が縮まれば、センス部２として
の特性も向上する。Second, since the sense pad electrode is provided near the gate pad electrode 1 and the distance between the sense portion 2 and the gate electrode is reduced, the resistance component of the polysilicon connecting them is reduced. The difference between the timings of performing the operations is reduced. Since the sense unit 2 is provided for protecting the main body MOSFET, it is necessary to turn on as soon as possible.
If the difference between the ON timings is reduced, the characteristics of the sense unit 2 are also improved.

【００４５】第３に、センスパッド電極を設けることに
よる、実動作領域５の無効領域を最小限に押さえられる
のでセル密度も向上し、オン抵抗の低減に寄与できる。Third, the provision of the sense pad electrode minimizes the ineffective area of the actual operation area 5, thereby improving the cell density and contributing to the reduction of on-resistance.

【００４６】第４にすべての電極を同じ径のボンディン
グワイヤで配線するため作業効率も向上する。Fourth, since all the electrodes are wired with bonding wires having the same diameter, work efficiency is also improved.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明のＭＯＳＦＥＴを説明する平面図であ
る。FIG. 1 is a plan view illustrating a MOSFET of the present invention.

【図２】本発明の半導体装置を説明する断面図である。FIG. 2 is a cross-sectional view illustrating a semiconductor device of the present invention.

【図３】本発明のＭＯＳＦＥＴを説明する断面図であ
る。FIG. 3 is a cross-sectional view illustrating a MOSFET according to the present invention.

【図４】従来のＭＯＳＦＥＴを説明する平面図である。FIG. 4 is a plan view illustrating a conventional MOSFET.

【図５】従来の半導体装置を説明する断面図である。FIG. 5 is a cross-sectional view illustrating a conventional semiconductor device.

【図６】従来のＭＯＳＦＥＴを説明する断面図である。FIG. 6 is a cross-sectional view illustrating a conventional MOSFET.

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/60 ３０１ Ｈ０１Ｌ 21/60 ３０１Ｎ 25/065 25/08 Ｚ 25/07 25/18 Ｆターム(参考） 5F044 AA12 EE02 ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 21/60 301 H01L 21/60 301N 25/065 25/08 Z 25/07 25/18 F term (reference ) 5F044 AA12 EE02

Claims (5)

【特許請求の範囲】[Claims] 【請求項１】多数のＭＯＳトランジスタのセルを配列し
た実動作領域と、 該実動作領域上に設けられ前記ＭＯＳトランジスタの各
セルのソース領域と接続されたソース電極と、 該ソース電極と接続したソースパッド電極と、 前記ＭＯＳトランジスタの各セルのゲート電極と接続し
たゲートパッド電極と、 前記ＭＯＳトランジスタのうちの複数のセルからなるセ
ンス部と、 前記センス部に接続し前記センス部上を覆うセンス電極
と、 前記セルを設けない領域上に設けられ前記センス電極と
接続したセンスパッド電極と、 前記ソース電極、前記ゲートパッド電極および前記セン
スパッド電極にそれぞれ固着するワイヤとを具備するこ
とを特徴とするＭＯＳＦＥＴ。An actual operating region in which a number of MOS transistor cells are arranged; a source electrode provided on the actual operating region and connected to a source region of each cell of the MOS transistor; and a source electrode connected to the source electrode. A source pad electrode; a gate pad electrode connected to a gate electrode of each cell of the MOS transistor; a sense unit including a plurality of cells of the MOS transistor; and a sense connected to the sense unit and covering the sense unit. An electrode, a sense pad electrode provided on a region where the cell is not provided, and connected to the sense electrode, and wires fixed to the source electrode, the gate pad electrode, and the sense pad electrode, respectively. MOSFET. 【請求項２】前記センスパッド電極の直下は、平坦であ
ることを特徴とする請求項１記載のＭＯＳＦＥＴ。2. The MOSFET according to claim 1, wherein a portion immediately below said sense pad electrode is flat. 【請求項３】前記センスパッド電極は前記ゲートパッド
電極の近くに設けられることを特徴とする請求項１記載
のＭＯＳＦＥＴ。3. The MOSFET according to claim 1, wherein said sense pad electrode is provided near said gate pad electrode. 【請求項４】前記ＭＯＳＦＥＴは１つのパッケージ内に
コントロールＩＣと二重構造で実装されることを特徴と
する請求項１に記載のＭＯＳＦＥＴ。4. The MOSFET according to claim 1, wherein the MOSFET is mounted in a single package in a double structure with a control IC. 【請求項５】前記コントロールＩＣに固着されたワイヤ
は前記センスパッド電極に延在されて圧着し切断される
ことを特徴とする請求項１に記載のＭＯＳＦＥＴ。5. The MOSFET according to claim 1, wherein the wire fixed to the control IC extends to the sense pad electrode, and is compressed and cut.
JP2001115265A 2001-04-13 2001-04-13 MOSFET Expired - Lifetime JP5014534B2 (en)

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