JPS60128655A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS60128655A JPS60128655A JP58236161A JP23616183A JPS60128655A JP S60128655 A JPS60128655 A JP S60128655A JP 58236161 A JP58236161 A JP 58236161A JP 23616183 A JP23616183 A JP 23616183A JP S60128655 A JPS60128655 A JP S60128655A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- low
- layer
- substrate
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Description
〔発明の利用分野〕
本発明は、半導体装置、特に相補型ＭＯ８素子を用いた
ＬＳＩの電源配線の形成法に関する。
〔発明の背景〕
従来より、相補型Ｍ ＯＳ素子は、ＩＣ，ＬＳＩの基本
構成素子として用いられ、最近では特に、その低電力性
からメモリ、ランダムロジックやマイクロコンピュータ
などのＵ Ｌ Ｓ Ｉ （Ｕ］、ｔ、ｒｎＬａｒｇａ
５ｅａｌ Ｉｎｔｅｇｒｄｔｉｏｎ）に必要不可欠とな
っている。第１図は相補型ＭＯ８素子の断面構造図を示
したものである。同図において、１は０１０１Ω・印程
度の比抵抗を有する高濃度ｎ形半導体基板、２は５〜１
０Ω・印程度の比抵抗を有する低濃度ｎ形半導体基板、
３はｐ形つェル層である。通常、ｐチャネルＭＯＳトラ
ンジスタ１６は、Ｐ形不純物層５，６をソース、ドレイ
ン、１０をゲート酸化膜として構成され、ｎチャネルＭ
ＯＳトランジスタ１７は、ｎ形不純物層７，８をドレイ
ン、ソース、１１をゲート酸化膜として構成される。
１４．１５はそれぞれ１６．１７で構成したＣＭＯＳイ
ンベータ回路の入力および出力端子で、１６゜１７の基
板電位を固定するため、ｎ形基板２に対しては４なるｎ
形不純物層を設けて電源端子１３に、ｐ形つェル３に対
しては９なるｐ形不純物層を設けて接地端子１２に接続
される。
さて、このような構造をもつ相補型ＭＯ８素子でＬＳ
Ｉ、ＵＬＳ Ｉを構成して場合、最も大きな問題点は電
源配線、接地配線のチップ全体に占める割合が極めて大
きくなることである。しかも電源および接地線の配線材
料（通常アルミニムが用いられる）の幅を大きくしなけ
れば高信頼性を保ちえず、また、電源線と接地線を同一
層の同一材料で形成した場合、クロスさせることができ
ないため、必然的に集積度が低下するという欠点があっ
た。
〔発明の目的〕
本発明の目的は、上述した従来技術における問題点を克
服した電源配線の形成法を提供することにある。
〔発明の概要〕
本発明の基本概念は以下の如くである。すなわち、第１
図における１なる高濃度ｎ形半尋体基板に注目し、この
基板を電源配線の一部に使用することによって、ＬＳ
Ｉ、ＵＬＳ Ｉの電源配線ネックを解消し、直に集積度
の高い半導体装置をえることにある。
〔１明の実施例〕
以下、本発明を実施例を参照して詳細に説明する。
第２図は、本発明による半導体装置の第１の実施例の断
面構造図を示すものである。本発明の特徴は、２３なる
導電性物質で２なる半導体基板上の電源端子２０、金属
配線２１と高濃度半導体基板１を低抵抗状態で接続し、
この１を介してしＳ１内部回路、例えばＰチャネルＭ０
Ｓトランジスタ１６の電源を供給する点にある。該２３
なる導電性物質は、高濃度（６’ １０” ｃｍ−・）
の・形不純物を含むシリコン層あるいはポリシリコン層
、アルミニウム層、タングステン層など、低抵抗材料で
あればすべて本発明の目的にかなう。２２は、ｐ形不純
物層５と２３を低抵抗状態で接続するための金属配線で
５と２３だけでオーミックに近い接続かえられれば、こ
の配線は不要となる。
第３図は、本発明による半導体装置の第２の実施例を示
したものである。同図において、３０はＬＳＩチップ、
３１は電源のリード線、３２は電源のボンディングバッ
ト部、３２は電源の配線部を示し、３２．３３の下部、
すなりち半導体内は第２図で示した本発明の構造で高濃
度基板が接続された状態となっている６[Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a method for forming power supply wiring of an LSI using complementary MO8 elements. [Background of the Invention] Complementary MOS devices have traditionally been used as basic components of ICs and LSIs, and recently, due to their low power consumption, they have been used in ULSI devices such as memories, random logic, and microcomputers. ],t,rnLarga
5eal Integration). FIG. 1 shows a cross-sectional structural diagram of a complementary MO8 element. In the same figure, 1 is a high-concentration n-type semiconductor substrate having a specific resistance of about 0101 Ω·mark, and 2 is 5 to 1
A low concentration n-type semiconductor substrate having a specific resistance of about 0Ω・mark,
3 is a p-type well layer. Normally, the p-channel MOS transistor 16 is configured with P-type impurity layers 5 and 6 as a source and drain, and 10 as a gate oxide film, and an n-channel MOS transistor
The OS transistor 17 is configured with the n-type impurity layers 7 and 8 as a drain and source, and the n-type impurity layers 11 as a gate oxide film. 14.15 are the input and output terminals of the CMOS inverter circuit constituted by 16.17, respectively, and in order to fix the substrate potential of 16°17, the n of 4 for the n-type substrate 2.
For the p-type well 3, a p-type impurity layer 9 is provided and connected to the ground terminal 12. Now, with a complementary MO8 element having such a structure, LS
When configuring I, ULS I, the biggest problem is that the power supply wiring and ground wiring occupy an extremely large proportion of the entire chip. Moreover, high reliability cannot be maintained unless the width of the wiring material for the power and ground wires (usually aluminum is used) is increased, and if the power and ground wires are made of the same material on the same layer, they may cross each other. This has the disadvantage of inevitably lowering the degree of integration. [Object of the Invention] An object of the present invention is to provide a method for forming power supply wiring that overcomes the problems in the prior art described above. [Summary of the Invention] The basic concept of the present invention is as follows. That is, the first
By paying attention to the high-concentration n-type semicircular substrate 1 in the figure, and using this substrate as part of the power supply wiring, the LS
The objective is to eliminate the power supply wiring bottleneck of I and ULS I and directly obtain a semiconductor device with a high degree of integration. [First Examples] The present invention will be described in detail below with reference to Examples. FIG. 2 shows a cross-sectional structural diagram of the first embodiment of the semiconductor device according to the present invention. The feature of the present invention is that the power terminal 20 on the semiconductor substrate 2, the metal wiring 21, and the high concentration semiconductor substrate 1 are connected in a low resistance state with the conductive substance 23,
Through this 1, the S1 internal circuit, for example P channel M0
The point is to supply power to the S transistor 16. 23
The conductive substance has a high concentration (6'10" cm-・)
Any low-resistance material, such as a silicon layer or polysilicon layer, an aluminum layer, or a tungsten layer containing impurities of the type impurity, is suitable for the purpose of the present invention. Reference numeral 22 denotes a metal wiring for connecting the p-type impurity layers 5 and 23 in a low-resistance state, and if only 5 and 23 can be connected to an almost ohmic connection, this wiring becomes unnecessary. FIG. 3 shows a second embodiment of the semiconductor device according to the present invention. In the same figure, 30 is an LSI chip;
31 is the lead wire of the power supply, 32 is the bonding butt part of the power supply, 32 is the wiring part of the power supply, the lower part of 32.33,
Inside the Sunarichi semiconductor, a high-concentration substrate is connected according to the structure of the present invention shown in Figure 26.
本発明によれば、チップの下部全体が低抵抗の電源配線
となっているため、他の電源線例えば接地配線とのクロ
スを全く気にすることなく自由に素子の配置、配線を行
なうことができ、チップ集積度を飛羅的に向上させるこ
とができ、また、配線低杭の点でも、高濃度基板の比抵
抗が０．０１Ω・印で厚さ４００μｍ、１ｃｍ口を想定
すると高々１０−７Ωの低抵抗が実現でき、従来の代表
的な金属配線であるアルミニウム（抵抗値５０ｍΩ／口
）と比較して、より低抵抗で、平面上の配線領域の極め
て小さなＬＳＩが実現できる。According to the present invention, since the entire lower part of the chip is a low-resistance power supply wiring, elements can be freely arranged and wired without worrying about crossing with other power supply lines, such as ground wiring. In addition, in terms of low wiring, assuming that the resistivity of the high-concentration substrate is 0.01Ω・mark, the thickness is 400 μm, and the opening is 1 cm, the chip integration level can be dramatically improved. A low resistance of 7Ω can be achieved, and compared to aluminum (resistance value 50 mΩ/unit), which is a typical conventional metal wiring, an LSI with lower resistance and an extremely small wiring area on a plane can be realized.
第１図は、相補型ＭＯ８素子の断面図、第２図は１本発
明の実施例の断面図、第３図は、本発明の他の実施例の
平面図である。
ｌ・・・半導体基板、２・・・半導体領域、３・・・ｐ
形つェル領域、４・・・ｎ形不純物領域、５，６・・・
ｐ形不純物領域、７，８・・・ｎ形不純物領域、９・・
・ｐ形不純物領域、２０・・・電源端子、２１・・・金
属配線、２２・・・金属配線、２３・・・導電性物質、
３０・・・ＬＳＩチップ、３１・・・リード線、３２・
・・ボンデイングパツ第 １ 回
第 Ｚ 図
ｅｒ
ｚ ｚｒ ｚ
″ｆＪ ３ ヅFIG. 1 is a sectional view of a complementary MO8 element, FIG. 2 is a sectional view of one embodiment of the present invention, and FIG. 3 is a plan view of another embodiment of the present invention. l...Semiconductor substrate, 2...Semiconductor region, 3...p
type well region, 4...n type impurity region, 5, 6...
p-type impurity region, 7, 8...n-type impurity region, 9...
・P-type impurity region, 20... Power supply terminal, 21... Metal wiring, 22... Metal wiring, 23... Conductive substance,
30... LSI chip, 31... Lead wire, 32...
... Bonding Pats 1st Z Figure er z zr z ″fJ 3 ヅ
Claims (1)
チャネルＭＯＳトランジスタを形成するＣ ’Ｍ ＯＳ
構成において、該高抵抗基板内に低抵抗層を形成し、該
高抵抗基板表面の電源端子が該低抵抗層を介して該低抵
抗基板に接続され、該低抵抗基板を０Ｍ０８回路の電源
配線として用いることを特徴とする半導体装置。1. P channel and n channel in high resistance substrate on low resistance substrate
C'MOS forming a channel MOS transistor
In the configuration, a low resistance layer is formed within the high resistance substrate, a power terminal on the surface of the high resistance substrate is connected to the low resistance substrate via the low resistance layer, and the low resistance substrate is connected to the power supply wiring of the 0M08 circuit. A semiconductor device characterized in that it is used as a semiconductor device.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58236161A JPS60128655A (en) | 1983-12-16 | 1983-12-16 | Semiconductor device |
| KR1019840007910A KR850005159A (en) | 1983-12-16 | 1984-12-13 | Semiconductor integrated circuit with power supply passage to board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58236161A JPS60128655A (en) | 1983-12-16 | 1983-12-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60128655A true JPS60128655A (en) | 1985-07-09 |
Family
ID=16996669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58236161A Pending JPS60128655A (en) | 1983-12-16 | 1983-12-16 | Semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS60128655A (en) |
| KR (1) | KR850005159A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6428861A (en) * | 1987-05-01 | 1989-01-31 | Digital Equipment Corp | Cmos integrated circuit with connection parts from upper surface to substrate |
| JPS6489557A (en) * | 1987-09-30 | 1989-04-04 | Toshiba Corp | Semiconductor device |
| EP1061572A1 (en) * | 1999-06-16 | 2000-12-20 | STMicroelectronics S.r.l. | Intergrated stucture for radio frequency applications |
-
1983
- 1983-12-16 JP JP58236161A patent/JPS60128655A/en active Pending
-
1984
- 1984-12-13 KR KR1019840007910A patent/KR850005159A/en not_active Application Discontinuation
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6428861A (en) * | 1987-05-01 | 1989-01-31 | Digital Equipment Corp | Cmos integrated circuit with connection parts from upper surface to substrate |
| JPS6448454A (en) * | 1987-05-01 | 1989-02-22 | Digital Equipment Corp | Manufacture of cmos integrated circuit having connecting part to substrate on upper surface |
| JPS6489557A (en) * | 1987-09-30 | 1989-04-04 | Toshiba Corp | Semiconductor device |
| EP1061572A1 (en) * | 1999-06-16 | 2000-12-20 | STMicroelectronics S.r.l. | Intergrated stucture for radio frequency applications |
Also Published As
| Publication number | Publication date |
|---|---|
| KR850005159A (en) | 1985-08-21 |
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