JPS63124551A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS63124551A
JPS63124551A JP61271151A JP27115186A JPS63124551A JP S63124551 A JPS63124551 A JP S63124551A JP 61271151 A JP61271151 A JP 61271151A JP 27115186 A JP27115186 A JP 27115186A JP S63124551 A JPS63124551 A JP S63124551A
Authority
JP
Japan
Prior art keywords
type
film
impurity diffusion
diffusion layer
type impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61271151A
Other languages
Japanese (ja)
Other versions
JPH0671050B2 (en
Inventor
Osamu Kudo
修 工藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61271151A priority Critical patent/JPH0671050B2/en
Publication of JPS63124551A publication Critical patent/JPS63124551A/en
Publication of JPH0671050B2 publication Critical patent/JPH0671050B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To connect an n-type conductor and a p-type conductor having different conductivity types stably by using a polysilicon wiring film, by forming a high-melting-point film or a silicide film thereof at an opening part. CONSTITUTION:The following are included in the title device: an n-type silicon substrate 11; a p-type impurity diffused layer 12, which is formed on a part of said substrate; a field insulating film 13, which covers the inactive region of the substrate 1; an interlayer insulating film 14, in which an opening is provided for the p-type impurity diffused layer 12; a silicide film 15 comprising high-melting-point metal (e.g., tungsten) covering said opening part; and a polysilicon wiring film 16, which is connected in an ohmic mode to the p-type impurity diffused layer 12 through the silicide film 15 and in which n-type impurities are added. Namely, the n-type impurity diffused layer 12 and the n-type polysilicon wiring film 16 are connected through the tungsten silicide film 15 at one opening part. Thus the two conductor parts 12 and 16 can form the very stable connecting part regardless of their conductivities.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路装置に関し、特にポリシリコン
配線の構造に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to the structure of polysilicon wiring.

〔従来の技術〕[Conventional technology]

半導体集積回路装置では、例えば、基板上のp形不純物
拡散層とn形ポリシリコン配線のように導電形を互いに
異にする半導体層同志を直接に結線することは難しいの
で、このような結線が必要となった場合には従来は導電
形に支配されないアルミニウム配線が通常用いられる。
In semiconductor integrated circuit devices, it is difficult to directly connect semiconductor layers of different conductivity types, such as a p-type impurity diffusion layer on a substrate and an n-type polysilicon wiring, so such a connection is difficult. Conventionally, aluminum wiring, which is not subject to conductivity type, is typically used when necessary.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、上述の従来の配線構造によるとn形およびn形
半導体層同志の接続点に開口部がそれぞれ必要となるこ
とは勿論アルミニウム配線を混在させることとなるので
、集積密度が低下する欠点を生じる。
However, the above-mentioned conventional wiring structure requires openings at the connection points between n-type and n-type semiconductor layers, and of course requires aluminum wiring to be mixed in, resulting in a disadvantage of reduced integration density. .

本発明の目的は、上記の情況に鑑み導電形を互いに異に
するn形およびn形の半導体層をアルミニウム配線によ
らずポリシリコン配線を用いて結線し得るきわめて安定
な接続部構造を備えた半導体集積回路装置を提供するこ
とである。
In view of the above circumstances, an object of the present invention is to provide an extremely stable connection structure capable of connecting n-type and n-type semiconductor layers having different conductivity types using polysilicon wiring instead of aluminum wiring. An object of the present invention is to provide a semiconductor integrated circuit device.

〔問題点を解決するための手段〕[Means for solving problems]

本発明によれば半導体集積回路装置は、半導体基板と、
前記半導体基板Pに形成される−導電形の不純物拡散層
と、前記不純物拡散層の開口部を被覆する高融点金に膜
またはそのシリサイド膜と、前記高融点金属膜またはそ
のシリサイド膜を介し前記不純物拡散層と電気接続する
前記不純物拡散層とは逆導電形を有するポリシリコン配
線膜とを備えることを含む。
According to the present invention, a semiconductor integrated circuit device includes a semiconductor substrate;
- conductivity type impurity diffusion layer formed on the semiconductor substrate P; a high melting point gold film or its silicide film covering the opening of the impurity diffusion layer; The method includes providing a polysilicon wiring film electrically connected to the impurity diffusion layer and having a conductivity type opposite to that of the impurity diffusion layer.

〔実施例〕〔Example〕

以下図面を参照して本発明の詳細な説明する。 The present invention will be described in detail below with reference to the drawings.

第1図は本発明の一実施例を示す半導体集積回路装置の
断面図である。本実施例によれば、本発明の半導体集積
回路装置は、n形シリコン基板11と、この基板上の一
部に形成されたρ形不純物拡散層12と、基板1の不活
性領域を被覆するフィールド絶縁115113と、ρ形
不純物拡散層12に開口部を形成する層間絶縁WA14
と、この開口部を被覆する高融点金属〈例えばタングス
テン)のシリサイド膜15と、このシリサイド膜15を
介しρ形不純物拡散層12とオーム接続するn形不純物
を添加のポリシリコン配線膜16とを含む。
FIG. 1 is a sectional view of a semiconductor integrated circuit device showing one embodiment of the present invention. According to this embodiment, the semiconductor integrated circuit device of the present invention includes an n-type silicon substrate 11, a ρ-type impurity diffusion layer 12 formed on a portion of this substrate, and an inactive region of the substrate 1 that covers the n-type silicon substrate 11. Field insulation 115113 and interlayer insulation WA14 forming an opening in the ρ-type impurity diffusion layer 12
A silicide film 15 of a high melting point metal (for example, tungsten) covers this opening, and a polysilicon wiring film 16 doped with an n-type impurity is ohmically connected to the ρ-type impurity diffusion layer 12 via this silicide film 15. include.

すなわち、本実施例は、p形不純物拡散12とn形ポリ
シリコン配線膜16とが一つの開口部においてタングス
テン・シリサイドy415を介して結線されている場合
を示す、かかる配線横道によると互いに導電形を異にす
るp形不純物拡散層12とn形ポリシリコン配線lB1
16との間には高融点金属のシリサイド膜15が介在す
るので、2つの導電層は導電形の如何には全く関係なく
きわめて安定な接続部を形成する。
That is, this embodiment shows a case where the p-type impurity diffusion 12 and the n-type polysilicon wiring film 16 are connected through the tungsten silicide layer 415 in one opening. p-type impurity diffusion layer 12 and n-type polysilicon wiring lB1 with different
Since the silicide film 15 of a high melting point metal is interposed between the two conductive layers and the conductive layer 16, the two conductive layers form an extremely stable connection regardless of their conductivity type.

第2図は本発明の他の実施例を示す断面図である0本実
施例は0MO3構造の半導体集積回路に実施した場合を
示すもので、p形半導体基板21上に形成されたnチャ
ネルMO3電界効果トランジスタとフィールド絶縁膜2
3上の5OI(シリコン・オン・インシュレータ)基板
上に形成されたpチャネルMO8電界効果トランジスタ
とから成る。ここで、22.27および28はnチャネ
ルMO3電界効果トランジスタのn形不純物拡散層(ド
レイン領域)、ゲート酸化膜およびゲート電極をそれぞ
れ示し、29.30.31および32はpチャネルMO
3電界効果1ヘランジスタのチャネル領域(単結晶化さ
れたn形Sol基板)。
FIG. 2 is a cross-sectional view showing another embodiment of the present invention. This embodiment shows a case where it is implemented in a semiconductor integrated circuit with an OMO3 structure, and an n-channel MO3 formed on a p-type semiconductor substrate 21. Field effect transistor and field insulating film 2
It consists of a p-channel MO8 field effect transistor formed on a 3.5 OI (silicon-on-insulator) substrate. Here, 22.27 and 28 indicate the n-type impurity diffusion layer (drain region), gate oxide film, and gate electrode of the n-channel MO3 field effect transistor, respectively, and 29.30.31 and 32 indicate the p-channel MO3 field effect transistor.
3 Field effect 1 channel region of helangister (single crystallized n-type Sol substrate).

p形不純物拡散層(ドレイン領域)、ゲート酸化膜およ
びゲート電極をそれぞれ示している。また、24 aお
よび24bはそれぞれ第1および第2の層間絶縁膜、2
5はタングステンの如き高融点金属のシリサイド膜、2
6はn形ポリシリコン配線膜である。すなわち、本実施
例によれば、pチャネルMO9電界効果トランジスタの
ドレイン領域を形成するp形不純物拡散層30は開口部
を被覆する高融点金属のシリサイド膜25を介してn形
ポリシリコン配線膜26と接続され更にnチャネル電界
効果トランジスタのトレイン領域を形成するn形不純物
拡散層22と回路結線される。この場合においてもp形
不純物拡散層30とn形ポリシリコン配線膜26との間
には高融点金属のシリサイド膜25が介在するので2つ
の導電層は導電形の如何にかかわらずきわめて安定な接
続部を形成する。
A p-type impurity diffusion layer (drain region), a gate oxide film, and a gate electrode are shown, respectively. Further, 24a and 24b are the first and second interlayer insulating films, respectively.
5 is a silicide film of a high melting point metal such as tungsten, 2
6 is an n-type polysilicon wiring film. That is, according to this embodiment, the p-type impurity diffusion layer 30 forming the drain region of the p-channel MO9 field effect transistor is connected to the n-type polysilicon interconnection film 26 via the refractory metal silicide film 25 covering the opening. Further, a circuit connection is made to an n-type impurity diffusion layer 22 forming a train region of an n-channel field effect transistor. In this case as well, since the silicide film 25 of a high-melting point metal is interposed between the p-type impurity diffusion layer 30 and the n-type polysilicon wiring film 26, the two conductive layers have an extremely stable connection regardless of their conductivity type. form a section.

以上の実施例では何れも高融点金属のシリサイドを用い
た場合を説明したが、高融点金属の単一膜を介在させる
ことによっても、また不純物拡散層とポリシリコン配線
膜の導電形が互いに入れ換った場合でも全く同等の効果
を得ることができる。
In each of the above embodiments, a case was explained in which a high-melting point metal silicide was used, but it is also possible to interpose a single film of a high-melting point metal so that the conductivity types of the impurity diffusion layer and the polysilicon wiring film can be mutually controlled. Even if you change it, you can get exactly the same effect.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によれば、開口部に
高融点金属膜またはそのシリサイド膜を形成することに
より互いに異なる導電形のn形導体とp形導体とを付加
的な面積を使うことなしにポリシリコン配線膜を用いて
安定に結線できるので、半導体集積回路、特に相補型(
CMOS型)素子半導体装置の集積密度の向上に顕著な
る効果を奏し得る。
As explained in detail above, according to the present invention, by forming a high melting point metal film or its silicide film in the opening, an additional area is used for the n-type conductor and the p-type conductor of different conductivity types. Because it can be stably connected using a polysilicon wiring film without any problems, it is suitable for semiconductor integrated circuits, especially complementary type (
This can have a significant effect on improving the integration density of CMOS type) element semiconductor devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す半導体集積回路装置の
断面図、第2図は本発明の他の実施例を示す断面図であ
る。 11・・・n形シリコン基板、12.30・・・p形不
純物拡散層、13.23・・・フィールド絶縁膜、14
 、24 a 、 24 b−・・層間絶縁膜、16.
26・・・n形ポリシリコン配線膜、27.31・・・
ゲート酸化膜、28.32・・・ゲート電極、29川チ
ヤネル領域(単結晶化されたn形SOI基板)、21¥
5+図
FIG. 1 is a sectional view of a semiconductor integrated circuit device showing one embodiment of the invention, and FIG. 2 is a sectional view showing another embodiment of the invention. 11... N-type silicon substrate, 12.30... P-type impurity diffusion layer, 13.23... Field insulating film, 14
, 24a, 24b--interlayer insulating film, 16.
26...n-type polysilicon wiring film, 27.31...
Gate oxide film, 28.32... Gate electrode, 29 River channel region (single crystal n-type SOI substrate), 21 yen
5+ figure

Claims (1)

【特許請求の範囲】[Claims] 半導体基板と、前記半導体基板上に形成される一導電形
の不純物拡散層と、前記不純物拡散層の開口部を被覆す
る高融点金属膜またはそのシリサイド膜と、前記高融点
金属膜またはそのシリサイド膜を介し前記不純物拡散層
と電気接続する前記不純物拡散層とは逆導電形を有する
ポリシリコン配線膜とを備えることを特徴とする半導体
集積回路装置。
a semiconductor substrate, an impurity diffusion layer of one conductivity type formed on the semiconductor substrate, a high melting point metal film or its silicide film covering an opening of the impurity diffusion layer, and the high melting point metal film or its silicide film. A semiconductor integrated circuit device comprising a polysilicon wiring film having a conductivity type opposite to that of the impurity diffusion layer and electrically connected to the impurity diffusion layer through the impurity diffusion layer.
JP61271151A 1986-11-14 1986-11-14 Semiconductor integrated circuit device Expired - Lifetime JPH0671050B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61271151A JPH0671050B2 (en) 1986-11-14 1986-11-14 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61271151A JPH0671050B2 (en) 1986-11-14 1986-11-14 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS63124551A true JPS63124551A (en) 1988-05-28
JPH0671050B2 JPH0671050B2 (en) 1994-09-07

Family

ID=17496041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61271151A Expired - Lifetime JPH0671050B2 (en) 1986-11-14 1986-11-14 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0671050B2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55162224A (en) * 1979-06-06 1980-12-17 Toshiba Corp Preparation of semiconductor device
JPS57117257A (en) * 1981-01-13 1982-07-21 Nec Corp Semiconductor device
JPS58215063A (en) * 1982-06-07 1983-12-14 Toshiba Corp Semiconductor device
JPS61131558A (en) * 1984-11-30 1986-06-19 Toshiba Corp Semiconductor device
JPS62262458A (en) * 1986-05-09 1987-11-14 Seiko Epson Corp Semiconductor integrated circuit device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55162224A (en) * 1979-06-06 1980-12-17 Toshiba Corp Preparation of semiconductor device
JPS57117257A (en) * 1981-01-13 1982-07-21 Nec Corp Semiconductor device
JPS58215063A (en) * 1982-06-07 1983-12-14 Toshiba Corp Semiconductor device
JPS61131558A (en) * 1984-11-30 1986-06-19 Toshiba Corp Semiconductor device
JPS62262458A (en) * 1986-05-09 1987-11-14 Seiko Epson Corp Semiconductor integrated circuit device

Also Published As

Publication number Publication date
JPH0671050B2 (en) 1994-09-07

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