JPS58215063A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the speed-up by a method wherein double layer gate electrodes of N type poly Si in the lower layer and metal silicide in the upper layer are formed respectively on the gate oxide film and the field oxide film on a P type substrate, an N-channel MOSFET is provided on the substrate, and a P-channel one of the other gate electrode side, thus the threshold values of both are set low. CONSTITUTION:N type poly Si islands 41-43 are formed on the gate oxide film 3 the field oxide film 2 of the P type Si substrate 1, and N<+> layers 5 and 6 on the substrate 1, then covered with SiO2 7. SiO2 7' is left on the side surface of each island by reactive ion etching, covered with Mo 8 and then annealed in N2, resulting in the formation of MoSi2 91-93. The non-reacted Mo 8 is removed, and the part is covered with an SiO2 film 12, then Poly Si 13 is selectively provided on the gate electrode 103. B ions are implanted by applying a resist mask 14, and then P<+> layers 15 and 16 are formed by annealing. They are covered with an SiO2 film 17, and the electrode is added by opening an aperature. By this constitution, the N and P-channel MOSFETs having the gate electrodes 101 and 102 have threshold voltages respectively determined by the work functions of the layers 41 and 92, and both can be set low, therefore the device operated by high speed switching can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and more particularly, to an improvement of a complementary type 'v10S semiconductor device (CMo8).

[Preliminary Background of the Invention and its Problems] A CMO8''P conductor device is equipped with an n-channel Mo8 transistor and a p-channel MO3) Lannostar with the same number of conductors or the same number of insulators. and low power consumption kv.These CMOS semiconductor devices have 2
As a result, low resistance metal or metal silicide is being used instead of polycrystalline silicon as the material for gate electrodes and wiring. is used. In particular, gold oxide is stable and can withstand the heat treatment temperature (1200°C 8°C) used in the back-way process of semiconductor devices for polycrystalline silicon and concave spheres. Unlike metals, it has highly acidic properties, so
It has the characteristics of being washed and washed using sulfuric acid, salt and water, and water.

For this reason, in C-■O8 semiconductor devices, MoSi2 is used instead of polycrystalline silicon for the dart electrode.
Shaping is done with gold silicide such as. However, if other conditions are the same, such as replacing the in-type polycrystalline silicon with Mo51□, an n-channel Mo8) runnostar and an n-channel Mo8 transistor using the gate electrode as a constituent member. As shown in FIG. 1, the small direct voltages shift by about 0.7 V in both square directions. Figure 1 shows the relationship between the amount of impurity injected into the Nayan region and the current @I/-1 + hair pressure using a SiO□ term with a thickness of 500 mm as a cell constant. , Kate electrode material? It is a custom-made diagram showing a case where n-type polycrystalline silicon and Mo512 are used. As impurities mentioned above, boron was used in the n-channel Mo8 transistor, and arsenic was used in some of the p-channel transistors. 2. N1 in Fig. 1 is an n-channel Mo8 using n-type polycrystalline silicon as the gate electrode.
) Lannostar v -4H = Gu, N2 is Mo as the same
For Si2'i, I used the same transnostar's custom-made wire, and Pl used n-type polycrystalline silicon as the gate return. The same transistor used
It is d1. In this way, the difference in D, which is about 0.7 V in the square wave, is due to the fact that the n-type polycrystalline silicon, MoSi2, and the D Tsuji Yasushi function transfer are about 0.7 eV. -10,000, MOS transistor switching work? High: In order to achieve this, it is necessary to set a complete threshold retroactive pressure. Therefore, the gate pole of CA1O8 semiconductor installation is
□ If you try to form low-temperature resistance illumination, it is clear from the custom-made diagram in Figure 1 that the threshold voltage of both p-channel and n-channel: VIO8) can be set. However, the shortcoming is that high-speed excitation is often limited.

[Purpose of the invention]

The present invention reduces the resistance of the first dirt electrode of the Mo8) transistor on the semiconductor substrate side and the second dirt electrode of the MOS transistor on the side of the laminated semiconductor film to shorten the signal propagation time and to reduce the resistance of both transistors. The present invention aims to provide a semiconductor device such as a CMOS semiconductor device in which the value voltage can be set shallowly.

[Summary of the Invention] The present invention provides a first dirt electrode provided between the source and drain regions of a semiconductor substrate via a dirt oxide film, and a second dirt electrode in which a semiconductor film is laminated via an insulating film.
Laminated structure where the upper and lower surfaces are made of materials with different work functions,
For example, a two-layer structure consisting of an n-type polycrystalline silicon film (lower layer) and a metal silicide film (upper layer) is used, and the n-channel MOS transistor is placed on the semiconductor substrate side where the first dirt electrode is provided, and the second r-type electrode is placed on the semiconductor substrate side. By completely forming an n-channel Mo8) run source on the provided semiconductor film side, the n-channel Mo8)
Threshold pressure for both channel and p-channel MOS transistors? The main idea is to set it low.

[Result of invention, ground side]

An embodiment in which the present invention is applied to a zcMOs inverter will be described in detail with all the manufacturing methods shown in 2U(a) to (j1) shown in FIG.

(1) First, by selectively oxidizing the cut surface of a p-type silicon substrate 1, a field-enhancing film 2 having a thickness of, for example, 8000× was completely formed to separate the substrate 1 (as shown in FIG. 2(a)). Is it a heat ratio treatment in a murine atmosphere at 1000℃? An island-like suffocating area separated by a field J-shaped tear 2 (
If it is applied to the device area), it will be made to have a thickness of 250X to prevent the growth of the pattern 3, and will also have a thickness of 300X containing n-type impurities such as arsenic on the finished surface.
0X n-type child crystal silicon film? After depositing, this is patterned to form a layer on the oxidized ptos and a field layer.
N-type polycrystalline Noricon pattern on 02 41.4□ +4
3Th1g was selectively formed (as shown in FIG. 2(b)). Na2
An island-shaped substrate is formed before forming the n-type polyolecrystalline pattern 4L+42+43! In order to control the threshold value, ion implantation of an impurity such as Giron may be performed.

([1) Next, the n-type polycrystalline silicon pattern 41
and field oxide film 2, n-type impurity as filler layer,
For example, arsenic is accelerated at a voltage of 50 keV and at a dose of I
Ions were implanted into the p-type silicon substrate I under the conditions of 10'/art' (as shown in Figure 2(e)).Next, heat treatment was performed to activate the arsenic ion-implanted layer and form n+ type source and drain regions. 5,6 completely formed.

Continue to coat the entire surface with, for example, 2000X thick CVD-8.
A 10□ film 7 was deposited (as shown in FIG. 2(d)). after that,
The entire CVD-8IO2 film 7 was etched by the thickness of the SiO□ film 7 by reactive ion etching (RIE). At this time, as shown in FIG.
Since the 8102 film 7' was thick in the vertical direction, the 8102 film 7' remained on the peripheral side surfaces of the n-type polycrystalline silicon patterns 41 to 43.

) Next, the entire surface is coated with a thickness of, for example, 200 mm by sputtering.
0 X OMo, J d'd: Q +X L/ f
Heat treatment was performed for 15 minutes in a N2 atmosphere at 'C'm, l O01, )°C. Which samurai, n-type polycrystalline silicon pattern 41
~43 (D) Mo in contact with the exposed upper surface reacts with 7 silicon to form a MoSi2 film 91~ on the upper surface of the patterns 41~43.
93 was disgraced. In addition, in this step 2, residual S is formed on the circumferential surface of the Δ crystal silicon patterns 41 to 43 in the n-type device.
iO □) Since Han 2 exists, Mo to those j:j
Can you completely prevent the formation of Si2 film? Through this process, an n-type polycrystalline silicon pattern 41 and MoS are formed on the oxide film 3.
12 W 91 and 2 [Shinzo Den's first date 4 similar 1
θ1 is 2 films (lCn type polycrystalline converter 42 and 8 ioS i 2 rlj-9
The second cage pole lθ2 has a two-layer structure with 2, and on the same field enemy desert 2 there is a two-story structure II with nf polycrystalline reconverter 43 and MoS 12 rot 93. , which is formed as a ridge (as shown in FIG. 2(f)).

After urinating in Oψ and unreacted Dzio, the entire surface is covered with p-channel Δ-iO8) An example (-250 hole C■-3iO2 A thin film 12 was deposited (as shown in FIG. 2(g)).

Next, the entire surface is coated with a thickness of, for example, 3000× by CVD method.
After depositing a polycrystalline silicon film, the second dirt electrode 102 is patterned by photo-etching technology.
A polycrystalline silicon film pattern (semiconductor film) z, yi was selectively formed in a region on the gold-containing CVD-8IO2 thin film Z2 (as shown in FIG. 2(h)).

(V) Next, after forming a resist groove 14f covering the polycrystalline silicon film pattern I3 corresponding to the second dirt electrode 10Q and the area other than the pattern 13,
A p-type impurity, for example boron, is used as a mask for the resist pattern 14f at a total acceleration voltage of 50 keV and a dose of I.
Ions were implanted into the polycrystalline silicon film pattern I3 under the condition of X I Q"7m2 (as shown in FIG. 2 (1)). Prior to the boron ion implantation, a threshold value was applied to the polycrystalline silicon film pattern I3, which will become the channel region. For control purposes, all ions of n-type impurities such as arsenic may be implanted, or all energy beams such as laser beams may be irradiated to convert the polycrystalline silicon film pattern 13 into a monolayer crystal or to modify the crystal grains.

(li) After forming the Lennost pattern '147 and prefecture, heat treatment is performed to implant seven layers of boron ions, R is activated and polycrystalline silicon film pattern 13 is formed: P+ type source and drain regions 15. ! 6 Completely cut. Poke,
CVD-3 in 2 mo 17 with 8000 yen on the whole surface
Although the contact hole 18 was filled evenly, the contact hole 18 was completely opened.

Hiki Tsutsusa, A4. %, buttering is performed to form n+ type") source region 5, drain region 6, p+ type/D
The source region 15 and the drain region I6 are connected through contact holes 18, respectively. 9 to 22 full-scale models, they used a CMOS inverter device (see the second south (j) figure).
1 is a p-type silicon substrate l-7 as shown in FIG. 2(j).
) 4 also n+-type vertebrates, separated from each other in the insular region.

All polycrystalline silicon substrates 41 and MoSi are placed on the substrate Z region including at least the narrowed part between these source and drain regions 5 and 6.
□The film 91 and the first guard electrode xo1 having an O two-layer structure are provided through the dirt oxidation layer 3, and the n-type child crystal silicon is formed on the field 1-wave conversion film 2, which is a region other than the island region. A second gate 1102 having a two-layer structure of a pattern 42 and a MoSh 2 film 92 is provided, and a CVD-S IO2 thin film 12 is provided on the region including the second gate electrode I02.
Polycrystalline silicon film pattern throughout (semiconductor 1) 13
At the same time, the polycrystalline silicon film pattern I3 is provided with the same pattern 1 as the second gate electrode 102.
The pv source and drain regions are electrically isolated from each other in three parts. Since the electrodes tol, to
The threshold voltage of an n-channel MOS transistor whose shape is changed to 1 is the first f-) n-type child crystal/
The work function of the υcon pattern 41 is expressed as follows, while the second r-) electrode 10. CVD-8in2 thin film 12f on top
The threshold voltage of the p-channel MO8) transistor formed on the side of the polycrystalline silicon film pattern Z3 laminated via the MoSi2 film 9 on the second dirt electrode 102 is
It is determined by the work function of 2.

Therefore, as shown in the characteristic diagram of FIG. 1 described above, both the n-channel MO3) transistor and the p-channel MO8) transistor can be set to shallow threshold voltages, and high-speed switching operations can be achieved. In addition, the dirt electrode 10
1 +102 and wiring 11 are each made of MoSi in the upper layer.
Since two films 91+92+93 are formed, the sheet resistance value of these is 2-3Ω@ from 30-50ΩIIcIIL when formed only with n-type polycrystalline silicon.
α can be reduced, and signal propagation delay time can be significantly shortened.

Furthermore, an n-channel MO3) transistor is mounted on a p-type silicon substrate I with high mobility, as in the above embodiment, etc., and a p-channel MOS transistor is mounted on a laminated polycrystalline silicon film pattern I3.
Rather than constructing a CMOS inverter by integrating the transistors individually, we can use two of these transistors to form a single layer of the memory cells of the six transistors shown in Figure 3. Even if polycrystalline silicon, which has higher mobility compared to crystalline silicon films, is used as a semiconductor film,
Memory cells capable of high-speed operation can be returned.

In other words, as shown in FIG.
It is formed in the OS inverter, and the entire circuit essentially constitutes a flip-flop circuit. 27 “T-in the diagram Qn3.Qn4
The transistor QH3* is used as a transfer gate, and the transistor QH3* is turned on when the memory cell is wiped, stored, and read. Qn3+ Q
The bit line BI4.
Information is transferred between BL2 and the flip-flop circuit. For these transistors QB3 + QB4, n-channel transistors are often used from the viewpoint of increasing the operating speed. The common melain portion DI of the transistors Qpt l QHl and the common drain portion D2 of the transistor QP2 r Qnz of the FRI717071 circuit are respectively at the VDD potential, 8. It is set to a potential and retains information. For example, when the common drain portion D1 is at VDD, the transistor Qp2 is turned off, the transistor Qn2 is turned on, and the common drain portion D2 is at the ■as potential.
Therefore, transistor Qp1 is on, transistor Qn
1 is off. In addition, WL in the figure is a transfer f-
1 transistor n3. This is a word line connected to Qn4 node.

When writing all information to the above-mentioned memory cell, for example, common drain portion D1kV6B potential, common drain portion D
When setting to 2k VDD potential, bit line BL+'kVss level, bit line BL 2 k
■The first transistor Qn3 is set to the nD level and is transferred by the word line WL. Q
Turn on nl. However, the current supply capacity of the bit line BL2 is normally determined by the QOI of each transistor in the memory cell.
Qp2, Qni to QH4 are much larger, and in the case of a -1W signal, the n-channel MO8 transistor Qn3. Q
The performance of n4 will dominate.

On the other hand, in the case of reading;・Mabit line B L 1
rBLz'z Connect to the sense amplifier (not shown) and turn on the transistors Qn3 and Qn4 as transfer gates. At this time, since the impedance of the sense up circuit is the same as that of the passing light, the common drain The parts D11D2 are not completely configured, and even if the resistance when transistor Qpt or QT)2 is turned on is a little thick, the transistor Q
If the on-resistance of n1 or Qn2 is small, the n signal of the memory cell is the same as the transistor Q, □ or Q mutual QT
+2 is reversed due to its thick on-abrasive surface.Also, when the memory cell is not transparent (when information is retained), the transistor Qp+ or Qpz connected to the vDD potential is connected to the memory cell. It is sufficient that the transistor Q, 1 or Qpx has the function of compensating for the potential due to cell leakage.
It is not a problem even if the on-resistance is a little high.

Therefore, the operation of the memory cell composed of six transistors is based on the n-channel MO8) transistor Qn1 + Qn2, which is one component of the CMOS inverter, and the n-channel MO8) transistor Qn3. If the performance of Qn4 is secured, CMO
p-channel MO8) which is another component of the S inverter
Since the performance of the transistors Q and 1°Qpx is not so much of a problem, as in the above embodiment, an n-channel MO transistor (8) transistor is placed on the side of the substrate l, which has high mobility, and a p-channel MOS transistor is placed on the side of the laminated polycrystalline silicon film pattern 13, which has low mobility. It is effective to form a CMOS interface by forming transistors respectively.

Note that the semiconductor device according to the present invention is not limited to the structure shown in FIG. 2(j), but may have the structure shown in FIGS. 4 to 6, for example. However, the same material as Q25 (j))
The explanation will be omitted by adding a number.

That is, the CMOS inverter shown in FIG.
For example, MO is placed on the n+ type source and drain regions 5 and 6 of the
It has a structure that includes all of the 231°232-mounted mountains such as Si2. 2. Synthetic silicide layer 23r+2
3z'i Formation: Before depositing the Mo of the above embodiment, the n-type device 1.3z'i is formed. Live crystal recombination pattern 4rk
After removing the AJ37 as a mask and fully exposing the n+ type source and drain receivers 5 and 6, the entire surface is steamed with Mohan8 and heat treated. 42 + 43 Cutting to the top surface 08i2
It is formed simultaneously with the formation of the film 91 +92°93. According to this configuration, the n-type source and drain mi5+6
The resistance value can be reduced to a wide range, and even higher performance can be achieved. This is particularly effective when the device is patterned and the J depth of the n+ type source and drain regions 5 and 6 is reduced.

In the CMOS inverter installation shown in FIG. 5, a silicon layer 25 is grown on a device substrate, such as a sapphire substrate 24,
This silicon layer '25 has a structure in which n-type source and drain regions s/ and 6/ are provided. The CMOS inverter device shown in FIG. 6 has a CVD-3102 film by etching the entire silicon layer, whereas the inverter device shown in FIG. ! 7 etc., and a second gate electrode RO2 is placed on the sapphire substrate 24.
, and has a structure in which a direction → II is provided.

In addition, in the above embodiment, MoSi2+, i was used as the metal silicide film constituting the entire first and second gate electrodes of the RR, but the material is not limited to this, and silicides of high melting point metals such as PT, PD, W, etc. may also be used.

In the above-mentioned disaster example, the first and second key points were kumquats with a near-one-layer structure of n-type polycrystalline silicon and metal silicide, but the combination of n-type polycrystalline silicon and p-type child-crystalline silicon was used. A fake structure VC may be used.

The p-type microcrystalline silicon dirt electrode/pole is compared to the lifting platform 7ζ used for the n-type polycrystalline silicon keto electrode. By forming an n-channel MO8 transistor on the n-channel MO8) /':/nostar and a p-channel MO8 transistor on the p-type child crystal silicon side (this allows each transistor to be set to a shallow threshold voltage. -Tozom
It may also be a three-layer structure in which metal or metal silicide is interposed between kn-type subcrystalline silicon and p-type polycrystalline silicon. With such a structure, the degree of shift of threshold value≦pressure can be completely increased, and the resistance of the gate electrode can be completely reduced.

In the above embodiment, the first and second electrodes were provided separately, but the second electrode was formed by the extension of the first electrode and integrated. It's okay.

Furthermore, the semiconductor device according to the present invention has n on the semiconductor substrate (the substrate or the semiconductor layer on the 5-edge substrate) like the above-mentioned Sho Asahi fM.
Instead of forming the channel Mo3) transistor in a structure in which a p-channel MO8 transistor is formed in the stacked semiconductor films, this structure may be reversed.

The semiconductor device according to the present invention can be applied not only to a CMOS inverter device but also to an ETD inverter device in which Mo8) transistors of the same channel are formed. for example,
In the structure shown in FIG. 2 (''), the stacked semiconductor films (
If an n-channel MOS transistor similar to that on the substrate side is formed on the polycrystalline silicon film pattern), the laminated Mo8
) The threshold voltage of the transistor is shifted approximately 0.7 V in the positive direction from the characteristic diagram in Figure 2, and the
o8) The threshold voltage is higher than that of the Rannostar, and all n-channel Mos transistors on the substrate side can operate in depletion mode, and the same transistors on the semiconductor film side can operate in enhancement mode, making it possible to configure the entire ED inverter device.

[Effects of the Invention] As detailed above, according to the present invention, the total resistance of the r-) electrode can be reduced to significantly shorten the signal propagation delay time, and the n
The threshold voltage of both channel and p-channel MO8 transistors can be set shallowly, making it possible to operate at high speeds, making it suitable for use in high-volume, 100MOS inverter devices, etc.
I can do it.

[Brief explanation of drawings]

Figure 1 shows the results of ion implantation into the channel region of n-channel and p-channel Mo8 l-lannosmets using n-type molten silicon and Mo512k as r-total electrode materials. Characteristic diagram showing the relationship between A and the threshold value λ of the transistor, Fig. 2 (a) ~
(jHtA cross-sectional view showing the four-side process of a CMOS inverter device in an example of advancement of the present invention, FIG. 3 is a 6-transistor O memory cell configured using two inverters shown in FIG. 4 to 6 are cross-sectional views of a CMOS inverter device showing all other examples of the present invention. !...p-type silicon substrate, 2-field oxide film,
3...Oxide film (gate oxide film), J
, 42゜43...n-type child crystal silicon Bakoon, 5
, 5'...n+ type source region, 6,6'...n+ type drain region, 91.92.93...Mo Si
2 membranes, 10I, IOQ... dart electrode, 11...
Wiring, Z2...CVD-8in2 thin film, 13...Polycrystalline silicon film pattern (semiconductor film), 15.p+ type source region, I6...p+ type drain region, 19-22.
・-AA wiring, 231. 23,...metal silicide layer, 24...su? IA substrate, 25... silicon layer, Qn1-Qn4...n
Channel MO8) 5 registers, Q1~Qpt...
p-channel MOS transnostar, BLl, BL,...
・Bit line, WL...Word line. Applicant's Representative Patent Attorney Takehiko Tsurie' Figure 4 - Injection (XIOcm) Figure 3 Figure 4 Figure 5 Portion Figure 6

Claims (5)

[Claims] (1) A semiconductor substrate, a source and drain region provided electrically isolated from each other in an island region of the semiconductor substrate, and a region including at least a portion sandwiched between the source and drain regions Jil[. a first r-) electrode provided through one insulating film; a second dirt electrode provided on a region of the semiconductor substrate different from the island region;
A semiconductor film laminated on a region containing gold via a second insulating film, and a part of the semiconductor film provided on this semiconductor film and facing the second dirt electrode, electrically isolated from each other. 1. A semiconductor device comprising a source and a P-rain region, and having a laminated structure in which all upper and lower surfaces of the first and second dart electrodes are made of materials having different work functions. (2) The first and second r-upper electrodes have a two-layer structure of an n-type polycrystalline silicon film and a metal silicide film. Semiconductor equipment. (3) Are the first and second date electrodes made of two cores consisting of an n-type polycrystalline silicon film and a p-type subcrystalline silicon pattern? What to do'f!
: The semiconductor device according to item 1 of the range of special features with I# characteristics. (4) Are the first and second dart electrodes a polycrystalline silicon film and a p-type polycrystalline silicon film, or a metal silicide film? The semiconductor device according to claim 1, characterized in that it has a three-layer structure. (5) “OL” made of materials with different work functions
, :, l< Among the first and second gate electrodes of the structure, the first
The lower surface of the dart electrode is made of a material with a small total work function, and the half-core body on the lower surface is formed with an n-channel MOS.
A patent characterized in that a transistor is arranged, the upper surface of the M2 gate electrode is made of a material with a large total work function, and a p-channel MO8) runnostar is arranged on the half folding pattern on the upper surface side. A semiconductor device according to any one of claims 1 to 4. (6i) The semi-integrated device according to any one of the first to fifth features, characterized in that the second dart electrode is an extension of the first dart electrode.