JPS6360546B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention provides a complementary MOS integrated circuit (CMOS IC).
Manufacturing method, especially for high power supply (high withstand voltage) CMOS
The present invention relates to a method for shortening the masking process of integrated circuits, particularly silicon gate CMOS integrated circuits.

Logic gates, which incorporate complementary pairs of MOS transistors, are among the lowest power consumption logic circuits and operate at high speeds, making them ideal for large-scale integrated circuits (LSIs), batteries, etc. It is widely used in portable calculators or space engineering.

A conventional manufacturing process for a CMOS integrated circuit will be explained with reference to FIG. First, a thin wafer-shaped N-type silicon single crystal doped with phosphorus is cut out as an N-type substrate 1, the surface is polished to a mirror finish, and exposed to an oxidizing atmosphere at a high temperature of 1100°C to form a field oxide film with a thickness of about 6000 Å. A silicon oxide film 3 called . Next, a P-well is formed. This involves forming a well region pattern on the oxide film using photoresist, then etching away the oxide film in the P-well region using the photoresist as a mask, washing off the photoresist, and then patterning. The P-well layer 2 is formed by thermally diffusing boron at 1200° C. into the exposed portion. At the same time, an oxide film is formed again on the surface of the P well. In the same way as P well patterning,
The oxide film in the region is removed, boron is thermally diffused in the patterned part to form a P ⁺ type channel cut diffusion layer, and an oxide film 4 that will become a gate oxide film is grown again in that part. Furthermore, P-well
The oxide film in the N ⁺ region is removed using the same method as patterning, and phosphorus is thermally diffused into the patterned area to form an N ⁺ channel cut diffusion layer, and the area is again oxidized to become the gate oxide film. A film 4 is formed. Field oxide film ( _SiO2
The region in which the film 3) is formed (indicated by an arrow in the figure) is called a field region, and the region separated by the field region and indicated by an arrow in the figure is called a transistor region. Note that these channel cut diffusion layers are omitted from FIG. 2 onwards.

In order to control the threshold voltage V ^P _TH of the P-channel transistor, the N-channel transistor side is covered with a photoresist 5 using the first mask, and a high concentration of boron (B ⁺ ) is ion-implanted. ,
Increase V ^P _TH from -1.4V to -0.7V (Figure 2). In the figure, the dotted line indicates the limit of ion implantation. (The same applies to the following figures.) At this point, wash off the photoresist.

Next, N-type doped polysilicon 6, 7
A polysilicon film is grown to a thickness of 4000 Å and a width of 4 μm, and this polysilicon and SiO ₂ (oxide) are patterned to form gate oxide film 4 and gates 6 and 7 (Figure 3).

In order to increase the withstand voltage of the P-channel transistor, a second mask is prepared, a window is opened in the photoresist 8 only in the portion desired to be an offset gate, and boron B ⁺ ions are implanted at a low concentration (FIG. 4).

Next, using a third mask, windows were opened in the photoresist only for the highly doped source and drain portions of the P-channel transistor (indicated by S and D in the figure).
Perform boron B ⁺ ion implantation at high concentration (5th
figure).

When similar steps are performed for an N-channel transistor, the structure shown in FIG. 6 is obtained. For this purpose, two masks are used. The concentration of the N ⁺ diffusion layer near the electrode 6 is 5×10 ¹⁶ /cm ³ , and the concentration of the N ⁺⁺ diffusion layer outside it (close to the field oxide film 3) is 5×
10 ²¹ /cm ³ , the concentration of the P ⁺ diffusion layer near gate 7 is 5×
10 ¹⁷ cm ³ , and the concentration of the P ⁺⁺ diffusion layer outside it is 5×
10 ¹⁹ / ^cm3 . Five masks are used in the steps from FIG. 1 to FIG. 6. (In the case of an N-channel transistor, the threshold voltage V ^N _TH can be controlled by the P-well concentration, so no special ion implantation is required.) To complete the CMOS integrated circuit,
It is oxidized to a certain extent to form an oxide film (SiO ₂ ) 9, and the PSG
(Foosilicate glass) membrane 10
The wafer is grown to 8000 Å, an electrode window is opened, aluminum is deposited in a vacuum to cover the entire surface of the wafer, a photoresist pattern is formed, and unnecessary parts are removed by etching using this photoresist as a mask to reduce the thickness. A wiring layer 20 of 1.0 μm is formed (FIG. 7). Note that the impurity concentration in the upper right part of the P-well was 1×10 ¹⁶ /cm ³ and that of the N-type substrate was 1×10 ¹⁵ /cm ³ .

In the present invention, the above-mentioned mask process is shortened, and the method thereof will be explained with reference to FIG. 8 and subsequent figures as an example. (Same as above, the channel cut diffusion layer is not shown in FIGS. 8 and below.) The structure shown in FIG. 8 is exactly the same as the structure shown in FIG. 3, and the structure shown in FIGS. formed in the manner described with reference to it. As shown in the figure, the gate 16,
17 and a gate oxide film (SiO ₂ ) 14 are patterned. In addition, in the same figure, 11 is an N-type substrate, 1
2 is a P well, 13 is a field oxide film,
In the figure, regions indicated by arrows are a field region and a transistor region, respectively.

First, in a step using a first mask, the N-channel transistor side is covered with a photoresist 15,
When B ⁺ is implanted at 160 KeV at a dose of about 1 × 10 ¹¹ /cm ² , B ⁺ penetrates through the gate polysilicon and SiO ₂ and controls the threshold voltage V ^N _TH of the P-channel transistor (Fig. 9). ). In the figure, the dotted line indicates the limit of ion implantation. (The same applies to the following figures.) Furthermore, in order to make the P-channel transistor an offset gate, the photoresist is left as it is and B ⁺ is applied at a dose of 1× at 40 KeV.
Inject about 10 ¹³ /cm ² (Figure 10). The area above the dotted line in FIGS. 9 and 10 is the P ⁺ region.

Next, using a second mask, windows are opened in the photoresist 15' only in the highly doped source and drain portions of the P-channel transistor (indicated by S and D in the figure), and the N-channel transistor 9 and the P-channel transistor are With the offset region on the side of the guard covered, B ⁺ ions are implanted at 20 KeV and at a dose of about 1×10 ¹⁵ /cm ² (FIG. 11). After removing the photoresist, P ⁺ ions are implanted into the entire surface at a dose of about 1×10 ¹² /cm ² at 50 KeV.
This forms a low concentration region of the offset gate of the N-channel transistor. This P ⁺ ion implantation is also implanted into the offset gate portion and source/drain portion of the P channel transistor, and the dose of B ⁺ ion implantation into the offset portion of the P channel transistor is 1×10 ¹³ as described above. / ^cm2 , which is 10 times more than P ⁺ ion implantation, so it is not a problem. The dose in the highly concentrated source/drain region is 1×10 ¹⁵ cm ² , which is 100 times higher (first
Figure 2).

Next, using a third mask, a window is opened in the photoresist 25 only in the highly doped source and drain portions of the N-channel transistor, so that the P-channel transistor and the offset region next to the guard of the N-channel transistor are covered. P ⁺ ion implantation is performed at 25 KeV and at a dose of approximately 4×10 ¹⁵ /cm ² (Figure 13).

After that, in the same manner as described above with reference to FIG. 7, an oxide film is formed by oxidation, a PSG film is formed, an electrode window is opened, and wiring is performed. A gate CMOS integrated circuit is completed.

By using the process described above, compared to the conventional technology, two mask processes can be saved, the threshold voltage V ^P _TH can be controlled and the transistor can be made to withstand high voltage, and the yield can therefore be improved. It is something.

[Brief explanation of the drawing]

The attached drawings are cross-sectional views of the manufacturing process of a silicon gate CMOS integrated circuit, and FIGS. 1 to 7 are cross-sectional views of the manufacturing process according to the prior art, and FIGS. 8 to 13 are cross-sectional views of the manufacturing process of a silicon gate CMOS integrated circuit. FIG. 3 is a cross-sectional view of an example. 1, 11...N type board, 5, 8, 15, 15',
25...Resist, 2, 12...P well, 6,
7, 16, 17... Gate, 3, 13... Field oxide film, 9... Oxide film, 4, 14... Gate oxide film, 10... PSG film, 20... Wiring layer.

Claims (1)

[Claims] 1. A CMOS having a field region, a first transistor region whose channel is one conductivity type, and a second transistor region whose channel is the opposite conductivity type.
A method for manufacturing an integrated circuit, comprising: forming a field oxide film separating each of the transistor regions in the field region of a semiconductor substrate of one conductivity type; and introducing impurities of an opposite conductivity type into the first transistor region. a step of forming a well region; a step of forming gates in the first and second transistor regions; and after forming a first mask covering the first transistor region, a step of forming a gate at a predetermined energy and concentration. a first ion implantation step of ion-implanting a conductivity type impurity using the gate as a mask to form an offset region for the second transistor region; Using a second mask covering the second transistor region, impurities of the opposite conductivity type are ion-implanted at a higher concentration than in the first ion implantation step to form highly-concentrated source and drain regions of the second transistor region. a second ion implantation step; after removing the mask on the first transistor region, one conductivity type impurity is ion-implanted at a lower concentration than in the second ion implantation step to offset the first transistor region; ion implantation of one conductivity type impurity using a second mask covering the second transistor region and the offset region of the first transistor region; a fifth ion implantation step for forming highly doped source and drain regions of the first transistor region.
A method of manufacturing integrated circuits. 2 The energy and concentration listed at the beginning are respectively
B ⁺ 160KeV and about 1×10 ¹¹ /cm ² , and the second listed one is B ⁺ 40KeV and about 1×10 ¹³ /cm ² , respectively.
The third one is about 1×10 ¹⁵ /cm2, and the fourth one is about 1×10 15 /cm ²
The first one listed is As ⁺ or P ⁺ 1×10 ¹² / ^cm2 , and the last one listed is As ⁺ or P ⁺ 4×10 ¹⁵ /cm2.
2. The method according to claim 1, characterized in that the temperature is about cm ² .