JPS5743456A - Manufacture of cmos integrated circuit - Google Patents

Manufacture of cmos integrated circuit

Info

Publication number
JPS5743456A
JPS5743456A JP55119323A JP11932380A JPS5743456A JP S5743456 A JPS5743456 A JP S5743456A JP 55119323 A JP55119323 A JP 55119323A JP 11932380 A JP11932380 A JP 11932380A JP S5743456 A JPS5743456 A JP S5743456A
Authority
JP
Japan
Prior art keywords
photoresist
steps
ions
channel mosfet
injected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55119323A
Other languages
Japanese (ja)
Other versions
JPS6360546B2 (en
Inventor
Katsuyuki Inayoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55119323A priority Critical patent/JPS5743456A/en
Publication of JPS5743456A publication Critical patent/JPS5743456A/en
Publication of JPS6360546B2 publication Critical patent/JPS6360546B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce to number of masking steps by employing the same photoresist in the steps of injecting ions for controlling a threshold voltage and for enhancing the withstand voltage. CONSTITUTION:In an N type substrate having a P type well 12, gate polysilicons 16, 17 and oxidized films 13, 14, the first mask is provided and a photoresist 15 is covered on the N-channel side, B<+> ions are injected, and the threshold voltage of a P-channel MOSFET is controlled. Then, the photoresist 15 remains as it is, B<+> ions are injected, and P-channel MOSFET is formed in an off-set gate. Windows are opened only at the high density source and drain of the photoresist 15 in the P- channel MOSFET, and B<+> ions are injected. In this manner, one masking step can be decreased in the steps of manufacturing the P-channel MOSFET, and one masking step can also be decreased in the steps of the N-channel side.
JP55119323A 1980-08-29 1980-08-29 Manufacture of cmos integrated circuit Granted JPS5743456A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55119323A JPS5743456A (en) 1980-08-29 1980-08-29 Manufacture of cmos integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55119323A JPS5743456A (en) 1980-08-29 1980-08-29 Manufacture of cmos integrated circuit

Publications (2)

Publication Number Publication Date
JPS5743456A true JPS5743456A (en) 1982-03-11
JPS6360546B2 JPS6360546B2 (en) 1988-11-24

Family

ID=14758611

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55119323A Granted JPS5743456A (en) 1980-08-29 1980-08-29 Manufacture of cmos integrated circuit

Country Status (1)

Country Link
JP (1) JPS5743456A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62149163A (en) * 1985-08-30 1987-07-03 Nec Corp Manufacture of complementary mos integrated circuit
JPH06310528A (en) * 1993-12-24 1994-11-04 Toshiba Corp Manufacture of mos type semiconductor device of mask ldd structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62149163A (en) * 1985-08-30 1987-07-03 Nec Corp Manufacture of complementary mos integrated circuit
JPH06310528A (en) * 1993-12-24 1994-11-04 Toshiba Corp Manufacture of mos type semiconductor device of mask ldd structure

Also Published As

Publication number Publication date
JPS6360546B2 (en) 1988-11-24

Similar Documents

Publication Publication Date Title
JPS5743456A (en) Manufacture of cmos integrated circuit
JPS57192063A (en) Manufacture of semiconductor device
JPS54113278A (en) Selective wiring in lsi
JPS6442853A (en) Manufacturing process of cmos device
JPS57107067A (en) Manufacture of semiconductor device
JPS55101058A (en) Detection circuit for operating lowest limit voltage
JPS56164570A (en) Semiconductor memory unit
JPS55121666A (en) Mos transistor circuit
JPS5448179A (en) Mis-type semiconductor integrated circuit device
JPS56103536A (en) Mis output circuit
JPS5725726A (en) Synchronous decoder
JPS5538019A (en) Manufacturing of semiconductor device
JPS5784164A (en) Manufacture of semiconductor device
JPS56162874A (en) Manufacture of mos semiconductor device
JPS6464364A (en) Semiconductor device and its manufacture
JPS57120371A (en) Manufacture of complementary type mos semiconductor
JPS5649561A (en) Complementary mos ic device and its process of preparation
JPS56100478A (en) Semiconductor device and manufacture thereof
JPS57100767A (en) Mos type semiconductor device
JPS5745969A (en) Mis type semiconductor integrated circuit device
JPS5377182A (en) Production of mos type semiconductor device
JPS5715467A (en) Manufacture of ccd
JPS5799768A (en) Manufacture of complementary type metal oxide semiconductor device
JPS54112180A (en) Manufacture of complementary type insulation gate field effect semiconductor device
JPS52147983A (en) Insulation gate type semiconductor device