JPS6464364A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPS6464364A
JPS6464364A JP62220226A JP22022687A JPS6464364A JP S6464364 A JPS6464364 A JP S6464364A JP 62220226 A JP62220226 A JP 62220226A JP 22022687 A JP22022687 A JP 22022687A JP S6464364 A JPS6464364 A JP S6464364A
Authority
JP
Japan
Prior art keywords
depletion
drain
channel
mode
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62220226A
Other languages
Japanese (ja)
Other versions
JP2550092B2 (en
Inventor
Akihiro Shimizu
Naotaka Hashimoto
Toshiaki Yamanaka
Yoshio Sakai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi ULSI Engineering Corp
Hitachi Ltd
Original Assignee
Hitachi ULSI Engineering Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi ULSI Engineering Corp, Hitachi Ltd filed Critical Hitachi ULSI Engineering Corp
Priority to JP62220226A priority Critical patent/JP2550092B2/en
Publication of JPS6464364A publication Critical patent/JPS6464364A/en
Application granted granted Critical
Publication of JP2550092B2 publication Critical patent/JP2550092B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To execute an operation with good reliability by using a conventional power-supply voltage by a method wherein a depletion-mode region is formed in a self-aligned manner at ends of a source and a drain of a channel in an MIS-type transistor of an LDD structure. CONSTITUTION:In an LDD structure having a low-concentration layer 5 in a source and a drain, a threshold voltage near the source and the drain of a channel is set to a depletion mode. Because depletion-mode layers 4 exist at both ends of the channel, a symmetrical operation like a transfer gate is possible. In the case of a driver MOS such as an inverter or the like, only a drain side is sufficient. In addition, when punchthrough stopper layers 16 are added and the depletion-mode layers 4 are formed, boron is implanted into a substrate at higher energy. In addition, the punchthrough stopper layers 16 are formed on a whole face inside the substrate 1; by this setup, high reliability is realized; a short-channel effect such as a punchthrough or the like can be reduced.
JP62220226A 1987-09-04 1987-09-04 Semiconductor device and manufacturing method thereof Expired - Fee Related JP2550092B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62220226A JP2550092B2 (en) 1987-09-04 1987-09-04 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62220226A JP2550092B2 (en) 1987-09-04 1987-09-04 Semiconductor device and manufacturing method thereof

Publications (2)

Publication Number Publication Date
JPS6464364A true JPS6464364A (en) 1989-03-10
JP2550092B2 JP2550092B2 (en) 1996-10-30

Family

ID=16747859

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62220226A Expired - Fee Related JP2550092B2 (en) 1987-09-04 1987-09-04 Semiconductor device and manufacturing method thereof

Country Status (1)

Country Link
JP (1) JP2550092B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216272A (en) * 1990-04-13 1993-06-01 Nippondenso Co., Ltd. High withstanding voltage MIS transistor
US5594264A (en) * 1994-12-16 1997-01-14 Mitsubishi Denki Kabushiki Kaisha LDD semiconductor device with peak impurity concentrations
US5606191A (en) * 1994-12-16 1997-02-25 Mosel Vitelic, Inc. Semiconductor device with lightly doped drain regions

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5216272A (en) * 1990-04-13 1993-06-01 Nippondenso Co., Ltd. High withstanding voltage MIS transistor
US5342802A (en) * 1990-04-13 1994-08-30 Nippondenso Co., Ltd. Method of manufacturing a complementary MIS transistor
US5594264A (en) * 1994-12-16 1997-01-14 Mitsubishi Denki Kabushiki Kaisha LDD semiconductor device with peak impurity concentrations
US5606191A (en) * 1994-12-16 1997-02-25 Mosel Vitelic, Inc. Semiconductor device with lightly doped drain regions

Also Published As

Publication number Publication date
JP2550092B2 (en) 1996-10-30

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