JPS5799768A - Manufacture of complementary type metal oxide semiconductor device - Google Patents

Manufacture of complementary type metal oxide semiconductor device

Info

Publication number
JPS5799768A
JPS5799768A JP55175301A JP17530180A JPS5799768A JP S5799768 A JPS5799768 A JP S5799768A JP 55175301 A JP55175301 A JP 55175301A JP 17530180 A JP17530180 A JP 17530180A JP S5799768 A JPS5799768 A JP S5799768A
Authority
JP
Japan
Prior art keywords
drain
source
channel
high temperature
shaped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55175301A
Other languages
Japanese (ja)
Inventor
Takeshi Tanaka
Haruo Kaneko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP55175301A priority Critical patent/JPS5799768A/en
Publication of JPS5799768A publication Critical patent/JPS5799768A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the shortening of a channel by treating a source and a drain of a P channel FET at a high temperature so to be proper to the diffusion of B after completing treatment at a high temperature for forming a source and a drain of an N channel FET. CONSTITUTION:A P well 2 is shaped to an N type Si substrate through the diffusion of B, and separated by oxide films 4, a gate oxide film 51 and gate electrodes 61, 62 are formed selectively, and the surface is coated with poly Si 8 to which As is added. The whole is treated at a high temperature in an oxidizing atmosphere, the N<+> source and drain 9, 10 are shaped, and the layer 8 is changed into an As added oxide film. The layer 8 is removed, the electrodes are coated with oxide films 11, a resist mask 12 is formed, B ion injecting layers 131, 132 are shaped selectively, thermally treated and activated, and the P<+> source and drain layers 14, 15 are molded. According to this constitution, the CMOS, which has predetermined threshold voltage and drain dielectric resistance and works at high speed even when each FET is fined, is obtained because the P<+> layers 41, 15 can be formed shallowly and the shortening of the channel of the P channel FET can be inhibited.
JP55175301A 1980-12-12 1980-12-12 Manufacture of complementary type metal oxide semiconductor device Pending JPS5799768A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55175301A JPS5799768A (en) 1980-12-12 1980-12-12 Manufacture of complementary type metal oxide semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55175301A JPS5799768A (en) 1980-12-12 1980-12-12 Manufacture of complementary type metal oxide semiconductor device

Publications (1)

Publication Number Publication Date
JPS5799768A true JPS5799768A (en) 1982-06-21

Family

ID=15993697

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55175301A Pending JPS5799768A (en) 1980-12-12 1980-12-12 Manufacture of complementary type metal oxide semiconductor device

Country Status (1)

Country Link
JP (1) JPS5799768A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57167680A (en) * 1981-04-08 1982-10-15 Matsushita Electric Ind Co Ltd Manufacture of complementary mis field-effect transistor
JPS6477956A (en) * 1987-09-19 1989-03-23 Nec Corp Manufacture of complementary mos transistor

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57167680A (en) * 1981-04-08 1982-10-15 Matsushita Electric Ind Co Ltd Manufacture of complementary mis field-effect transistor
JPS6477956A (en) * 1987-09-19 1989-03-23 Nec Corp Manufacture of complementary mos transistor

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