JPS6477956A - Manufacture of complementary mos transistor - Google Patents

Abstract

PURPOSE:To prevent the effect of heat treatment at a high temperature, to avoid a punch-through phenomenon and to miniaturize a transistor by implanting an impurity for controlling a threshold after a high-temperature heat treatment process for activating an impurity for source-drain diffusion layers. CONSTITUTION:Gate polysilicon electrodes 6 are formed selectively. An N-type diffusion layer 8 in source-drain regions is shaped. A substrate is thermally treated at a high temperature for activating an arsenic impurity forming the N-type diffusion layer 8. P-type impurity implanting layers 11 for controlling a threshold are shaped onto the surfaces of activating regions in the lower sections of gate insulating oxide films 5. The N-type diffusion layer 8 for source- drain is formed, the N-type diffusion layer 8 is thermally treated at a high temperature and activated, and ions are implanted by energy through which the gate electrodes 6 and the gate insulating oxide films 5 are permeated, thus shaping the P-type impurity implanting layer 11 for controlling the threshold. Accordingly, the impurity implanting layers 11 are not affected by heat treatment at a high temperature.