JPH04113634A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04113634A JPH04113634A JP23353090A JP23353090A JPH04113634A JP H04113634 A JPH04113634 A JP H04113634A JP 23353090 A JP23353090 A JP 23353090A JP 23353090 A JP23353090 A JP 23353090A JP H04113634 A JPH04113634 A JP H04113634A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- gate electrode
- forming
- source
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 239000012535 impurity Substances 0.000 claims abstract description 15
- 238000009792 diffusion process Methods 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 19
- 150000002500 ions Chemical class 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 6
- 239000010410 layer Substances 0.000 abstract description 36
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 12
- 229910052710 silicon Inorganic materials 0.000 abstract description 12
- 239000010703 silicon Substances 0.000 abstract description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 4
- 229910052796 boron Inorganic materials 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 4
- 229910052785 arsenic Inorganic materials 0.000 abstract description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 abstract description 3
- 239000011229 interlayer Substances 0.000 abstract description 3
- 238000005468 ion implantation Methods 0.000 description 14
- 238000000206 photolithography Methods 0.000 description 6
- 230000001133 acceleration Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 230000004913 activation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 101001003569 Homo sapiens LIM domain only protein 3 Proteins 0.000 description 1
- 102100026460 LIM domain only protein 3 Human genes 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明ζ友 ソース−ドレイン間のバンチスルー現象の
抑制を目的とした不純物拡散領域を有する半導体装置の
製造方法に関すも
従来の技術
半導体装置は微細化にともない様々な問題点が出てきて
い、Ｌ ＭＯ３構造の半導体装置における問題点のひ
とつにソース−ドレイン間のバンチスルー現象があム
この現象（よ ゲート長が短くなるとソース−ドレイン
間の耐圧が低下し チャネルが形成されていなくてもソ
ース−ドレイン間にリーク電流が流れるようになるもの
である。この現象を抑制するために有効な方法として、
ゲート電極下の比較的深い（ソースまたはドレイン接合
の深さ程度）部分に基板不純物濃度の高い領域（以下、
バンチスルーストップ拡散層と称する）を形成すること
が従来から提案されていも 以下にバンチスルーストッ
プ拡散層形成の従来例について説明すも
第２図（ａ）〜（ｄ）は従来の半導体装置の製造方法を
示す工程断面図である。例えばＰ型シリコン基板１の上
にフィールド絶縁膜２およびゲート酸化膜３を形成した
後、バンチスルーストップ拡散層５形成のための例えば
ほう素（Ｂ）のイオン注入を行う（第２図（ａ））。こ
のイオン注入の加速エネルギーと注入量は後で形成する
ソースまたはドレイン拡散層とＰ型シリコン基板ｌとの
接合（ソースまたはドレイン接合）の深さと同程度の深
さにおける不純物濃度がＰ型シリコン基板ｌの不純物濃
度に比べて十分に高くなるように設定されも またここ
ではパンチスルーストップ拡散層５の形成により、Ｐ型
シリコン基板１の表面の不純物濃度も制御する。すなわ
ちパンチスルーストップ拡散層５形成のイオン注入がし
きい値電圧の設定の役割を兼用するとしだ力（別に表面
濃度設定のための浅いイオン注入を行う場合もあムイオ
ン注入後、ゲート酸化膜３の上の一部にゲート電極４を
形成する（第２図（ｂ））。ゲート電極４をマスクに自
己整合的にソースおよびドレイン形成のための例えばひ
素（Ａｓ）のイオン注入が行われ その後の活性化のた
めの熱処理によってソースおよびドレイン拡散層６が形
成される（第２図（Ｃ））。その後、層間絶縁膜７の形
成と配線８の形成が行われ トランジスタが完成する（
第２図（ｄ））。DETAILED DESCRIPTION OF THE INVENTION Industrial Field of Application This invention relates to a method for manufacturing a semiconductor device having an impurity diffusion region for the purpose of suppressing the bunch-through phenomenon between source and drain. Various problems have arisen with the advancement of semiconductor technology, and one of the problems with semiconductor devices with the LMO3 structure is the bunch-through phenomenon between the source and drain.
When the gate length becomes shorter, the withstand voltage between the source and drain decreases, and leakage current begins to flow between the source and drain even if a channel is not formed.It is effective to suppress this phenomenon. As a method,
A region with high substrate impurity concentration (hereinafter referred to as
Although it has been proposed in the past to form a bunch-through stop diffusion layer (referred to as a bunch-through stop diffusion layer), a conventional example of forming a bunch-through stop diffusion layer will be explained below. It is a process sectional view showing a manufacturing method. For example, after forming a field insulating film 2 and a gate oxide film 3 on a P-type silicon substrate 1, ions of boron (B), for example, are implanted to form a bunch-through stop diffusion layer 5 (see FIG. 2(a). )). The acceleration energy and implantation amount of this ion implantation are such that the impurity concentration at a depth similar to the depth of the junction (source or drain junction) between the source or drain diffusion layer and the P-type silicon substrate l, which will be formed later, is determined in the P-type silicon substrate. Here, the impurity concentration on the surface of the P-type silicon substrate 1 is also controlled by forming the punch-through stop diffusion layer 5. In other words, if the ion implantation to form the punch-through stop diffusion layer 5 also serves as the threshold voltage setting, then the gate oxide film 3 A gate electrode 4 is formed on a part of the electrode (FIG. 2(b)). Using the gate electrode 4 as a mask, ions of, for example, arsenic (As) are implanted in a self-aligned manner to form a source and a drain. A source and drain diffusion layer 6 is formed by heat treatment for activation (FIG. 2(C)). After that, an interlayer insulating film 7 and a wiring 8 are formed, and the transistor is completed (
Figure 2(d)).
以上に述べた製造方法によって作製されたトランジスタ
においてＣＬ ソース−ドレイン間のソスまたはドレ
イン接合の深さと同程度の深さの領域においてＰ型シリ
コン基板ｌの不純物濃度が高くなるので、ソースまたは
ドレインからチャネル領域への空乏層の広がりが抑えら
れ パンチスルー現象を抑制することが可能とな本
発明が解決しようとする課題
しかしながら上記従来の構成では 一般に複数種のトラ
ンジスタを集積する半導体装置の製造において、パンチ
スルーストップ拡散層を形成するためのイオン注入時に
他のトランジスタをフォトレジスト等で覆っておく必要
があり、そのためにフォトリソグラフィー工程を必要と
すも この工程が半導体装置の製造工程に占める割合は
大きく、できるだけフォトリソグラフィー工程を省略す
ることが要求されていも またパンチスルーストップ拡
散層の不純物プロファイルＣよ 不純物のイオン注入条
件とその後の熱処理による拡散とにより決定され イオ
ン注入後の高温での熱履歴が少ないほうが制御性良くプ
ロファイルを設定できる。In the transistor manufactured by the manufacturing method described above, the impurity concentration of the P-type silicon substrate l is high in a region with a depth comparable to the depth of the sos or drain junction between the CL source and drain, so that The problem to be solved by the present invention is that the spread of the depletion layer into the channel region can be suppressed and the punch-through phenomenon can be suppressed. During ion implantation to form the punch-through stop diffusion layer, it is necessary to cover other transistors with photoresist, etc., and this requires a photolithography process.The proportion of this process in the manufacturing process of semiconductor devices is Although it is required to omit the photolithography process as much as possible, the impurity profile C of the punch-through stop diffusion layer is determined by the impurity ion implantation conditions and the diffusion by subsequent heat treatment, and the thermal history at high temperature after ion implantation. The smaller the number, the better the controllability and the profile can be set.
しかしながら上記従来の構成で（よ イオン注入後、ゲ
ート酸化膜形成工程やゲート電極形成工程等の高温での
熱処理を必要とし 制御性よく不純物のプロファイルを
設定できないという課題を有していた
本発明は上記従来の課題を解決するもので、製造方法を
簡略化し かつ制御性良く不純物プロファイルを設定で
き、パンチスルーストップ拡散層を有する半導体装置の
製造方法を提供することを目的とすも
課題を解決するための手段
この目的を達成するために本発明の半導体装置の製造方
法ζよ ゲート電極形成後 半導体基板主面の法線との
なす角度が望ましくは１０度以上の入射角度で、ゲート
電極に対して少なくともソースとなる領域側およびドレ
インとなる領域側の両側か収 半導体基板と同一導電型
の拡散層を形成するためのイオンを注入し パンチスル
ーストップ拡散層を形成するものである。However, the present invention has the problem that the conventional configuration described above requires high-temperature heat treatment in the gate oxide film formation process, gate electrode formation process, etc. after ion implantation, and it is not possible to set the impurity profile with good controllability. The purpose of this invention is to provide a method for manufacturing a semiconductor device having a punch-through stop diffusion layer, which simplifies the manufacturing method, allows setting the impurity profile with good control, and solves the above-mentioned conventional problems. Means for Achieving this Object In order to achieve this object, the method for manufacturing a semiconductor device according to the present invention is used. After forming the gate electrode, the angle of incidence with respect to the normal to the main surface of the semiconductor substrate is preferably 10 degrees or more, with respect to the gate electrode. A punch-through stop diffusion layer is formed by implanting ions to form a diffusion layer of the same conductivity type as that of the semiconductor substrate.
作用
この構成によって、ゲート電極形成後にパンチスルース
トップ拡散層を形成することになるので、ソースおよび
ドレイン拡散層形成のためのイオン注入時にパンチスル
ーストップ拡散層形成のためのイオン注入ができも す
なわ顎 ソースおよびドレイン形成用のフォトリソグラ
フィー工程がパンチスルーストップ拡散層形成用にも兼
用することができ、パンチスルーストップ拡散層形成を
目的とするフォトリソグラフィー工程が不要となａまた
パンチスルーストップ拡散層がゲート電極形成までの高
温の熱処理を受けな（一
実施例
以下本発明の一実施例における半導体装置の製造方法を
第１図（ａ）〜（ｅ）を参照しながら説明すも
例えばＰ型シリコン基板ｌの上にフィールド絶縁膜２、
例えば膜厚１０ｎｍのゲート酸化膜３を形成した後、例
えば膜厚３００ｎｍの多結晶シリコンを減圧ＣＶＤ法に
より堆積し 燐（Ｐ）をド−ブレ フォトリソグラフィ
ー法とドライエツチング法によりゲート電極４を形成す
る（第１図（ａ））。次に ソースおよびドレイン拡散
層形成のためのフォトレジストマスクを他種のトランジ
スタ領域に形成した後、第１図（ｂ）、 （ｃ）に示す
ようにほう素（Ｂ）のイオン注入をＰ型シリコン基板ｌ
ａ主面の法線に対して例えば４５度の入射角度かつ紙面
（ゲート幅方向に垂直な面）に並行な方向でゲート電極
の左右か収 例えば加速エネルギー５０ｋｅＶ、注入量
４ ｘ １０１２ｃｍ−’で行う。このようにＰ型シリ
コン基板ｌの面に対して斜めにイオン注入することによ
り、ゲート長しがたとえば０．３μｍの場合には ゲー
ト電極４の下のチャネル領域すべてに不純物濃度の高い
拡散層すなわちパンチスルーストップ拡散層５が形成さ
れることになる。さらに ひ素（Ａ ｓ ）のイオン注
入をたとえばＰ型シリコン基板ｌに垂直な入射方向で、
加速エネルギー４０ｋｅＶ、注入量４ Ｘ １０”
ｃｍ−２で行（＼ ソースおよびドレイン拡散層６を形
成する。フォトレジストを除去した後に 例えば８５０
ｔ、 ３０分の熱処理を施すことにより、パンチスル
ーストップ拡散層５、ソースおよびドレイン拡散層６の
注入イオンが活性化される（第１図（ｄ））。その後、
層間絶縁膜７の形成と配線８の形成が行われ トランジ
スタが完成する（第１図（ｅ））。Effect: With this configuration, the punch-through stop diffusion layer is formed after the gate electrode is formed, so that the ion implantation for forming the punch-through stop diffusion layer can be performed at the same time as the ion implantation for forming the source and drain diffusion layers. The photolithography process for forming the source and drain can also be used for forming the punch-through stop diffusion layer, eliminating the need for the photolithography process aimed at forming the punch-through stop diffusion layer. (For example, P-type Field insulating film 2 on silicon substrate l,
For example, after forming a gate oxide film 3 with a thickness of 10 nm, polycrystalline silicon with a thickness of 300 nm, for example, is deposited by a low pressure CVD method, doped with phosphorus (P), and a gate electrode 4 is formed by photolithography and dry etching. (Figure 1(a)). Next, after forming a photoresist mask for forming the source and drain diffusion layers in the other type of transistor region, boron (B) ion implantation is performed as shown in FIGS. 1(b) and 1(c). silicon substrate l
a. At an incident angle of, for example, 45 degrees with respect to the normal to the main surface and in a direction parallel to the plane of the paper (a plane perpendicular to the gate width direction), the left and right sides of the gate electrode are focused. conduct. By implanting ions obliquely to the surface of the P-type silicon substrate 1 in this way, when the gate length is, for example, 0.3 μm, the entire channel region under the gate electrode 4 is filled with a diffusion layer with a high impurity concentration, i.e. A punch-through stop diffusion layer 5 will be formed. Furthermore, arsenic (As) ions are implanted, for example, in the direction perpendicular to the P-type silicon substrate l.
Acceleration energy 40keV, implantation amount 4 x 10”
cm-2 to form the source and drain diffusion layer 6. After removing the photoresist, for example 850
By performing heat treatment for 30 minutes, the implanted ions in the punch-through stop diffusion layer 5 and the source and drain diffusion layers 6 are activated (FIG. 1(d)). after that,
The interlayer insulating film 7 and the wiring 8 are formed, and the transistor is completed (FIG. 1(e)).
な耘 本実施例ではイオン注入を４５度の入射角度で行
った例について説明したカミ チャネル長、加速電圧
総注入量、イオンの種類によってイオン注入の入射角度
を変更する必要があム また入射角度を浅くすると不純
物のゲート下横方向への入り込みが少なくなるため濃度
を上げる必要が出てくる力（高濃度イエン打ち込みにな
ると欠陥の回復 活性率の向上等新たな問題が出てくる
。またある入射角度の下でイオンが奥深く到達するチャ
ネル効果を避けるためにはイオン注入の入射角度は１０
度以上が望まし賎
以上のように本実施例によれζＬ ゲート長りに対して
ほう素（Ｂ）の注入角度および加速エネルギーを適切に
設定することにより、ゲート電極４の形成後にゲート電
極４の下にパンチスルーストップ拡散層５を形成するこ
とができる。This example describes an example in which ion implantation was performed at an incident angle of 45 degrees.Channel length, acceleration voltage
It is necessary to change the incident angle of ion implantation depending on the total implantation amount and the type of ions. Also, if the incidence angle is made shallower, impurities will be less likely to enter laterally under the gate, so it will be necessary to increase the concentration. When implanting concentrated yen, new problems arise such as defect recovery and improvement of activation rate.Also, in order to avoid the channel effect where ions reach deep under a certain incidence angle, the incidence angle of ion implantation must be 10.
By appropriately setting the implantation angle and acceleration energy of boron (B) with respect to the gate length, the gate electrode 4 can be A punch-through stop diffusion layer 5 can be formed underneath.
な耘 以上に述べた実施例においてｉＬ Ｐ型シリコ
ン基板１の上のＮチャネルトランジスタの製造方法につ
いて述べた力＜Ｎ型シリコン基板上のＰチャネルトラン
ジスタに本実施例を適用することも可能であム
発明の効果
以上のように本発明によれ（戯 パンチスルーストップ
拡散層形成のためのフォトリソグラフィー工程が省略可
能となるた八 製造工程が簡略化されも またパンチス
ルーストップ拡散層の形成のためのイオン注入がゲート
電極形成後に行われるた数 イオン注入後の高温での熱
処理が従来の方法に比べて少なくなり、不純物のプロフ
ァイルの制御性が良くなａ したがって本発明の実用的
効果は太き（ｔIn the embodiment described above, it is also possible to apply this embodiment to a P-channel transistor on an N-type silicon substrate. Effects of the Invention As described above, the present invention makes it possible to omit the photolithography process for forming the punch-through stop diffusion layer. The number of ion implantations performed after forming the gate electrode is less than that required for high-temperature heat treatment after ion implantation compared to conventional methods, and the controllability of impurity profiles is improved.A Therefore, the practical effects of the present invention are significant. (t
第１図（ａ）〜（ｅ）は本発明の一実施例における半導
体装置の製造方法を示す工程断面図 第２図（ａ）〜（
ｄ）は従来の半導体装置の製造方法を示す工程断面図で
ある。
１・・・Ｐ型シリコン基板（−導電型半導体基板）、４
・・・ゲート電極 ５・・・パンチスルーストップ拡散
層（半導体基板と同一導電型の拡散層）、 ６・・・ソ
ースおよびドレイン拡散層（半導体基板とは反対導電型
の拡散層）。
代理人の氏名 弁理士 小鍜治 明 ほか２名Ｃ１
城FIGS. 1(a) to (e) are process cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 2(a) to (e)
d) is a process cross-sectional view showing a conventional method for manufacturing a semiconductor device. 1...P-type silicon substrate (-conductive type semiconductor substrate), 4
... Gate electrode 5... Punch-through stop diffusion layer (diffusion layer of the same conductivity type as the semiconductor substrate), 6... Source and drain diffusion layer (diffusion layer of the opposite conductivity type to the semiconductor substrate). Name of agent: Patent attorney Akira Okaji and two others C1 Jyo
Claims (1)
ゲート電極に対して少なくともソースとなる領域側およ
びドレインとなる領域側の両側から斜め方向に前記半導
体基板と同一導電型の拡散層を形成するための第一の不
純物イオンを注入する工程と、前記半導体基板とは反対
導電型の拡散層を形成する第二の不純物イオンを注入す
る工程と、前記第一および第二の不純物イオンを注入し
た後に熱処理を施す工程とを有する半導体装置の製造方
法。After forming a gate electrode on a semiconductor substrate of one conductivity type, a diffusion layer of the same conductivity type as the semiconductor substrate is formed diagonally from both sides of at least the source region and the drain region with respect to the gate electrode. a step of implanting a first impurity ion to form a diffusion layer of a conductivity type opposite to that of the semiconductor substrate; and a step of implanting the first and second impurity ions. 1. A method for manufacturing a semiconductor device, the method comprising the step of performing heat treatment after the above steps.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23353090A JPH04113634A (en) | 1990-09-03 | 1990-09-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23353090A JPH04113634A (en) | 1990-09-03 | 1990-09-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04113634A true JPH04113634A (en) | 1992-04-15 |
Family
ID=16956490
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23353090A Pending JPH04113634A (en) | 1990-09-03 | 1990-09-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04113634A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5543337A (en) * | 1994-06-15 | 1996-08-06 | Lsi Logic Corporation | Method for fabricating field effect transistor structure using symmetrical high tilt angle punchthrough implants |
| EP0970513A2 (en) * | 1996-12-30 | 2000-01-12 | Intel Corporation | Well boosting threshold voltage rollup |
| JP2006165524A (en) * | 2004-11-05 | 2006-06-22 | Infineon Technologies Ag | High-frequency switching transistor and high-frequency circuit |
| US9314961B2 (en) | 2001-05-31 | 2016-04-19 | 3M Innovative Properties Company | Processes and apparatus for making transversely drawn films with substantially uniaxial character |
| US10350818B2 (en) | 2005-04-08 | 2019-07-16 | 3M Innovative Properties Company | Heat setting optical films |
-
1990
- 1990-09-03 JP JP23353090A patent/JPH04113634A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5543337A (en) * | 1994-06-15 | 1996-08-06 | Lsi Logic Corporation | Method for fabricating field effect transistor structure using symmetrical high tilt angle punchthrough implants |
| EP0970513A2 (en) * | 1996-12-30 | 2000-01-12 | Intel Corporation | Well boosting threshold voltage rollup |
| EP0970513A4 (en) * | 1996-12-30 | 2000-01-12 | Intel Corp | Well boosting threshold voltage rollup |
| US9314961B2 (en) | 2001-05-31 | 2016-04-19 | 3M Innovative Properties Company | Processes and apparatus for making transversely drawn films with substantially uniaxial character |
| JP2006165524A (en) * | 2004-11-05 | 2006-06-22 | Infineon Technologies Ag | High-frequency switching transistor and high-frequency circuit |
| JP4579134B2 (en) * | 2004-11-05 | 2010-11-10 | インフィネオン テクノロジーズ アクチエンゲゼルシャフト | High frequency switching transistor and high frequency circuit |
| US8525272B2 (en) | 2004-11-05 | 2013-09-03 | Infineon Technologies Ag | High-frequency switching transistor and high-frequency circuit |
| US10350818B2 (en) | 2005-04-08 | 2019-07-16 | 3M Innovative Properties Company | Heat setting optical films |
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