JPH0466379B2 - - Google Patents
Info
- Publication number
- JPH0466379B2 JPH0466379B2 JP11189886A JP11189886A JPH0466379B2 JP H0466379 B2 JPH0466379 B2 JP H0466379B2 JP 11189886 A JP11189886 A JP 11189886A JP 11189886 A JP11189886 A JP 11189886A JP H0466379 B2 JPH0466379 B2 JP H0466379B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- bonding layer
- forming
- shallow
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- -1 silicon ions Chemical class 0.000 claims description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052736 halogen Inorganic materials 0.000 claims description 3
- 150000002367 halogens Chemical class 0.000 claims description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
【発明の詳細な説明】
＜産業上の利用分野＞
本発明は、半導体装置に用いられる浅い接合層
の形成方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for forming a shallow bonding layer used in a semiconductor device.
＜従来の技術＞
半導体装置に用いられるp+、n+接合層は、素
子の微細化に伴い、浅くすることが要求されてい
る。従来は、イオン注入後、電気炉アニールを行
う方式で、制御性よく接合層が形成されてきた。<Prior Art> P + and n + junction layers used in semiconductor devices are required to be shallower as elements become smaller. Conventionally, a bonding layer has been formed with good controllability by performing electric furnace annealing after ion implantation.
＜発明が解決しようとする問題点＞
しかしながら、今後要求される0.1μｍ以下の良
好な接合層を形成することは、イオン注入装置の
低エネルギー化の限界、軽質量ボロンを用いるこ
とによる飛程圧縮の困難性、アニール制御性の問
題等から非常に困難になつている。<Problems to be Solved by the Invention> However, forming a good bonding layer of 0.1 μm or less, which will be required in the future, is at the limit of reducing the energy of ion implantation equipment and reducing the range by using low-mass boron. It has become extremely difficult due to the difficulty of processing and problems with annealing controllability.
それ故に、本発明の目的は、素子の微細化に伴
う短チヤネル効果等の悪影響の防止の為に、浅い
接合層の形成方法を提供することにある。 Therefore, an object of the present invention is to provide a method for forming a shallow bonding layer in order to prevent adverse effects such as the short channel effect accompanying miniaturization of elements.
＜問題点を解決するための手段＞
半導体基板にシリコン・イオンを注入し、導電
性不純物源となるPSG膜又はBSG膜を付着し、
ハロゲン・ランプを用いて加熱することにより、
リン又はボロンを半導体基板中に拡散して、浅い
接合層を形成する。<Means to solve the problem> Silicon ions are implanted into the semiconductor substrate, a PSG film or BSG film is attached as a source of conductive impurities,
By heating with a halogen lamp,
Phosphorus or boron is diffused into the semiconductor substrate to form a shallow bonding layer.
シリコン・イオンの注入を使う目的は、シリコ
ン基板に0.1μｍ程度の浅いアモルフアス層を形成
することにある。アモルフアス層は赤外線の吸収
が大きく、その部分だけ速く昇温し、不純物が拡
散できるからである。 The purpose of using silicon ion implantation is to form a shallow amorphous layer of about 0.1 μm in a silicon substrate. This is because the amorphous layer has a large absorption of infrared rays, and the temperature of that part increases quickly, allowing impurities to diffuse.
＜実施例＞
以下、本発明をMOSトランジスタ製造方法に
適用した場合について述べる。<Example> Hereinafter, a case will be described in which the present invention is applied to a MOS transistor manufacturing method.
第２図は本発明を用いて製造したMOSトラン
ジスタの断面構造図、第１図ａ乃至ｇは製造工程
図である。 FIG. 2 is a cross-sectional structural diagram of a MOS transistor manufactured using the present invention, and FIGS. 1a to 1g are manufacturing process diagrams.
まず、ｎ型のシリコン基板１を熱酸化して、そ
の表面に600Åの酸化膜（SiO2膜）２を形成する
（第１図ａ）。続いて、シリコン窒化膜３を堆積
し、パターンを形成する（第１図ｂ）。次に、フ
イールド酸化膜４を形成し、シリコン窒化膜３を
除去する（第１図ｃ）。次に、ポリシリコンを
4500Å堆積し、不要部をエツチングして、ゲート
電極５を形成した後、シリコン・イオンを
70keV、３×1015ions／cm2注入する（第１図ｄ）。
続いて、ソース、ドレイン部の酸化膜を除去し、
BSG膜（1500Å）６を付着させ、ハロゲン・ラ
ンプにより加熱拡散させると、拡散層（ソース、
ドレイン領域）７が形成される（第１図ｅ）。ポ
リシリコン・ゲート５、シリコン基板１、フイー
ルド酸化膜４及びゲート酸化膜４′との選択性の
高い方法でエツチングして、BSG膜６を除去し、
続いて、Si界面での準位密度の小さい清浄な熱酸
化膜（図示せず）を形成し、その上にNSG膜８
を堆積させ、コンタクト孔９を形成する（第１図
ｆ）。ソース、ドレイン用アルミニウム電極１０
を形成すればｐチヤネルMOSトランジスタが製
造できる（第１図ｇ）。 First, an n-type silicon substrate 1 is thermally oxidized to form an oxide film (SiO 2 film) 2 of 600 Å on its surface (FIG. 1a). Subsequently, a silicon nitride film 3 is deposited to form a pattern (FIG. 1b). Next, a field oxide film 4 is formed and the silicon nitride film 3 is removed (FIG. 1c). Next, polysilicon
After depositing 4500 Å and etching unnecessary parts to form the gate electrode 5, silicon ions are deposited.
Inject 70 keV and 3×10 15 ions/cm 2 (Figure 1d).
Next, remove the oxide film on the source and drain parts,
A BSG film (1500 Å) 6 is deposited and heated and diffused with a halogen lamp to create a diffusion layer (source,
A drain region) 7 is formed (FIG. 1e). The BSG film 6 is removed by etching with a method that is highly selective to the polysilicon gate 5, the silicon substrate 1, the field oxide film 4, and the gate oxide film 4';
Next, a clean thermal oxide film (not shown) with low level density at the Si interface is formed, and an NSG film 8 is formed on top of it.
is deposited to form a contact hole 9 (FIG. 1f). Aluminum electrode 10 for source and drain
By forming this, a p-channel MOS transistor can be manufactured (Fig. 1g).
ｐ型の基板を使い、PSG膜を用いれば、ｎチ
ヤネルMOSトランジスタを作ることもできる。 By using a p-type substrate and a PSG film, it is also possible to create an n-channel MOS transistor.
なお、ゲート電極としては、ポリシリコンの他
に高融点金属又はそのシリサイド、更にはポリサ
イドが使用できる。また、基板としては、エピタ
キシヤル基板、及びｐウエルやｎウエルを形成し
た基板等が使用できる。 Note that as the gate electrode, in addition to polysilicon, a high melting point metal or its silicide, or even polycide can be used. Further, as the substrate, an epitaxial substrate, a substrate on which a p-well or an n-well is formed, etc. can be used.
前記PSG膜或いはBSG膜の膜厚、PSG膜中の
リン濃度、BSG膜中のボロン濃度、前記シリコ
ン・イオンの注入量及び注入エネルギーにより、
拡散層の濃度を接合深さを制御することができ
る。 Depending on the thickness of the PSG film or BSG film, the phosphorus concentration in the PSG film, the boron concentration in the BSG film, the implantation amount and implantation energy of the silicon ions,
The concentration of the diffusion layer can be controlled by the junction depth.
＜発明の効果＞
以上詳細に説明したように、本発明は、シリコ
ン・イオンの注入によつて形成された浅いアモル
フアス層の選択加熱を利用して浅い接合層を形成
することを特徴とするものであり、今後、要求さ
れる0.1μｍ程度以下の浅い良好な接合層の形成に
於いて極めて有用な技術を提供するものである。<Effects of the Invention> As explained in detail above, the present invention is characterized in that a shallow bonding layer is formed by selectively heating a shallow amorphous layer formed by silicon ion implantation. This provides an extremely useful technique for forming a shallow and good bonding layer of about 0.1 μm or less, which will be required in the future.
第１図は製造工程図、第２図は断面構造図であ
る。
符号の説明、１：シリコン基板、２：酸化膜、
３：シリコン窒化膜、４：フイールド酸化膜、
４′：ゲート酸化膜、５：ゲート電極、６：BSG
膜、７：拡散層、８：NSG膜、９：コンタクト
孔、１０：ソース、ドレイン用アルミニウム電
極。
FIG. 1 is a manufacturing process diagram, and FIG. 2 is a cross-sectional structural diagram. Explanation of symbols, 1: silicon substrate, 2: oxide film,
3: Silicon nitride film, 4: Field oxide film,
4': Gate oxide film, 5: Gate electrode, 6: BSG
film, 7: diffusion layer, 8: NSG film, 9: contact hole, 10: aluminum electrode for source and drain.
Claims (1)
電性不純物源となるPSG膜又はBSG膜を付着し、
ハロゲン・ランプを用いて加熱することにより、
リン又はボロンを半導体基板中に拡散して、浅い
接合層を形成することを特徴とする、浅い接合層
の形成方法。1. Inject silicon ions into a semiconductor substrate, attach a PSG film or BSG film to serve as a source of conductive impurities,
By heating with a halogen lamp,
A method for forming a shallow bonding layer, the method comprising forming a shallow bonding layer by diffusing phosphorus or boron into a semiconductor substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11189886A JPS62266829A (en) | 1986-05-14 | 1986-05-14 | Formation of shallow junction layer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11189886A JPS62266829A (en) | 1986-05-14 | 1986-05-14 | Formation of shallow junction layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62266829A JPS62266829A (en) | 1987-11-19 |
| JPH0466379B2 true JPH0466379B2 (en) | 1992-10-23 |
Family
ID=14572897
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11189886A Granted JPS62266829A (en) | 1986-05-14 | 1986-05-14 | Formation of shallow junction layer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62266829A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0644559B2 (en) * | 1987-09-04 | 1994-06-08 | 株式会社東芝 | Method for manufacturing semiconductor integrated circuit |
| JPH0291932A (en) * | 1988-09-28 | 1990-03-30 | Fujitsu Ltd | Manufacture of semiconductor device |
| JP2810947B2 (en) * | 1990-01-19 | 1998-10-15 | 日本電信電話株式会社 | Method for manufacturing semiconductor device |
| JPH04245424A (en) * | 1991-01-30 | 1992-09-02 | Nippon Precision Circuits Kk | Manufacture of semiconductor device |
| WO1997013273A1 (en) * | 1995-10-04 | 1997-04-10 | Intel Corporation | Formation of source/drain from doped glass |
| JPWO2014064873A1 (en) * | 2012-10-22 | 2016-09-08 | シャープ株式会社 | Manufacturing method of semiconductor device |
-
1986
- 1986-05-14 JP JP11189886A patent/JPS62266829A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62266829A (en) | 1987-11-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |