JPH04245424A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH04245424A JPH04245424A JP1010191A JP1010191A JPH04245424A JP H04245424 A JPH04245424 A JP H04245424A JP 1010191 A JP1010191 A JP 1010191A JP 1010191 A JP1010191 A JP 1010191A JP H04245424 A JPH04245424 A JP H04245424A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon oxide
- silicon substrate
- impurity atoms
- oxide layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 239000012535 impurity Substances 0.000 claims abstract description 32
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 239000007789 gas Substances 0.000 claims abstract description 13
- 238000000137 annealing Methods 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims abstract description 6
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910001882 dioxygen Inorganic materials 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 7
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 abstract description 4
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 abstract description 2
- 239000012495 reaction gas Substances 0.000 abstract 1
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- 239000000370 acceptor Substances 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、半導体装置における不
純物拡散層の製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an impurity diffusion layer in a semiconductor device.
【0002】0002
【従来の技術】MOSトランジスタのソ−ス・ドレイン
やバイポ−ラトランジスタのエミッタを構成する不純物
拡散層を形成する場合、従来はイオン注入法や気相また
は液相での熱拡散法により不純物の導入を行っていた。[Prior Art] When forming an impurity diffusion layer constituting the source/drain of a MOS transistor or the emitter of a bipolar transistor, impurities are conventionally formed by ion implantation or thermal diffusion in a vapor or liquid phase. It was being introduced.
【0003】0003
【発明が解決しようとする課題】素子を微細化する場合
、シュリンク則に基いて、浅い不純物拡散層を形成する
必要がある。しかしながら、上記従来の方法では浅い不
純物拡散層を形成することが困難であった。[Problems to be Solved by the Invention] When miniaturizing elements, it is necessary to form shallow impurity diffusion layers based on the shrink law. However, with the above conventional method, it is difficult to form a shallow impurity diffusion layer.
【0004】本発明の目的は、浅い不純物拡散層を形成
することが可能な半導体装置の製造方法を提供すること
である。An object of the present invention is to provide a method for manufacturing a semiconductor device that allows formation of a shallow impurity diffusion layer.
【0005】[0005]
【課題を解決するための手段】本発明に係わる半導体装
置の製造方法は、シリコン基板上に、開口部を有し不純
物の侵入を阻止するマスク層を形成する工程と、不純物
原子を有する反応ガスおよび酸素ガスを含むガス雰囲気
中でランプアニ−ル処理を行うことにより、上記開口部
における上記シリコン基板の表面に上記不純物原子を含
む酸化シリコン層を形成する工程と、高温雰囲気中で熱
処理を行うことにより、上記酸化シリコン層に含まれる
上記不純物原子を上記シリコン基板に拡散して不純物拡
散層を形成する工程とからなる。[Means for Solving the Problems] A method for manufacturing a semiconductor device according to the present invention includes the steps of forming a mask layer having openings on a silicon substrate to prevent the intrusion of impurities, and a reactive gas containing impurity atoms. and a step of forming a silicon oxide layer containing the impurity atoms on the surface of the silicon substrate in the opening by performing lamp annealing treatment in a gas atmosphere containing oxygen gas, and performing heat treatment in a high temperature atmosphere. The step of diffusing the impurity atoms contained in the silicon oxide layer into the silicon substrate to form an impurity diffusion layer.
【0006】[0006]
【実施例】図1(A)〜(D)は、実施例の製造工程を
模式的に示した断面図である。EXAMPLE FIGS. 1A to 1D are cross-sectional views schematically showing the manufacturing process of an example.
【0007】1はシリコン基板、2は酸化シリコンを用
いたマスク層、3はマスク層2に形成された開口部、4
は不純物原子を含む酸化シリコン層、5は不純物拡散層
である。1 is a silicon substrate, 2 is a mask layer using silicon oxide, 3 is an opening formed in the mask layer 2, and 4 is a mask layer made of silicon oxide.
5 is a silicon oxide layer containing impurity atoms, and 5 is an impurity diffusion layer.
【0008】つぎに、図1(A)〜(D)にしたがって
製造工程の説明をする。Next, the manufacturing process will be explained with reference to FIGS. 1(A) to 1(D).
【0009】(A)シリコン基板1の主表面側に、開口
部3を有するマスク層2を形成する。このマスク層2に
は酸化シリコンが用いられ、その層厚は後述の拡散工程
において不純物のシリコン基板1への拡散を十分に阻止
できる厚さ、例えば数百nm程度にする。(A) A mask layer 2 having an opening 3 is formed on the main surface side of the silicon substrate 1. Silicon oxide is used for this mask layer 2, and its layer thickness is set to a thickness that can sufficiently prevent impurities from diffusing into the silicon substrate 1 in a diffusion process to be described later, for example, about several hundred nanometers.
【0010】(B)ホスフィン(PH3 )やジボラン
(B2 H6 )等の反応ガスおよび酸素(O2 )ガ
スを含むガス雰囲気中(反応ガスの割合は酸素ガスに対
して10モル%程度)で、ランプアニ−ラを用いたラン
プアニ−ル処理を行う。反応ガスとしては、ホスフィン
やジボラン以外にも、ドナ−やアクセプタとなる不純物
原子を有するガスを適宜用いることができる。ランプア
ニ−ル処理は、1000〜1150度Cの温度で数秒〜
数十秒程度行う。このランプアニ−ル処理により、開口
部3におけるシリコン基板1の表面に、高濃度の不純物
原子を含んだ酸化シリコン層4(層厚数十nm程度)が
形成される。(B) In a gas atmosphere containing a reactive gas such as phosphine (PH3) or diborane (B2H6) and oxygen (O2) gas (the proportion of the reactive gas is about 10 mol% to the oxygen gas), the lamp animate - Perform lamp annealing using a laser. As the reactive gas, in addition to phosphine and diborane, gases containing impurity atoms that serve as donors and acceptors can be used as appropriate. Lamp annealing is performed at a temperature of 1000 to 1150 degrees Celsius for several seconds.
Do this for about ten seconds. By this lamp annealing process, a silicon oxide layer 4 (layer thickness of about several tens of nanometers) containing a high concentration of impurity atoms is formed on the surface of the silicon substrate 1 in the opening 3.
【0011】(C)アルゴン(Ar)等の不活性ガス雰
囲気中で熱処理を行うことにより、酸化シリコン層4か
らシリコン基板1に不純物原子の固相拡散を行う。熱処
理はファ−ネスアニ−ルあるいはランプアニ−ルにより
行う。この熱処理により、厚さ100nm程度の浅い不
純物拡散層5が形成される。(C) Solid-phase diffusion of impurity atoms from the silicon oxide layer 4 to the silicon substrate 1 is performed by performing heat treatment in an inert gas atmosphere such as argon (Ar). The heat treatment is performed by furnace annealing or lamp annealing. Through this heat treatment, a shallow impurity diffusion layer 5 with a thickness of about 100 nm is formed.
【0012】(D)フッ酸を用いたウエットエッチング
法やエッチバック法を用いて、酸化シリコン層4を除去
する。このとき同時に、マスク層2の表面側も同程度の
厚さエッチングされる。(D) The silicon oxide layer 4 is removed using a wet etching method using hydrofluoric acid or an etch-back method. At this time, the surface side of the mask layer 2 is also etched to a similar thickness.
【0013】以上のようにして形成された不純物拡散層
5は、MOSトランジスタのソ−ス・ドレインやバイポ
−ラトランジスタのエミッタ等に用いることができる。The impurity diffusion layer 5 formed as described above can be used as a source/drain of a MOS transistor, an emitter of a bipolar transistor, etc.
【0014】[0014]
【発明の効果】本発明によれば、不純物原子を有する反
応ガスおよび酸素ガスを含むガス雰囲気中でランプアニ
−ル処理を行うことにより酸化シリコン層を形成し、こ
の酸化シリコン層からの固相拡散により不純物原子をシ
リコン基板に拡散して不純物拡散層を形成するため、浅
い不純物拡散層を形成することが可能である。According to the present invention, a silicon oxide layer is formed by performing lamp annealing treatment in a gas atmosphere containing a reactive gas containing impurity atoms and oxygen gas, and solid-phase diffusion from this silicon oxide layer is achieved. Since impurity atoms are diffused into the silicon substrate to form an impurity diffusion layer, it is possible to form a shallow impurity diffusion layer.
【図1】図1(A)〜(D)は、実施例の製造工程を模
式的に示した断面図である。FIG. 1A to FIG. 1D are cross-sectional views schematically showing the manufacturing process of an example.
1……シリコン基板 2……マスク層 3……開口部 4……酸化シリコン層 5……不純物拡散層 1...Silicon substrate 2...Mask layer 3...Opening 4...Silicon oxide layer 5... Impurity diffusion layer
Claims (1)
物の侵入を阻止するマスク層を形成する工程と、不純物
原子を有する反応ガスおよび酸素ガスを含むガス雰囲気
中でランプアニ−ル処理を行うことにより、上記開口部
における上記シリコン基板の表面に上記不純物原子を含
む酸化シリコン層を形成する工程と、高温雰囲気中で熱
処理を行うことにより、上記酸化シリコン層に含まれる
上記不純物原子を上記シリコン基板に拡散して不純物拡
散層を形成する工程とからなる半導体装置の製造方法。Claim 1: Forming a mask layer having an opening on a silicon substrate to prevent impurities from entering, and performing lamp annealing in a gas atmosphere containing a reactive gas containing impurity atoms and oxygen gas. By forming a silicon oxide layer containing the impurity atoms on the surface of the silicon substrate in the opening and performing heat treatment in a high temperature atmosphere, the impurity atoms contained in the silicon oxide layer are removed from the silicon. A method for manufacturing a semiconductor device comprising the step of forming an impurity diffusion layer by diffusing into a substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1010191A JPH04245424A (en) | 1991-01-30 | 1991-01-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1010191A JPH04245424A (en) | 1991-01-30 | 1991-01-30 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04245424A true JPH04245424A (en) | 1992-09-02 |
Family
ID=11740930
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1010191A Pending JPH04245424A (en) | 1991-01-30 | 1991-01-30 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04245424A (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62266829A (en) * | 1986-05-14 | 1987-11-19 | Sharp Corp | Formation of shallow junction layer |
JPS6453413A (en) * | 1987-08-25 | 1989-03-01 | Fuji Electric Co Ltd | Formation of impurity diffusion layer |
-
1991
- 1991-01-30 JP JP1010191A patent/JPH04245424A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62266829A (en) * | 1986-05-14 | 1987-11-19 | Sharp Corp | Formation of shallow junction layer |
JPS6453413A (en) * | 1987-08-25 | 1989-03-01 | Fuji Electric Co Ltd | Formation of impurity diffusion layer |
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