JPH04291729A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04291729A
JPH04291729A JP5530891A JP5530891A JPH04291729A JP H04291729 A JPH04291729 A JP H04291729A JP 5530891 A JP5530891 A JP 5530891A JP 5530891 A JP5530891 A JP 5530891A JP H04291729 A JPH04291729 A JP H04291729A
Authority
JP
Japan
Prior art keywords
diffusion
forming
coating
temperature
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5530891A
Other languages
Japanese (ja)
Inventor
Tetsumasa Okamoto
岡本 哲昌
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP5530891A priority Critical patent/JPH04291729A/en
Publication of JPH04291729A publication Critical patent/JPH04291729A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a forming method for emitter and base layers of an ultrahigh speed bipolar Tr particularly necessary for a shallow junction in the method for forming a shallow diffused layer. CONSTITUTION:This invention has a step of reacting oxide of B, P, As of n-type and P-type impurities as coating diffusion sources with organic polymer to be polymerized, dissolving it in an alcoholic organic solvent, and coating a silicon substrate therewith; a step of baking it in an oxygen atmosphere at 200 deg.C or lower diffusing temperature to form an impurity layer (e.g. B2O3), and a step of diffusing it in a low temperature region at 900 deg.C or lower for several seconds - several tens min, are provided. A distribution depth is eliminated at a diffusion starting point due to a low temperature diffusion from the diffusion source, and hence possibility of shallow junction is high as well. This method is used for forming an emitter and a base of a bipolar transistor to desire to remarkably improve performance and yield of the transistor.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は、浅い拡散層の形成方法
に関し、特に、浅い接合を必要とする超高速バイポーラ
・トランジスタのエミッタ及びベース層の形成方法に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming shallow diffusion layers, and more particularly to a method for forming emitter and base layers of ultrafast bipolar transistors requiring shallow junctions.

【0002】0002

【従来の技術】従来、半導体中にドーパントを導入する
方法としては、熱拡散法及びイオン注入法がよく知られ
ている。しかし、5インチ以上の大口径ウェハーに対し
ては、熱拡散法は、ウェハーの面内均一性が悪く、イオ
ン注入法が主流となっている。
2. Description of the Related Art Conventionally, thermal diffusion and ion implantation are well known methods for introducing dopants into semiconductors. However, for large diameter wafers of 5 inches or more, the thermal diffusion method has poor in-plane uniformity of the wafer, and the ion implantation method has become mainstream.

【0003】このイオン注入法により、浅い接合を形成
する方法としては、一般に、例えばボロンの場合、B+
 より重いBF2 + イオンを用いて、低加速電圧で
注入する方法とあらかじめ、Si+ あるいはGe+ 
イオンを注入して、シリコン基板の表面をアモルファス
化した後、低加速電圧で注入する方法が研究されてきた
[0003] Generally speaking, in the case of boron, for example, B +
A method of implanting heavier BF2 + ions at a low acceleration voltage and a method of implanting Si+ or Ge+ ions in advance
Research has been conducted on a method in which ions are implanted to make the surface of a silicon substrate amorphous, and then implanted at a low acceleration voltage.

【0004】更に、他の方法としては、ドーパントを含
んだプラズマを作り、プラズマ中に生成したドーパント
イオンをイオンシース等により引出し、シリコン基板中
に打ち込むプラズマドーピング法や、B2 H6 (ジ
ボラン)ガス中にエキシマレーザを照射し、レーザ光に
より表面に吸着したB2 H6 を分解するとともに、
溶融シリコン基板表面にドープするエキシマレーザドー
プ法が研究されている。
Furthermore, other methods include plasma doping, in which a plasma containing a dopant is created, the dopant ions generated in the plasma are drawn out using an ion sheath, etc., and implanted into a silicon substrate; is irradiated with an excimer laser, the B2 H6 adsorbed on the surface is decomposed by the laser light, and
An excimer laser doping method in which the surface of a molten silicon substrate is doped has been studied.

【0005】[0005]

【発明が解決しようとする課題】この従来の浅い接合の
形成方法であるイオン注入法では、導入された不純物イ
オンの活性化やイオン注入時のダメージ回復のために、
注入後高温アニールが不可欠である。このアニールのた
め、0.1μm以下という極浅い拡散層の形成は不可能
となっている。また、もし高温アニールが不十分でダメ
ージが回復していなければ、リーク電流の発生による特
性劣化が生じてしまう問題がある。また、イオン注入を
より低加速電圧化することは、ドープの面内均一性を悪
化する原因となる。
[Problems to be Solved by the Invention] In the ion implantation method, which is the conventional method for forming shallow junctions, in order to activate the introduced impurity ions and recover damage during ion implantation,
A high temperature anneal after implantation is essential. This annealing makes it impossible to form an extremely shallow diffusion layer of 0.1 μm or less. Furthermore, if the high temperature annealing is insufficient and the damage is not recovered, there is a problem that characteristics may deteriorate due to the generation of leakage current. Furthermore, lowering the acceleration voltage for ion implantation causes deterioration of in-plane doping uniformity.

【0006】また、プラズマドーピング法及びエキシマ
レーザドープ法は、確かに極浅い拡散層の形成は可能で
あるがドープ深さ(Xj)と表面濃度(Ns)を独立に
制御することが困難でしかも現在のところドープの面内
均一性が悪いこと、表面濃度が高く、制御性が悪いこと
等いくつもの問題点をかかえている。
Furthermore, although plasma doping and excimer laser doping are capable of forming extremely shallow diffusion layers, it is difficult to independently control the doping depth (Xj) and surface concentration (Ns). At present, there are many problems such as poor in-plane doping uniformity, high surface concentration, and poor controllability.

【0007】[0007]

【課題を解決するための手段】本発明の浅い接合の形成
方法は、塗布拡散源としてそれぞれn型,P型不純物で
あるB,P,Asの酸化物(例えば、B2 O3 ,P
2 O5 等)を有機性高分子と反応させてポリマー化
し、アルコール系溶媒に溶解させたものを用い、シリコ
ン基板上に塗布する工程とその後、200℃以上、拡散
温度以下の酸素雰囲気中で焼成し、不純物層(B2 O
3 等)を形成する工程と、850℃以下という低温領
域で数秒〜数十分拡散を行う工程を有している。
[Means for Solving the Problems] The shallow junction forming method of the present invention uses oxides of B, P, and As (for example, B2 O3, P
2 O5, etc.) with an organic polymer and dissolved in an alcoholic solvent, the process of applying the polymer onto a silicon substrate, followed by baking in an oxygen atmosphere at a temperature of 200°C or higher and lower than the diffusion temperature. and the impurity layer (B2O
3 etc.) and a step of performing diffusion at a low temperature of 850° C. or lower for several seconds to several tens of minutes.

【0008】[0008]

【実施例】次に、本発明の一実施例として不純物として
ボロンを含有する塗布拡散源(例えば東京応化株式会社
製ポリ・ボロン・フィルム(PBF))を用いた例につ
いて断面図を参照して説明する。
[Example] Next, as an example of the present invention, an example using a coating diffusion source containing boron as an impurity (for example, poly boron film (PBF) manufactured by Tokyo Ohka Co., Ltd.) will be described with reference to a cross-sectional view. explain.

【0009】まず、10Ωcm程度のn型シリコン基板
を酸化し、表面にシリコン酸化膜(SiO2 )を形成
した後フォトリソグラフィ技術によりSiO2 膜をパ
ターニングする(図1(A))。次いで塗布拡散源であ
るPBFをスピンナーを用いてウェハー上に塗布する(
図1(B))。この時アルコール系有機溶媒は飛散して
しまう。次いで、200℃以上拡散温度以下(例えば6
00℃)の数%〜100%酸素雰囲気中で30分程度炉
ベークすることにより、有機物はすべて二酸化炭素(C
O2 )と水分(H2 O)に分解し、あとには、酸化
ホウ素(B2 O3 )膜が生じる(図1(C))。次
いで、同一炉内で窒素雰囲気にパージした後、温度コン
トローラにより所定の拡散温度まで昇温し、数分〜数十
分の拡散を行う(図1(D))。この時、図2に示すよ
うに窒素のトータル流量を400l/H以上にする必要
がある。 最後に、600℃前後に降温した後、炉より引き出し、
純水及び弗酸の混合液により、ボロンガラス層を除去す
る(図1(E))。
First, an n-type silicon substrate of about 10 Ωcm is oxidized to form a silicon oxide film (SiO2) on the surface, and then the SiO2 film is patterned by photolithography (FIG. 1(A)). Next, PBF, which is a coating diffusion source, is coated onto the wafer using a spinner (
Figure 1(B)). At this time, the alcohol-based organic solvent is scattered. Next, the temperature is 200°C or higher and lower than the diffusion temperature (for example, 6°C).
All organic matter is converted to carbon dioxide (C
It decomposes into water (H2O) and water (H2O), and a boron oxide (B2O3) film is formed afterwards (FIG. 1(C)). Next, after purging the same furnace to a nitrogen atmosphere, the temperature is raised to a predetermined diffusion temperature using a temperature controller, and diffusion is performed for several minutes to several tens of minutes (FIG. 1(D)). At this time, as shown in FIG. 2, the total flow rate of nitrogen needs to be 400 l/H or more. Finally, after the temperature has dropped to around 600℃, it is removed from the furnace.
The boron glass layer is removed using a mixed solution of pure water and hydrofluoric acid (FIG. 1(E)).

【0010】以上の工程を通常のパイポーラ・トランジ
スタの製造工程中に付加することにより、図3に示すよ
うな極浅いベース層を形成することができる。
By adding the above steps to the normal bipolar transistor manufacturing process, an extremely shallow base layer as shown in FIG. 3 can be formed.

【0011】他の実施例として、前実施例の図1(C)
の焼成後、炉より引き出し、直ちに常圧化学気相成長法
(以下常圧CVD)により、B2 O3 膜上にSiO
2 膜を堆積させる。次いで、ウェハーを洗浄後ランプ
アニール装置により数秒〜数十秒の短時間拡散を行う。 これにより、前実施例よりさらに極浅い拡散層を形成す
ることができる。
As another embodiment, FIG. 1(C) of the previous embodiment
After firing, SiO is removed from the furnace and immediately deposited on the B2 O3 film by atmospheric pressure chemical vapor deposition (hereinafter referred to as atmospheric CVD).
2 Deposit the film. Next, after cleaning the wafer, diffusion is performed for a short period of several seconds to several tens of seconds using a lamp annealing device. As a result, a much shallower diffusion layer can be formed than in the previous example.

【0012】0012

【発明の効果】以上、説明したように本発明は、フォト
レジストとほぼ同一成分を用いるため、ウェハーの大口
径化にイオン注入同様対応でき、スループットも大であ
る。しかも、焼成後は100%B2 O3 膜のため、
不純物拡散源中の濃度分布や偏析計数などを考慮する必
要がなく、それだけプロセスパラメータを単純化できる
。また、塗布膜厚の不均一性によるドープの均一性への
影響も小さく、イオン注入法のようなダメージも発生し
ない。
As explained above, since the present invention uses substantially the same components as photoresist, it can cope with increasing the diameter of wafers in the same way as ion implantation, and has a high throughput. Moreover, since it is a 100% B2 O3 film after firing,
There is no need to consider the concentration distribution in the impurity diffusion source, the segregation coefficient, etc., and the process parameters can be simplified accordingly. In addition, the influence of non-uniformity of the coating film thickness on doping uniformity is small, and damage unlike ion implantation does not occur.

【0013】加えて、塗布拡散源からの低温加熱拡散の
ため、拡散開始時点では分布深さはなく、それだけ浅い
接合形成の可能性が高い。
In addition, because of the low-temperature heating diffusion from the coating diffusion source, there is no depth of distribution at the time of starting the diffusion, and the possibility of forming a shallow junction is higher.

【0014】以上のような利点をバイポーラ・トランジ
スタのエミッタ及びベース形成に用いることによりトラ
ンジスタ性能及び歩留りの飛躍的向上が望める。
By utilizing the above-mentioned advantages in forming the emitter and base of a bipolar transistor, a dramatic improvement in transistor performance and yield can be expected.

【図面の簡単な説明】[Brief explanation of the drawing]

【図1】本発明の一実施例を示す工程断面図である。FIG. 1 is a process sectional view showing an embodiment of the present invention.

【図2】本発明実施時の窒素トータル流量依存性である
FIG. 2 shows dependence on nitrogen total flow rate when the present invention is implemented.

【図3】本発明実施時のSIMS分析による不純物濃度
分布である。
FIG. 3 is an impurity concentration distribution obtained by SIMS analysis during implementation of the present invention.

【符号の説明】[Explanation of symbols]

1    n型シリコン基板(10Ωcm以上)2  
  熱シリコン酸化膜(SiO2 )3    アルコ
ール系有機溶媒 4    塗布後のポリ・ボロン・フィルム5    
焼成時の二酸化炭素 6    焼成時の水分 7    拡散後のボロンガラス層(B2 O3 )8
    P型極浅い拡散層
1 N-type silicon substrate (10Ωcm or more) 2
Thermal silicon oxide film (SiO2) 3 Alcohol-based organic solvent 4 Poly boron film after coating 5
Carbon dioxide during firing 6 Moisture during firing 7 Boron glass layer after diffusion (B2 O3) 8
P-type ultra-shallow diffusion layer

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】  シリコン基板上に塗布拡散源を塗布す
る工程と、その後、200℃以上かつ拡散温度以下で数
%〜100%酸素雰囲気中で焼成して不純物層(例えば
B2 O3 )を形成する工程と、900℃以下の低温
で数秒〜数十分拡散する工程とを含むことを特徴とする
半導体装置の製造方法。
[Claim 1] A step of applying a coating diffusion source onto a silicon substrate, and then baking in an oxygen atmosphere of several percent to 100% at a temperature of 200° C. or higher and lower than the diffusion temperature to form an impurity layer (for example, B2 O3). 1. A method for manufacturing a semiconductor device, comprising: a step of diffusing at a low temperature of 900° C. or less for several seconds to several tens of minutes.
【請求項2】  前記塗布拡散源として、それぞれn型
,P型不純物であるB,P,Asの酸化物(例えばB2
 O3 ,P2 O5 ,As2 O5 等)を有機性
高分子と反応させてポリマー化し、アルコール系溶媒に
溶解させたものを用いることを特徴とする請求項1記載
の半導体装置の製造方法。
2. As the coating diffusion source, oxides of B, P, and As (for example, B2
2. The method of manufacturing a semiconductor device according to claim 1, characterized in that the method uses a polymer obtained by reacting O3, P2 O5, As2 O5, etc. with an organic polymer and dissolving it in an alcoholic solvent.
【請求項3】  前記拡散時の雰囲気として100%窒
素ガスとし、そのトータル流量を400l/H以上とす
ることを特徴とする請求項1又は2記載の半導体装置の
製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the atmosphere during said diffusion is 100% nitrogen gas, and the total flow rate thereof is 400 l/H or more.
JP5530891A 1991-03-20 1991-03-20 Manufacture of semiconductor device Pending JPH04291729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5530891A JPH04291729A (en) 1991-03-20 1991-03-20 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5530891A JPH04291729A (en) 1991-03-20 1991-03-20 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04291729A true JPH04291729A (en) 1992-10-15

Family

ID=12994942

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5530891A Pending JPH04291729A (en) 1991-03-20 1991-03-20 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04291729A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002075892A (en) * 2000-08-28 2002-03-15 Sanken Electric Co Ltd Liquid impurity raw material, and semiconductor device
JP2006156646A (en) * 2004-11-29 2006-06-15 Sharp Corp Solar cell manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002075892A (en) * 2000-08-28 2002-03-15 Sanken Electric Co Ltd Liquid impurity raw material, and semiconductor device
JP2006156646A (en) * 2004-11-29 2006-06-15 Sharp Corp Solar cell manufacturing method

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