JPS6386565A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce cost by a method wherein a bipolar transistor and other elements are built in an integrated circuit without an epitaxial layer growing process. CONSTITUTION:An ion implantation mask 2 is selectively formed on the surface of a P-type silicon substrate 1, and ions are implanted in an opening in the mask 2 at a high acceleration energy of 2-10MeV. Annealing is accomplished for the removal of a damaged layer 4 produced in the ion implantation process. Then, an N-type buried layer 5 is formed. A thin oxide film 6 is attached to the surface of the P-type silicon substrate 1, and photolithography is applied for the patterning of a photoresist 7. A process follows wherein P ions of approximately 1X10<13>-1X10<14>atom/cm<2> are implanted at an acceleration energy of 10-100Kev through the thin oxide film 6 with the photoresist 7 serving as a mask. Annealing is performed, the damaged layer 4 is removed, and an N-type well 9 is formed to be in contact with the N-type buried layer 5. Next, in the N-type well 9, an N-type collector 10, P-type base 11, and an N-type emitter 12 are built for the completion of a transistor of this design.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical field to which the invention pertains) The present invention relates to a semiconductor device, and particularly to a method for manufacturing a semiconductor device having a buried layer.

[Prior art and its problems]

When configuring bipolar transistors within an integrated circuit,
According to one conventional method, as shown in FIG. 3, N-type impurities such as antimony or arsenic with a small diffusion coefficient are selectively diffused into a P-type silicon substrate 1 to form an N-type buried N5. Next, an N-type epitaxial layer 14 is formed thereon, a P-type isolation diffusion 1ii15 is further formed, and an N-type collector 1 is formed in the N-type epitaxial layer 14 between the isolation diffusion layers.
0, a P-type base 11, an N-type emitter 12, and an aluminum electrode 13 constitute a bipolar transistor. This epitaxial layer formation is carried out by the CVD method, but it is expensive because only a small number can be processed in the same batch, there is a risk of explosion because a large amount of hydrogen gas is used, and the low temperature (1100 ~
Since a single crystal is formed at a temperature of 1,200° C.), crystal defects such as slips and protrusions occur, which reduces the yield rate.

On the other hand, in CMO3 integrated circuits, there is a tendency to use epitaxial wafers from the viewpoint of latch-up countermeasures.
Although progress has been made in epitaxial growth technology, the drawback of high cost has not yet been resolved.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for configuring elements such as bipolar transistors in integrated circuits without epitaxial layer growth, thereby significantly reducing costs.

[Key points of the invention]

The present invention is based on the fact that a bipolar transistor in a conventional integrated circuit has an N-type buried layer and an N-type epitaxial layer directly above the N-type buried layer, and that the acceleration energy in ion implantation can reach the MeV region. It focused on
Impurities are selectively introduced deep into the semiconductor substrate by ion implantation with high acceleration energy to form a buried layer, then impurities of the same conductivity type are selectively introduced from the surface using the same photomask, and heat treatment is performed. A well is formed by contacting the buried layer.

[Embodiments of the invention]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the manufacturing process of the method of the present invention. First, in FIG. 1a, an ion implantation mask 2 is selectively formed on the surface of a P-type silicon substrate 1. As shown in FIG. As the ion implantation mask 2, there are a method of applying a photoresist to a thickness of about 2 to 6 μm, a method of vapor depositing a metal to a thickness of about 1 to 3 μm, and the like.

Next, in FIG. 1, ion implantation is performed through the opening of the ion implantation mask 2 at a high acceleration energy of about 2 to 10 MeV. 3 represents implanted ions, and 4 represents a damaged layer caused by ion implantation on the surface side.

Ions incident on a silicon substrate using the ion implantation method are
It collides with silicon atoms one after another, losing energy as it moves forward, and finally comes to rest. As the acceleration energy increases,
Ions lose energy through collisions with electrons and move forward.

Furthermore, the greater the mass of the implanted ions, the greater the energy loss due to collision with the atomic nucleus, making it difficult for them to penetrate deeply. These phenomena are explained by LSS (Linhard, 5ch
arff+5chiftt) can be accurately determined by theory, but the explanation will be omitted here. In the case of acceleration energy of 2 to 10 MeV, the depth of P ions is about 2 to 10 μm, and the depth of As ions is about 1 to 5 μm. The dose is lXl0'4~IXIO15at
Let m/cd.

In FIG. 1C, annealing is performed to remove the damaged layer 4 caused by ion implantation, and an N-type buried N5 is formed. Annealing is performed at a temperature of 600 to 1200°C for 0.1 to several hours.

In FIG. 1d, a thin oxide film 6 is applied to the surface of the silicon substrate 1, and photolithography is performed using a mask with the same pattern as the photomask used in the step of FIG. 1a to pattern a photoresist 7. 10 to 100 keV through oxidized PJ6 using 7 as a mask
With an acceleration energy of about
Inject about Xl0" atm/-. 8 is 0.0 from the surface
It shows implanted ions implanted to a depth of about 1 to 0.1 μm. Note that this step may be performed by impurity diffusion instead of ion implantation.

In FIG. 1e, an annealing process is performed to remove the damaged layer, and an N-type well 9 is formed and brought into contact with the buried layer 5.

Annealing is performed at about 1000 to 1200° C. for 0.1 to several hours.

Next, as shown in FIG. 2, an N-type collector 10, a P-type base 11, and an N-type emitter 12 are formed in the N-type well 9, as in the conventional method, to complete the transistor. Figures 2 and 3
As can be seen from the comparison with the figure, according to the present invention, an N-type well 9 is used in place of the conventional N-type epitaxial N14 and P-type isolation diffusion 1'1i15, resulting in a significant cost reduction. achieved.

FIG. 4 shows the impurity concentration profile of the transistor formed according to the present invention, and the vertical axis is the impurity concentration Co (cm
-3), the horizontal axis shows the depth Xj (, um), 15 is the concentration curve of N-type emitter, 16 is the concentration curve of P-type base, 17 is the concentration curve of N-type buried layer, 18 is N-type emitter concentration curve This is a concentration curve of a type well, and 19 is a concentration curve of a conventional epitaxial layer for comparison. Although there is a difference between the profile of the conventional epitaxial layer and the profile of the N-type well of the present invention, it is possible to make the basic transistor characteristics the same, and there is no problem.

Note that the present invention is applicable not only to bipolar transistors but also to elements having a buried layer and an epitaxial layer, such as diodes. It goes without saying that it can also be applied to integrated circuits such as Bi-CMO3 ICs that include MO3 elements in addition to bipolar transistors.

〔Effect of the invention〕

According to the present invention, an N-type buried layer, which is a component of a bipolar transistor, is implanted deep into a semiconductor substrate with high acceleration energy, and using a mask with the same pattern used at the time, N-type buried By implanting type impurities to form an N-type well, the conventionally used N-type epitaxial layer growth and P-type separation diffusion are unnecessary, and costs can be significantly reduced.

[Brief explanation of the drawing]

Figure 1 is a sectional view showing the manufacturing process of an embodiment of the present invention, Figure 2 is a sectional view showing the manufacturing process of an embodiment of the present invention.
3 is a sectional view of a transistor obtained by the manufacturing process shown in FIG. 1, FIG. 3 is a sectional view of a conventional transistor, and FIG. 4 is an impurity concentration profile of a transistor according to the present invention and a conventional method. 1... Silicon substrate, 2... Ion implantation mask, 3
... Injected ions, 5... N-type buried layer, 7... Photoresist, 8... Injected ions, 9... N-type well.

Claims (1)

[Claims] 1) In a method for manufacturing a semiconductor device having a buried layer, a buried layer is formed by selectively introducing impurities of a conductivity type opposite to that of the semiconductor substrate by ion implantation onto a semiconductor substrate of one conductivity type, and then the buried layer is A well is formed by introducing an impurity of the same conductivity type as the buried layer at a lower concentration than the buried layer from directly above the buried layer, and the well and the buried layer are brought into contact by heat treatment. A method for manufacturing a semiconductor device.