JPS58218159A - Complementary type metal oxide semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a latch-up phenomenon, and to improve performance and increase density by forming a high resistance layer to one part of a boundary between a semiconductor base body and a well region formed in insular manner. CONSTITUTION:A p<-> type silicon layer 22 and an n<-> type layer 23 are grown on an n type silicon substrate 21 in an epitaxial manner in succession. A resist pattern 26 is formed, and a phosphorus ion implanted layer 27 is formed selectively extending over the n<-> type silicon layer 23 and the p<-> type silicon layer 22. The insular p-well region 29 and a p<-> type impurity layer (the high resistance layer) 30 are formed through heat treatment. With a CMOS manufactured through several processes, density can be increased because the latch-up phenomenon can be prevented by the high resistance layer 30 formed in the depth direction of the semiconductor base body without forming a guard ring region.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to improvements in complementary MOS semiconductor devices.

[Technical background of the invention and its problems]

A complementary MOS semiconductor device (hereinafter abbreviated as CMOS) uses, for example, an n-type semiconductor substrate on which an island-shaped p-well region is formed, an n-channel MOS transistor on the surface of the p-well region, and an n-channel MOS transistor on the surface region of the semiconductor substrate other than the p-well. , p-channel MOS transistors are provided, respectively. A circuit incorporating such a CMOS is superior in terms of power consumption compared to a single channel MOS transistor circuit. For this reason, it is suitable to form circuits using CMOS in VLSIs where heat generation in circuits due to higher integration is considered a problem.

By the way, a conventional CMOS has a structure shown in FIG. That is, 1 in the figure is an n-type semiconductor substrate, and a p-well region 2 is selectively provided in this substrate 1.

P+ type source and drain regions 3 and 4 electrically isolated from each other are provided on the surface of the substrate 1 other than the well region 2,
A gate electrode 6 is provided on the substrate 1 between these regions 3 and 4 with a gate oxide film 5 interposed therebetween. These p+ type source and drain regions 3, 4, gate electrode 6, etc.
A channel MOS transistor is configured. Note that 7 in the figure is provided on the substrate 1, and the p-channel MO
This is an n+ type region that provides VDD as the substrate bias potential of the S transistor. Furthermore, n+ type source and drain regions 8 and 9 which are electrically isolated from each other are provided on the surface of the p-well region 2, and on the well region 2 between these source and drain regions 8 and 9, A gate electrode 11 is provided with a gate oxide film 10 interposed therebetween. The n+ type source, drain regions 8, 9, gate electrode 11, etc. constitute an n-channel MOS transistor. Note that 12 in the figure is provided in the p-well region 2, and
V as the substrate bias of the channel MOS transistor
This is a p+ type region that provides an SS potential. This kind of CMO
The circuit formed by S is the simplest inverter circuit, and the gate electrodes 6 and 11 of each transistor are connected with aluminum wiring etc. and become the input Vin side, p+ type, n+ type.
The drain regions 4 and 9 of the mold are also connected by aluminum wiring or the like, and become an output Vout. Also, p-channel MOS
The p+ type source region 3 and potential application n+ type region 7 of the transistor are electrically connected to the power supply VD by aluminum wiring or the like.
Connected to D. On the other hand, the n+ type source region 8 of the n-channel MOS transistor and the p+ type region 1 for potential application.
2 is electrically reference power supply VS using aluminum wiring, etc.
Connected to S.

However, in the CMOS structure described above, the n+ type source region 8 and the p-
A parasitic npn transistor Qn has well region 2 and n-type semiconductor substrate 1 as emitter, base, and collector, respectively, and p+-type source region 3 of p-channel MOS transistor, n-type semiconductor substrate 1, and p- well region 2 as emitter, Parasitic pnp transistor Q as base and collector
p is formed. In addition, each parasitic transistor Q in FIG.
Although only one n and Qp are shown, they are actually widely distributed. Such a parasitic npn transistor Q
When a parasitic pnp transistor Qp is formed, a latch-up phenomenon occurs during operation. This will be explained below with reference to FIG. 1 and FIG. 2 showing an equivalent circuit.

First, if a negative voltage is applied to the output Vout due to a disturbance, a parasitic npn transistor Qn whose emitter, base, and collector are the n+ type drain region 9, p− well region 2, and n type semiconductor substrate 1 of the n channel MOS transistor, respectively. ’ emitter potential becomes negative. When the potential difference between this negative voltage and the potential VSS of the p-well region 2 becomes higher than the base-emitter potential of the parasitic npn transistor Qn', the n+ type drain region 9 of the n-channel MOS transistor and the p-well region 2 A bipolar action occurs between the transistor Qn and the n-type semiconductor substrate 1, and the collector current Ic' of the parasitic npn transistor Qn' flows. Since this collector current Ic' flows through the resistor Rbn of the n-type semiconductor substrate 1 on the VDD side, the base potential of the above-mentioned parasitic pnp transistor Qn is lowered, causing the transistor Qp to take a bipolar action. Collector current I of the same transistor Qp
CP will start flowing. And this collector current I
cp flows into VSS connected to the p+ type region 12 for well substrate power supply in the p- well region 2. At this time, the electrical resistance Rbp of the p-well region 2 raises the base of the parasitic npn transistor Qn, which causes the transistor Qn to take a bipolar action. Due to the bipolar action of the transistor Qn, its collector current ■cn and the base voltage of the parasitic pnp transistor Qp are lowered, and the transistor Q
A large current flows from VDD to VSS due to positive feedback in which the collector current Icp of p is made easier to flow, thereby further increasing the base voltage of the parasitic npn transistor Qn, and further increasing the collector current Icn of the transistor. Such latch-up current causes C
Not only does the MOS become inoperable, but an integrated circuit including such a CMOS is thermally destroyed by the large current.

In order to prevent the above-mentioned latch-up phenomenon, as shown in FIG. 3, p+ type guard ring regions 13 and n+ type guard ring regions are connected to the opposing regions of the p- well region 2 and the n-type semiconductor substrate 1 to the potentials of VSS and VDD, respectively. A CMOS circuit with a mold guard ring region 14 has been developed. With this configuration, the parasitic npn transistor Qn and the parasitic pnp transistor Qp, which cause latch-up, are equivalently connected to the guard ring regions 13 and 14 at their respective paces. In this equivalent connection, if the collector current Icp of the parasitic pnp transistor Qp flows, for example, the current flows through the p+ type guard ring region 1 of the p- well region 2.
3, the parasitic npn transistor Qn does not have a bipolar action and its collector current Icn does not flow. Therefore, the transistor Qp also does not have a bipolar action and 2cp does not flow either. In other words, parasitic pnp
Originally, the collector current Icp of the transistor Qp does not flow. Therefore, the guard ring area 13,
By providing 14, it is possible to make the latch-up phenomenon less likely to occur. However, since a guard ring region is provided in addition to the MOS transistor of each channel, the area required for the CMOS circuit configuration increases, which hinders high integration.

[Purpose of the invention]

The present invention aims to provide a complementary MOS semiconductor device that achieves high performance and high density by preventing latch-up phenomena without increasing the area between MOS transistors of each channel.

[Summary of the invention]

The present invention provides a latch-up method by providing a semiconductor layer (high resistance layer) having a lower electrical conductivity than that of the substrate and the well region at least in part of the boundary between the semiconductor substrate and the well region formed in an island shape on the nuclear substrate. The main idea is to make it difficult for the current flowing from the semiconductor substrate to the well region, which serves as a trigger current, to prevent the latch-up phenomenon without causing an increase in area due to the provision of a guard ring region as in the conventional method.

[Embodiments of the invention]

Next, examples of the present invention will be described along with manufacturing methods.

Example 1 (1) First, for example, 1013
A p-type silicon layer 22 and an n-type silicon layer 23 having an impurity concentration of /cm3 were epitaxially grown in sequence (as shown in FIG. 4(a)). Subsequently, a resist pattern 24 is formed by photolithography in an area on the n-type silicon layer 23 excluding a portion slightly smaller than the planned p-well region, and then using the resist pattern 24 as a mask, a p-type impurity, such as boron, is added. A boron ion implantation layer 26 was selectively formed in the n-type silicon layer 23 by ion implantation at an acceleration voltage of 100 keV and a dose of 5.times.10@12 /cm@2 (as shown in FIG. 4(b)). Subsequently, the resist pattern 24 is removed, and a resist pattern 26 is formed by photolithography in a region including the boron ion implanted layer 25 on the n-type silicon layer 23. Using the resist pattern 26 as a mask, an n-type impurity, For example, phosphorus was ion-implanted under the conditions of an acceleration voltage of 320 keV and a dose of 1 x 1012/cm^2, and a phosphorus ion implantation layer 27 was selectively formed over the n-type silicon layer 23 and the p-type silicon layer 22 (the fourth Figure (c) shown).

(ii) Next, after removing the resist pattern 26,
Heat treatment was performed. At this time, the boron ion implantation layer 25
The phosphorus ion implantation layer 27 is diffused to form an n-type silicon layer 28 on the n-type silicon substrate 21, and an island-shaped p-well region 29 and the p-well region 29 are formed in the silicon layer 28.
A p-type impurity layer (high resistance layer) 30 was formed between the well region 29 and the substrate 21 (as shown in FIG. 4(d)).

(iii) Next, after forming a field oxide film 31 for isolating the silicon layer 28 and the well region 29 and a channel stopper region (not shown) under the field oxide film by selective oxidation, the field oxide film 31 is used to separate the silicon layer 28 and the well region 29. A gate oxide film 32 was formed on the n-type silicon layer 28 and the island region of the p-well region 29. Subsequently, a polycrystalline silicon layer is deposited on the entire surface and patterned to form gate electrodes 331, 332, and 34 on the gate oxide film 32, and then boron is deposited on the n-type silicon layer 28 and the p-well region 29. Selectively implant and activate ions to form p+ type drain and source regions 361, 361 in the n-type silicon layer 28.
, 352 and 362, a p+ type region 37 for a p-well substrate power supply was formed in the p-well region 29.

Through these steps, two p-channel MOS transistors were formed in the n-type silicon layer 28.

Subsequently, p-well region 29 and n-type silicon layer 2
Arsenic is selectively ion-implanted into 8 and activated to form n+ type source and drain regions 38 and 39 in the p- well region 29.
, the n+ for substrate power supply (VDD) is applied to the n-type silicon layer 28.
A mold region 40 was formed. Through these steps, p-
An n-channel MOS transistor was formed in well region 29. Furthermore, after depositing a CVD-SiO2 film 41 on the entire surface and opening contact holes 42, an Al film is deposited on the entire surface and patterned to form the p+ type drain region 351 and the n+ type drain region 39. an Al wiring 43 connecting the p+ type source region 361 and the p+ type drain region 352 via the two contact holes 42, 42, an Al wiring 44 connecting the p+ type source region 361 and the p+ type drain region 352 via the two contact holes 42, Type source area 362
and the n+ type region 40 through two contact holes 42 and 4.
2, and the n+ type source region 38 and p+ type region 37 are connected through two contact holes 4.
Al wirings 46 connected via wires 2 and 42 were formed, respectively. Finally, a protective film 47 made of phosphorus silicide glass or the like was deposited on the entire surface to manufacture a CMOS (as shown in FIG. 4(e)).

As shown in FIG. 4(e), the CMOS of the present invention has an interface between the p-well region 29 and the semiconductor substrate composed of the n-type silicon substrate 21 and the n-type silicon layer 28.
- Since the structure is such that the high resistance layer 30 is provided at the bottom of the well region 29, latch-up phenomenon can be prevented. That is,
When the n-type drain region of the p-well region becomes a negative potential due to a disturbance, a trigger current Ic' flows from the semiconductor substrate in the CMOS structure shown in FIG.
The P well region shown in the equivalent circuit in the figure is the collector, and n
This becomes a base current of a parasitic pnp transistor having the type substrate as the base and the p+ type source region as the emitter, and a latch-up operation begins. On the other hand, the CMOS of the present invention has p
- Since the high resistance layer 30 is provided at the bottom of the well region 29, the trigger current c' flowing from the semiconductor substrate to the p-well region 29 is reduced in magnitude by the high resistance layer 30, resulting in a parasitic pnp transistor. The current flowing to the terminal also becomes smaller, making latch-up less likely to occur. Fact, 5
When operated with a power supply voltage of V, the high resistance layer 30
The magnitude of the trigger current required to cause latch-up from the outside with respect to the impurity concentration of the high-resistance layer 30 was determined using the film thickness (t) as a parameter, and the characteristic diagram shown in FIG. 5 was obtained. However, the trigger current in the figure is normalized to an appropriate value. From FIG. 5, it can be seen that the lower the impurity concentration of the high-resistance layer 30 and the thicker the film thickness, the larger the trigger current required for latch-up, and the more difficult it is for latch-up to occur. I understand.

Furthermore, the CMOS of the present invention is similar to the conventional CMOS shown in FIG.
As shown in FIG. 2, high density can be achieved by preventing latch-up phenomena by using the high resistance layer 30 provided in the depth direction of the semiconductor substrate without providing a guard ring region between the p-channel and n-channel MOS transistors.

Example 2 (i) First, for example, 1013 is placed on the n-type silicon substrate 21.
p-type silicon layer 22' having an impurity concentration of /cm3
was epitaxially grown (as shown in FIG. 6(n)). Subsequently, a resist pattern 24 is formed by photolithography on the p-type silicon layer 22' except for a portion slightly smaller than the planned p-well region, and then, using the resist pattern 24 as a mask, boron is deposited. Acceleration voltage 50keV,
A boron ion implantation layer 25 was selectively formed in the p-type silicon layer 22' by ion implantation at a dose of 4.times.10@12 /cm@2 (as shown in FIG. 6(b)). Continuing, the resist pattern 24 is removed and the p-type silicon layer 2 is removed again.
After forming a resist pattern 26 by photolithography in a region including the boron ion-implanted layer 25 on 2', phosphorus is accelerated at a voltage of 200 k using the resist pattern 26 as a mask.
Ions are implanted under the conditions of eV and a dose of 1×10 12 /cm 2 to form a phosphorus ion implanted layer 27 in the p-type silicon layer 22 ′.
was selectively formed (as shown in FIG. 6(c)).

(ii) Next, after removing the resist pattern 26,
Heat treatment was performed. At this time, the boron ion implantation layer 25
and phosphorous ion implantation layer 27 are respectively diffused to form an n-type silicon layer 28' on the n-type silicon substrate 21, and an island-shaped p-well region 29' is formed in the silicon layer 28'.
A p-type impurity layer (high resistance layer) 30' was formed between the p-well region 29' and the substrate 21 (FIG. 6(d)).
). Thereafter, a CMOS was manufactured in the same manner as in step (iii) of Example 1 (as shown in FIG. 6(e)).

Therefore, the CMOS shown in FIG. 6(e) has a high rise at the bottom of the well region 29', which is the interface between the p-well region 29' and the semiconductor substrate consisting of the n-type silicon substrate 21 and the n-type silicon layer 28'. Since the structure includes the resistive layer 30', the latch-up phenomenon can be prevented as in the CMOS shown in FIG. 4(e).

Embodiment 3 (i) First, a resist pattern 48 is formed by photolithography on an area of the n-type silicon substrate 21 excluding a portion slightly smaller than the planned p-well region, and then phosphorus is applied using the resist pattern 48 as a mask. A phosphorus ion implantation layer 49 was formed inside the n-type silicon substrate 21 by ion implantation under the conditions of an acceleration voltage of 1 MeV and a dose of 3×10 11 /cm 2 (as shown in FIG. 7(a)). Next, using the same resist pattern 48 as a mask, boron was accelerated at a voltage of 160 keV.
A boron ion implantation layer 50 was formed on the surface of the substrate 21 by ion implantation at a dose of 5×10 12 /cm 2 (as shown in FIG. 7(b)).

(ii) Next, after removing the resist pattern 48,
Heat treatment was performed. At this time, each of the ion implantation layers 49, 5
0 is diffused to form an island-shaped p-well region 29'' in the n-type silicon substrate 21, and a phosphorus ion-implanted layer 49 is formed in the n-type silicon substrate 21.
and the boron ion-implanted layer 50, a high resistance layer 30'' in which phosphorus and boron are mixed in almost equal amounts and has a high electrical resistance.
was formed at the bottom of the well region 29'' (as shown in FIG. 7(c)). Thereafter, a CMOS was manufactured by the same method as in step (iii) of Example 1 (as shown in FIG. 7(d)).

Therefore, the CMOS shown in FIG. 7(d) has a structure in which a high resistance layer 30'' is provided at the bottom of the well region 29'', which is the interface between the p-well region 2g'' and the n-type silicon substrate 21 (semiconductor base). Therefore, the CMO shown in Figure 4(e)
Like S, latch-up phenomenon can be prevented.

Note that the CMOS according to the present invention is not limited to the structure shown in each of the embodiments described above, and for example, as shown in FIG.
A shallow p-well region 29'' is provided in the well region 29'', and the n+ type source and drain regions 38, 39 and p+ type region 37 of the n-channel MOS transistor are provided in the well region 29''.
It is also possible to have a structure in which it is in contact with the high resistance layer 30'' at the bottom. With such a structure, the collector current of the parasitic transistor decreases as the well region within the well region 29'' becomes shallower. The latch-up phenomenon can be more effectively prevented.

Further, the CMOS according to the present invention is not limited to the structure shown in each of the above embodiments, but, for example, an island-shaped p
A structure may be adopted in which a -well region is provided and a low concentration impurity layer (high resistance layer) is provided by counter-doping arsenic into the bottom surface of the p-well region. CM with such structure
In the OS, the impurity concentration of the p-well region is set to 1016
/cm3, and the trigger current required to cause latch-up due to a change in arsenic concentration in the low concentration impurity layer (change in the difference from the impurity concentration in the p-well region) when operated at a power supply voltage of 5V is calculated as follows. The characteristic diagram is shown in FIG.

From this Figure 9, if arsenic is counter-doped to the same level as the impurity concentration of the p-well region (1016/cm3),
The p-type impurity (boron) and arsenic are neutralized, an insteric low concentration impurity layer (high resistance layer) is formed, and the trigger current increases. In other words, the smaller the difference between the impurity concentration in the p-well region and the counter-doped arsenic concentration, the greater the trigger current value required to cause latch-up, and the less latch-up occurs.

〔Effect of the invention〕

As detailed above, according to the present invention, each channel's MO
Complementary M that achieves higher performance and higher density by preventing latch-up without increasing the area between S transistors.
An OS semiconductor device can be provided.

[Brief explanation of drawings]

Fig. 1 is a schematic sectional view showing a conventional CMOS, Fig. 2 is an equivalent circuit diagram of a parasitic transistor occurring in the CMOS shown in Fig. 1, Fig. 3 is a schematic sectional view showing a conventional improved CMOS, and Fig. 4 (a) to (e) are CMOS of Example 1 of the present invention
FIG. 5 is a cross-sectional view showing the manufacturing process for obtaining Example 1.
Characteristic diagrams showing the increase and decrease of the trigger current necessary to cause latch-up with respect to changes in the impurity concentration of the high-resistance layer with respect to the film thickness parameters of the high-resistance layer in the CMOS, and Figures 6 (a) to (e) are from this book. 7(a) to 7(d) are cross-sectional views showing the manufacturing process for obtaining a CMOS according to Example 2 of the present invention; FIGS. The figure shows a further embodiment of the present invention.
FIG. 9 is a cross-sectional view of S, and is a characteristic diagram showing the relationship between the change in arsenic concentration that is counter-doped to form a low-concentration impurity layer at the bottom of the p-well region and the trigger current required to cause latch-up. . 21...n-type silicon substrate, 22, 22'...p-
type silicon layer, 23...n-type silicon layer, 28, 2
8'-n-type silicon layer, 29, 29', 29''29'''
...p-well region, 30, 30', 30'', 30''
'...Low concentration impurity layer (high resistance layer), 32...Gate
oxide film, 331, 332, 34...gate electrode, 3
51, 352...p+ type drain region, 361, 36
2...p+ type source region, 37...p+ type region, 3
8...n+ type source region, 39...n+ type drain region, 40...n+ type region, 41...CVD-Si
O2 film, 43-46... Al wiring, 47... Purulent retention film.

Claims (2)

[Claims] (1) A semiconductor substrate of a second conductivity type having an island-shaped well region of a first conductivity type on its surface, a MOS transistor of a second conductivity type channel provided on the surface of the well region, and a semiconductor other than the well region. In a complementary MOS semiconductor device including a MOS transistor of a first conductivity type channel provided on a surface of a substrate, at least a portion of the boundary between the well region and the semiconductor substrate has a conductivity lower than that of the well region and the semiconductor substrate. A complementary MOS semiconductor device characterized by providing a small semiconductor layer. (2) The complementary MOS semiconductor device according to claim 1, wherein the impurity concentration of the semiconductor layer is 1014/cm3 or less.