JPH0574729A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH0574729A
JPH0574729A JP23265891A JP23265891A JPH0574729A JP H0574729 A JPH0574729 A JP H0574729A JP 23265891 A JP23265891 A JP 23265891A JP 23265891 A JP23265891 A JP 23265891A JP H0574729 A JPH0574729 A JP H0574729A
Authority
JP
Japan
Prior art keywords
substrate
film
semiconductor region
poly
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP23265891A
Other languages
Japanese (ja)
Inventor
Yoshiko Okui
芳子 奥井
Makoto Nakamura
誠 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP23265891A priority Critical patent/JPH0574729A/en
Publication of JPH0574729A publication Critical patent/JPH0574729A/en
Withdrawn legal-status Critical Current

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  • Element Separation (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To avoid the billard phenomena of O ions thereby enabling a high quality diffused layer to be formed by using poly Si or amorphous Si as the covering film of a silicon substrate. CONSTITUTION:A multitude of element formation regions 3 encircled by separation insulating films 2 comprising SiO2 are formed on a phosphorus-doped N type Si substrate 1. A covering film 4 comprising phosphorus-doped poly-Si is formed on this substrate 1 using CVD process. Next, this substrate is ion- implanted with boron fluoride to form P type well in the element formation region 3 and then the substrate 1 is annealed for activation in N2 current to form a semiconductor region 5. Next, the whole body is immersed in a water solution using KOH, isopropanol and ethylenediaminepyrocatechol as a solute to remove the N type covering film 4. Through these procedures, such a problem of quality deterioration in a diffused layer due to the billiard phenomena of O ions during the ion implantation step can be solved thereby enabling a high quality semiconductor region to be formed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はイオン注入法による半導
体領域(拡散層)の形成方法に関する。半導体デバイス
は半導体基板に電子価制御が可能なイオンの拡散を行っ
て伝導型の異なる半導体領域を作り、この半導体領域を
用いてデバイス形成を行うものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a semiconductor region (diffusion layer) by an ion implantation method. A semiconductor device is one in which a semiconductor region having different conductivity types is formed by diffusing ions capable of controlling electron valence on a semiconductor substrate, and the device is formed using this semiconductor region.

【0002】こゝで、半導体領域の形成方法として当初
は不純物元素を含むガス或いは不純物元素を半導体基板
に接触させて固相−気相拡散或いは固相−固相拡散を行
わせる熱拡散法が使用さていたが、現在では不純物元素
をイオン化し、これに高いエネルギーを与えて半導体基
板に注入するイオン注入法(Ion Implantation) が不純
物元素の濃度の制御と深さの制御が容易なことから専ら
用いられるようになっている。
Here, as a method of forming a semiconductor region, initially, a thermal diffusion method in which a gas containing an impurity element or an impurity element is brought into contact with a semiconductor substrate to perform solid phase-vapor phase diffusion or solid phase-solid phase diffusion. Although it was used, the ion implantation method (Ion Implantation), which ionizes the impurity element and gives high energy to it to implant it into the semiconductor substrate, is now mainly used because it is easy to control the concentration and depth of the impurity element. It is being used.

【0003】[0003]

【従来の技術】従来のイオン注入法はイオン注入を行う
Si基板上に二酸化硅素(SiO2) 膜を設け、これをカバー
膜としてイオン注入を行っている。
2. Description of the Related Art Conventional ion implantation methods perform ion implantation.
A silicon dioxide (SiO 2 ) film is provided on a Si substrate, and ion implantation is performed using this as a cover film.

【0004】具体的には乾燥した酸素(O2)ガス雰囲気
中で900℃程度の温度でSi基板を熱処理してSi基板上に
数100 Åの厚さのSiO2膜を作り、このSiO2膜をカバー膜
としてイオン注入を行い、その後、引き続いて窒素
(N2) などの不活性ガス雰囲気中で熱処理して安定した
格子構造とすることにより半導体領域を形成している。
[0004] Specifically, making the dried oxygen (O 2) SiO 2 film having a thickness of several 100 Å on the Si substrate by heat-treating the Si substrate at a temperature of about 900 ° C. in a gas atmosphere, the SiO 2 Ion implantation is performed using the film as a cover film, and subsequently, heat treatment is performed in an atmosphere of an inert gas such as nitrogen (N 2 ) to form a stable lattice structure, thereby forming a semiconductor region.

【0005】この熱処理は一般に活性化アニールと言わ
れている。そして、この処理が終わった後は弗酸(HF)を
用いてSiO2よりなるカバー膜を除去して半導体領域を露
出させている。
This heat treatment is generally called activation annealing. After this process is completed, the cover film made of SiO 2 is removed using hydrofluoric acid (HF) to expose the semiconductor region.

【0006】こゝで、カバー膜を使用することの特徴
は、イオン注入時およびその後の熱処理を行うプロセス
の中で外部より侵入する不純物による汚染を防ぐことに
ある。然し、SiO2膜をカバー膜としてイオン注入を行う
と、SiO2を構成するOイオンが玉突き現象によりSi基板
に叩き込まれると云う現象が生じ、このOイオンがドナ
ー系の不純物を形成したり、半導体領域に欠陥を形成し
たり、イオン注入した不純物イオンの拡散係数を変化さ
せると云う問題を生じていた。
The feature of using the cover film is to prevent contamination by impurities penetrating from the outside during the process of heat treatment during ion implantation and the subsequent heat treatment. However, when ion implantation is performed using the SiO 2 film as a cover film, a phenomenon occurs in which O ions forming SiO 2 are hammered into the Si substrate due to a beading phenomenon, and the O ions form donor-type impurities, Problems such as forming defects in the semiconductor region and changing the diffusion coefficient of ion-implanted impurity ions have occurred.

【0007】[0007]

【発明が解決しようとする課題】イオン注入はSiO2より
なるカバー膜を通して行われているが、加速したイオン
の衝突によってSiO2を構成するOイオンの玉突き現象が
生じてSi基板に叩き込まれ、これにより拡散層の品質が
低下すると云う問題があり、この解決が課題である。
Ion implantation is carried out through a cover film made of SiO 2. However, due to accelerated collision of ions, a beading phenomenon of O ions constituting SiO 2 is generated and the ions are hit into the Si substrate. As a result, there is a problem that the quality of the diffusion layer deteriorates, and the solution is a problem.

【0008】[0008]

【課題を解決するための手段】上記の課題はSi基板に不
純物イオンをイオン注入してSi基板に半導体領域を形成
する工程において、注入種とは異なるタイプの不純物イ
オンを含むポリSi或いは非晶質Siをこの基板のカバー膜
とするか、或いは更にこの上にSiO2膜またはSi 3N4 膜を
被覆して使用して半導体装置の製造方法を構成すること
により解決することができる。
[Means for Solving the Problems] The above problems are not applicable to Si substrates.
Ion implantation of pure ions to form semiconductor region on Si substrate
In the process of
Poly Si or amorphous Si containing ON is a cover film for this substrate.
Or on top of this SiO2Membrane or Si 3NFourThe membrane
Constructing a method of manufacturing a semiconductor device by using it as a coating
Can be solved by.

【0009】[0009]

【作用】本発明はイオン注入を行う際にカバー膜を構成
するOイオンの玉突き現象を無くする方法としてカバー
膜としてポリSi或いは非晶質Siを用いるものである。
The present invention uses poly-Si or amorphous Si as the cover film as a method of eliminating the beading phenomenon of O ions constituting the cover film when performing ion implantation.

【0010】このような方法をとると、Oイオンの叩き
込まれがなく、またカバー膜と基板の材質が同じなため
に従来の問題点をなくすることができる。然し、カバー
膜としてポリSi或いは非晶質Siを用いる場合に生ずる問
題は、 活性化アニールが終わって後、カバー膜を除
去する必要があるが、基板が同一の材料であるために選
択溶解が困難である。 SiO2膜と異なり、ポリSi膜ま
たは非晶質Si膜は活性化アニールなどの処理工程におい
て、外部よりの不純物の拡散を防ぐ作用が劣ることから
SiO2膜をカバー膜とする場合に較べて半導体領域の汚染
が生じ易い。などのことがある。
By adopting such a method, the conventional problems can be eliminated because the O ions are not driven in and the cover film and the substrate are made of the same material. However, the problem that occurs when using poly-Si or amorphous-Si as the cover film is that the cover film needs to be removed after the activation annealing is finished, but since the substrate is the same material, selective dissolution does not occur. Have difficulty. Unlike the SiO 2 film, the poly Si film or the amorphous Si film is inferior in the effect of preventing the diffusion of impurities from the outside in the processing steps such as activation annealing.
Contamination of the semiconductor region is more likely to occur than when a SiO 2 film is used as the cover film. And so on.

【0011】の対策として本発明は、カバー膜の伝導
型を注入種とは異なるタイプとすることにより選択溶解
を可能とするものである。すなわち、N型のSi基板に硼
素(B)を注入してP型の拡散層を形成する場合、カバ
ー膜としてN型となる不純物を含むポリSi膜または非晶
質Si膜を形成しておけば、イオン注入により半導体領域
がP型となることから、BおよびSiを溶かしにくい苛性
カリ(KOH) , イソプロパノールとおよびエチレンジアミ
ンピロカテコールよりなる水溶液に浸漬することにより
カバー膜のみを除去することができる。
As a countermeasure against the above problem, the present invention enables selective dissolution by making the conductivity type of the cover film different from the injection species. That is, when boron (B) is implanted into an N-type Si substrate to form a P-type diffusion layer, a poly-Si film or an amorphous Si film containing an N-type impurity should be formed as a cover film. For example, since the semiconductor region becomes P-type by ion implantation, only the cover film can be removed by immersing it in an aqueous solution of caustic potassium (KOH), isopropanol, and ethylenediaminepyrocatechol, which hardly dissolve B and Si.

【0012】また、の対策として本発明は必要な場
合、ポリSiまたは非晶質Siよりなるカバー膜の上に従来
よりカバー膜として用いられているSiO2或いはSi3N4
薄膜を積層するものである。
As a countermeasure against the above problem, in the present invention, if necessary, a thin film of SiO 2 or Si 3 N 4 conventionally used as a cover film is laminated on a cover film made of poly-Si or amorphous Si. It is a thing.

【0013】このようにすると、イオン注入に当たって
加速電圧の上昇が必要であり、不利益となるように思わ
れるが、SiO2膜或いはSi3N4 膜の厚さは数10Åで足り、
そのために加速電圧の増加は僅かで済ませることができ
る。
If this is done, it is necessary to increase the acceleration voltage for ion implantation, which seems to be disadvantageous, but the thickness of the SiO 2 film or Si 3 N 4 film may be several tens of Å.
Therefore, the acceleration voltage can be slightly increased.

【0014】次に、本発明に係る注入種とは異なるタイ
プの不純物イオンを含むポリSi膜或いは非晶質Si膜はC
VD法,プラズマCVD法,スパッタ法など従来の膜形
成法を用いて作ることができる。
Next, the poly-Si film or amorphous Si film containing impurity ions of a type different from that of the implanted species according to the present invention is C
It can be formed using a conventional film forming method such as a VD method, a plasma CVD method, a sputtering method.

【0015】こゝで、CVD法を用いてポリSi或いは非
晶質Siを形成するには、使用材料とSi基板温度を選択す
ればよく、例えばポリSi膜を作るにはソースガスとして
シラン(SiH4)を用いて約650 ℃の基板温度で行えばよ
く、また非晶質Si膜を作るにはジシラン(Si2H6) を用い
約450 ℃の基板温度で行えばよい。
Here, in order to form poly-Si or amorphous Si by the CVD method, the material used and the Si substrate temperature may be selected. For example, in order to form a poly-Si film, silane ( SiH 4 ) may be used at a substrate temperature of about 650 ° C., and disilane (Si 2 H 6 ) may be used at a substrate temperature of about 450 ° C. to form an amorphous Si film.

【0016】なお、プラズマCVD法を用いると基板温
度を更に下げることができる。
The substrate temperature can be further lowered by using the plasma CVD method.

【0017】[0017]

【実施例】実施例1:図1は本発明の実施工程を示す断
面図であり、燐(P)をドープしてあるN型のSi基板1
の上にSiO2よりなる分離絶縁膜2に囲まれて複数の素子
形成領域3が形成されている。
EXAMPLE 1 FIG. 1 is a cross-sectional view showing the steps for carrying out the present invention, which is an N-type Si substrate 1 doped with phosphorus (P).
A plurality of element forming regions 3 are formed on the upper surface of the device and surrounded by the isolation insulating film 2 made of SiO 2 .

【0018】かゝる基板上にCVD法を用いてPドープ
のポリSiよりなるカバー膜4を200Åの厚さに形成し
た。こゝで、処理条件はキャリアガスとしてH2を,ソー
スガスとしてSiH4をまたドーパントとしてホスフイン(P
H3) を用い、基板温度を650 ℃に保って2分間に亙って
気相反応を行った。( 以上同図A)次に、この基板に対
して弗化硼素イオン(BF2 + ) のイオン注入を行い、素
子形成領域3にP型のウエルを形成した。
A cover film 4 made of P-doped poly-Si having a thickness of 200Å was formed on such a substrate by the CVD method. The processing conditions are H 2 as a carrier gas, SiH 4 as a source gas, and phosphine (P) as a dopant.
Using H 3 ), the substrate temperature was kept at 650 ° C. and the gas phase reaction was carried out for 2 minutes. Next, boron fluoride ion (BF 2 + ) was ion-implanted into this substrate to form a P-type well in the element formation region 3.

【0019】注入条件はエネルギー60 KeV, ドーズ量は
4×1015/cm2である。次に、この基板をN2気流中で1200
℃で6時間に亙って活性化アニールを行い、半導体領域
5を形成した。(以上同図B)次に、KOH とイソプロパ
ノールとエチレンジアミンピロカテコールを溶質とする
水溶液に浸漬することによりN型のカバー膜4を除い
た。(以上同図C) 実施例2:実施例1に使用したと同じ基板を用い、実施
例1と同様にCVD法を用いてPドープのポリSiよりな
るカバー膜4を200 Åの厚さに形成した。
The implantation conditions are an energy of 60 KeV and a dose of 4 × 10 15 / cm 2 . Next, the substrate in an N 2 stream 1200
Activation annealing was performed at 6 ° C. for 6 hours to form the semiconductor region 5. Next, the N-type cover film 4 was removed by immersing it in an aqueous solution containing KOH, isopropanol, and ethylenediaminepyrocatechol as solutes. Example 2 Using the same substrate as that used in Example 1, a cover film 4 made of P-doped poly-Si having a thickness of 200 Å is formed by the same CVD method as in Example 1. Formed.

【0020】次に、PH3 を酸素ガス(O2) に切り換え、
SiH4−O2の反応系を用い、基板温度を425 ℃に保って2
分間に亙ってCVDを行い、約50Åの厚さのSiO2膜を形
成した。
Next, PH 3 is switched to oxygen gas (O 2 ),
Use a SiH 4 -O 2 reaction system and keep the substrate temperature at 425 ℃.
CVD was performed for a period of time to form a SiO 2 film having a thickness of about 50Å.

【0021】次に、この基板に対しイオン注入装置を用
い、BF2 + をエネルギー60 KeV, ドーズ量は4×1015/c
m2の条件でイオン注入を行った後、N2気流中で1200℃で
6時間に亙って活性化アニールを行い、半導体領域を形
成した。
Next, an ion implanter was used for this substrate, and BF 2 + was added at an energy of 60 KeV and a dose of 4 × 10 15 / c.
After performing ion implantation under m 2 condition, activation annealing was performed at 1200 ° C. for 6 hours in N 2 gas flow to form a semiconductor region.

【0022】次に、HF水溶液に浸漬してカバー膜を構成
するSiO2膜を溶解除去した後、KOHとイソプロパノール
とエチレンジアミンピロカテコールを溶質とする水溶液
に浸漬してN型のポリSi膜を除いた。
Next, the SiO 2 film forming the cover film is dissolved and removed by immersing in an HF aqueous solution, and then the N type poly-Si film is removed by immersing in an aqueous solution containing KOH, isopropanol and ethylenediaminepyrocatechol as solutes. It was

【0023】[0023]

【発明の効果】本発明の実施によりカバー層としてSiO2
を用いる場合に半導体領域に生ずる欠陥や電気的特性の
劣化を解消することができ良質の半導体領域を形成する
ことができる。
As a result of the practice of the present invention, SiO 2 is used as the cover layer.
When using, it is possible to eliminate defects and deterioration of electrical characteristics that occur in the semiconductor region, and it is possible to form a good-quality semiconductor region.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の工程を示す断面図である。FIG. 1 is a cross-sectional view showing a process of the present invention.

【符号の説明】[Explanation of symbols]

1 Si基板 3 素子形成領域 4 カバー膜 5 半導体領域 1 Si substrate 3 element formation region 4 cover film 5 semiconductor region

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 シリコン基板に不純物イオンをイオン注
入して該シリコン基板に半導体領域を形成する工程にお
いて、注入種とは異なるタイプの不純物イオンを含むポ
リシリコン或いは非晶質シリコンを該基板のカバー膜と
して使用することを特徴とする半導体装置の製造方法。
1. In the step of implanting impurity ions into a silicon substrate to form a semiconductor region in the silicon substrate, the substrate is covered with polysilicon or amorphous silicon containing impurity ions of a type different from the implantation species. A method for manufacturing a semiconductor device, which is used as a film.
【請求項2】 前記カバー膜として用いるポリシリコン
或いは非晶質シリコンの上に更に二酸化硅素膜または窒
化硅素膜を被覆して使用することを特徴とする請求項1
記載の半導体装置の製造方法。
2. The polysilicon or amorphous silicon used as the cover film is further covered with a silicon dioxide film or a silicon nitride film for use.
A method of manufacturing a semiconductor device according to claim 1.
JP23265891A 1991-09-12 1991-09-12 Manufacture of semiconductor device Withdrawn JPH0574729A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23265891A JPH0574729A (en) 1991-09-12 1991-09-12 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23265891A JPH0574729A (en) 1991-09-12 1991-09-12 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH0574729A true JPH0574729A (en) 1993-03-26

Family

ID=16942761

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23265891A Withdrawn JPH0574729A (en) 1991-09-12 1991-09-12 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH0574729A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297113B1 (en) 1998-04-03 2001-10-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device, and a semiconductor device manufactured thereby
JP2005217151A (en) * 2004-01-29 2005-08-11 Fujitsu Ltd Semiconductor device and manufacturing method thereof

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297113B1 (en) 1998-04-03 2001-10-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing a semiconductor device, and a semiconductor device manufactured thereby
DE19853433B4 (en) * 1998-04-03 2005-07-07 Mitsubishi Denki K.K. Manufacturing method of a semiconductor device
JP2005217151A (en) * 2004-01-29 2005-08-11 Fujitsu Ltd Semiconductor device and manufacturing method thereof

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Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 19981203