JPS6453413A - Formation of impurity diffusion layer - Google Patents

Formation of impurity diffusion layer

Info

Publication number
JPS6453413A
JPS6453413A JP62209147A JP20914787A JPS6453413A JP S6453413 A JPS6453413 A JP S6453413A JP 62209147 A JP62209147 A JP 62209147A JP 20914787 A JP20914787 A JP 20914787A JP S6453413 A JPS6453413 A JP S6453413A
Authority
JP
Japan
Prior art keywords
impurity diffusion
teos
diffusion layer
wall
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62209147A
Other languages
Japanese (ja)
Inventor
Toshiharu Akimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP62209147A priority Critical patent/JPS6453413A/en
Publication of JPS6453413A publication Critical patent/JPS6453413A/en
Pending legal-status Critical Current

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  • Chemical Vapour Deposition (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To uniformly form a very shallow high concentration impurity diffusion layer on the inner wall of a groove by a method wherein, after a CVD film which is doped by the use of an organic compound impurity diffusion source such as tetraethoxysilane/trimethyl phosphate and the like, has been uniformly applied to the inner wall surface of a groove, impurities are subjected to solid-phase diffusion from the impurity diffusion source using an arc lamp. CONSTITUTION:After an HTO film 2, to be used for prevention of silicon wafer diffusion and having the inner wall part 1 of very narrow and deep trench of 1.5mum in width and 15mum in depth, has been coated, it is placed in a vacuum furnace. Then, tetraethoxysilane (TEOS) and trimethyl phosphate (TMPO) are introduced into the vacuum furnace, and a phosphorus-added glass (TEOS PSG) film 3 is formed. Then, when light 4 an xenon arc lamp is projected, solid-phase diffusion is generated from the TEOS PSG 3, a very shallow and high concentration impurity diffusion layer 5 of surface concentration of 5X10<19>cm<-3>, junction depth of 0.13mum, can be formed uniformly on the side face and the bottom part of the inner wall part.
JP62209147A 1987-08-25 1987-08-25 Formation of impurity diffusion layer Pending JPS6453413A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62209147A JPS6453413A (en) 1987-08-25 1987-08-25 Formation of impurity diffusion layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62209147A JPS6453413A (en) 1987-08-25 1987-08-25 Formation of impurity diffusion layer

Publications (1)

Publication Number Publication Date
JPS6453413A true JPS6453413A (en) 1989-03-01

Family

ID=16568087

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62209147A Pending JPS6453413A (en) 1987-08-25 1987-08-25 Formation of impurity diffusion layer

Country Status (1)

Country Link
JP (1) JPS6453413A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03214725A (en) * 1990-01-19 1991-09-19 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPH04245424A (en) * 1991-01-30 1992-09-02 Nippon Precision Circuits Kk Manufacture of semiconductor device
JP2005197638A (en) * 2003-12-30 2005-07-21 Hynix Semiconductor Inc High frequency semiconductor device and its manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03214725A (en) * 1990-01-19 1991-09-19 Nippon Telegr & Teleph Corp <Ntt> Manufacture of semiconductor device
JPH04245424A (en) * 1991-01-30 1992-09-02 Nippon Precision Circuits Kk Manufacture of semiconductor device
JP2005197638A (en) * 2003-12-30 2005-07-21 Hynix Semiconductor Inc High frequency semiconductor device and its manufacturing method

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