JPH07161820A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH07161820A
JPH07161820A JP5341698A JP34169893A JPH07161820A JP H07161820 A JPH07161820 A JP H07161820A JP 5341698 A JP5341698 A JP 5341698A JP 34169893 A JP34169893 A JP 34169893A JP H07161820 A JPH07161820 A JP H07161820A
Authority
JP
Japan
Prior art keywords
oxide film
formation region
boron
gate oxide
transistor formation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5341698A
Other languages
Japanese (ja)
Inventor
Hidekuni Nishimura
英訓 西村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP5341698A priority Critical patent/JPH07161820A/en
Publication of JPH07161820A publication Critical patent/JPH07161820A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To form oxide films of different film thicknesses in one oxidation process by varying the introduction concentration of impurities. CONSTITUTION:The surface of a standard-withstand voltage transistor formation region 3A is covered with a resist 10. In succession, boron is introduced, by making use of the resist 10 as a mask, only into a high-withstand voltage- transistor formation region 3B in which a silicon face has been exposed. After that, the resist 10 is removed, and a wafer is wet-oxidized. Then, a thin gate oxide film 11A is formed in the boron-undoped standard-withstand voltage- transistor formation region 3A, and a gate oxide film 11B whose film thickness is thick is formed in the boron-doped high-withstand voltage-transistor formation region 3B. Since the gate oxide films 11A, 11B with different thicknesses can be formed simultaneously in one oxidation process, the number of processes can be reduced as compared with conventional cases.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置の製造方法に
関し、例えば耐圧の異なる2種類のトランジスタを内蔵
する半導体装置の製造方法に適用して好適なものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and is suitable for application to, for example, a method for manufacturing a semiconductor device containing two types of transistors having different breakdown voltages.

【0002】[0002]

【従来の技術】今日、金属酸化膜半導体(MOS:meta
l oxide semiconductor )大規模集積回路においては、
高電圧等に対する耐圧を確保するためゲート酸化膜を厚
くした高耐圧型のトランジスタが広く用いられている。
ところで集積回路には高耐圧が要求される回路部分と通
常の耐圧で十分な回路部分とがあり、通常は、高耐圧ト
ランジスタと標準耐圧トランジスタとが混在している。
2. Description of the Related Art Today, metal oxide semiconductor (MOS: meta)
In large-scale integrated circuits,
A high breakdown voltage type transistor having a thick gate oxide film is widely used to secure a breakdown voltage against a high voltage or the like.
By the way, an integrated circuit has a circuit portion that requires a high breakdown voltage and a circuit portion that has a sufficient breakdown voltage. Normally, a high breakdown voltage transistor and a standard breakdown voltage transistor are mixed.

【0003】このように耐圧の異なるトランジスタを集
積回路に形成するには、図4に示すような製造方法が用
いられている。まず前処理によつてシリコン基板1のフ
イールド領域に素子分離酸化膜(LOCOS:local ox
idation of silicon)2を形成する。その後、素子形成
領域上を覆う酸化膜をウエツトエツチングによつて取り
除き、素子形成領域のシリコン面を露出する。この段階
の断面構造が図4(A)である。
In order to form transistors having different breakdown voltages in an integrated circuit, a manufacturing method as shown in FIG. 4 is used. First, an element isolation oxide film (LOCOS: local ox) is formed in the field region of the silicon substrate 1 by pretreatment.
Idation of silicon) 2 is formed. After that, the oxide film covering the element formation region is removed by wet etching to expose the silicon surface of the element formation region. A cross-sectional structure at this stage is FIG.

【0004】この後、1回目の酸化処理に移る。この酸
化処理には水素ガスと酸素ガスを反応炉外にて燃焼させ
るパイロジエニツク装置が用いられる。この酸化処理に
より標準耐圧トランジスタ形成領域3A及び高耐圧トラ
ンジスタ形成領域3Bにそれぞれ約24〔nm〕の膜厚のゲ
ート酸化膜が形成される。この段階の断面構造が図4
(B)である。続いて図4(C)に示すように、高耐圧
トランジスタ形成領域3Bに形成されたゲート酸化膜の
表面をレジスト4によつて覆い、この状態で標準耐圧ト
ランジスタ形成領域3A部分のゲート酸化膜をウエツト
エツチングする。
After this, the first oxidation process is performed. For this oxidation treatment, a pyrogenetic device that burns hydrogen gas and oxygen gas outside the reaction furnace is used. By this oxidation treatment, a gate oxide film having a film thickness of about 24 [nm] is formed in each of the standard breakdown voltage transistor formation region 3A and the high breakdown voltage transistor formation region 3B. The sectional structure at this stage is shown in FIG.
(B). Subsequently, as shown in FIG. 4C, the surface of the gate oxide film formed in the high breakdown voltage transistor formation region 3B is covered with a resist 4, and in this state, the gate oxide film in the standard breakdown voltage transistor formation region 3A is covered. Wet etching.

【0005】このエツチング処理により標準耐圧トラン
ジスタ形成領域3A部分のゲート酸化膜を取り除いた状
態が図4(D)である。この工程が終了すると、レジス
ト4をアツシングによつて取り除き、2回目の酸化処理
に移る。この酸化処理にもパイロジエニツク装置が用い
られる。これにより標準耐圧トランジスタ形成領域3A
には2回目の酸化処理によつて形成されたゲート酸化膜
が形成され、高耐圧トランジスタ形成領域3Bには1回
目と2回目の酸化処理によつて形成されたゲート酸化膜
が重ねて形成されることになる。
FIG. 4D shows a state in which the gate oxide film in the standard breakdown voltage transistor forming region 3A is removed by this etching process. When this step is completed, the resist 4 is removed by asking, and the second oxidation process is performed. A pyrogenetic device is also used for this oxidation treatment. As a result, the standard breakdown voltage transistor forming region 3A is formed.
Is formed with a gate oxide film formed by the second oxidation process, and the gate oxide film formed by the first and second oxidation processes is formed over the high breakdown voltage transistor formation region 3B. Will be.

【0006】すなわち図4(E)に示すように、標準耐
圧トランジスタ形成領域3Aには20.5〔nm〕の膜厚のゲ
ート酸化膜5Aが形成されるのに対し、高耐圧トランジ
スタ形成領域3Bには40〔nm〕の膜厚のゲート酸化膜5
Bが形成される。
That is, as shown in FIG. 4E, a gate oxide film 5A having a film thickness of 20.5 [nm] is formed in the standard breakdown voltage transistor formation region 3A, while a high breakdown voltage transistor formation region 3B is formed. 40 [nm] thick gate oxide film 5
B is formed.

【0007】[0007]

【発明が解決しようとする課題】このように従来の場合
には2回の酸化工程とレジストパターンニング工程等が
膜厚の異なるゲート酸化膜5A及び5Bを形成するのに
必要である。しかしながらこれらの工程よりも少ない工
程でこれらのゲート酸化膜を形成することができれば生
産効率は一段と向上すると考えられる。
As described above, in the conventional case, two oxidation steps and a resist patterning step are required to form the gate oxide films 5A and 5B having different film thicknesses. However, if these gate oxide films can be formed in fewer steps than these steps, it is considered that the production efficiency will be further improved.

【0008】本発明は以上の点を考慮してなされたもの
で、従来に比して生産効率に優れた半導体装置の製造方
法を提案しようとするものである。
The present invention has been made in view of the above points, and an object thereof is to propose a method of manufacturing a semiconductor device which is more excellent in production efficiency than ever before.

【0009】[0009]

【課題を解決するための手段】かかる課題を解決するた
め本発明においては、第1の膜厚の酸化膜11Bが形成
される第1の酸化膜形成領域3Bと、第1の膜厚に比し
て薄い第2の膜厚の酸化膜11Aが形成される第2の酸
化膜形成領域3Aとを有する半導体装置の製造方法にお
いて、シリコン面1が共に露出された第1及び第2の酸
化膜形成領域3A及び3Bのうち第2の酸化膜形成領域
3Aのシリコン面1をレジストパターン10によつて覆
う工程と、第1の酸化膜形成領域3Bのシリコン面1に
のみ不純物を導入する工程と、レジストパターン10を
除去した後、第1及び第2の酸化膜形成領域3A及び3
Bを同時に酸化する工程とを設けるようにする。
In order to solve such a problem, according to the present invention, the first oxide film forming region 3B in which the oxide film 11B having the first film thickness is formed and the first oxide film forming region 3B And a second oxide film forming region 3A in which an oxide film 11A having a second thin film thickness is formed. In the method for manufacturing a semiconductor device, the first and second oxide films having the silicon surface 1 exposed together are formed. Of the formation regions 3A and 3B, a step of covering the silicon surface 1 of the second oxide film formation region 3A with a resist pattern 10, and a step of introducing impurities only into the silicon surface 1 of the first oxide film formation region 3B. After removing the resist pattern 10, the first and second oxide film forming regions 3A and 3 are formed.
And a step of simultaneously oxidizing B.

【0010】[0010]

【作用】不純物が導入されたシリコン面には不純物が導
入されていないシリコン面に比して酸化膜が速く形成さ
れる性質がある。従つて1度の酸化工程によつて、不純
物が導入されている第1の酸化膜形成領域3Bには厚い
酸化膜11Bを形成することができ、また第2の酸化膜
形成領域3Aには膜厚の薄い酸化膜11Aを形成するこ
とができる。このように膜厚の異なる酸化膜11A及び
11Bを1回の酸化工程によつて形成することができる
ため従来に比して製造効率を高めることができる。
The oxide film is formed on the silicon surface having impurities introduced faster than the silicon surface having no impurities introduced. Therefore, a thick oxide film 11B can be formed in the first oxide film forming region 3B in which impurities are introduced, and a film can be formed in the second oxide film forming region 3A by one oxidation process. A thin oxide film 11A can be formed. In this way, the oxide films 11A and 11B having different film thicknesses can be formed by a single oxidation process, so that the manufacturing efficiency can be improved as compared with the conventional case.

【0011】[0011]

【実施例】以下図面について、本発明の一実施例を詳述
する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

【0012】図4との対応部分に同一符号を付して示す
図1によつて、厚みの異なるゲート酸化膜を1回の酸化
工程によつて形成する製造方法を説明する。まず従来の
場合と同様、前工程によつてフイールド領域に素子分離
酸化膜2を形成する。この後、緩衝フツ酸(フツ酸(H
F)とフツ化アンモニウム(NH4F)とを混合液)に
よつて素子形成領域3A及び3Bを覆う酸化膜を取り除
き、図1(A)の構造を得る。
A manufacturing method for forming gate oxide films having different thicknesses by a single oxidation step will be described with reference to FIG. 1 in which parts corresponding to those in FIG. First, as in the conventional case, the element isolation oxide film 2 is formed in the field region by the previous process. After this, buffered hydrofluoric acid (hydrofluoric acid (H
The oxide film covering the element forming regions 3A and 3B is removed with a mixed solution of F) and ammonium fluoride (NH4F) to obtain the structure of FIG.

【0013】従来の製造工程ではこの段階で1回目の酸
化工程に移ることになるが、この実施例では、図1
(B)に示すように、標準耐圧トランジスタ形成領域3
Aの表面をレジスト10によつて覆う。続いて図1
(C)に示すように、レジスト10をマスクとしてシリ
コン面が露出した高耐圧トランジスタ形成領域3Bのに
のみホウ素(B:boron )を導入する。
In the conventional manufacturing process, the first oxidation process is performed at this stage, but in this embodiment, as shown in FIG.
As shown in (B), the standard breakdown voltage transistor formation region 3
The surface of A is covered with a resist 10. Continuing with Figure 1
As shown in (C), boron (B: boron) is introduced only into the high breakdown voltage transistor formation region 3B where the silicon surface is exposed using the resist 10 as a mask.

【0014】これはホウ素が導入されている場合と導入
されていない場合とでウエツト酸化の際に成長される酸
化膜の膜厚に差が生じるシリコンの性質を利用するため
である。
This is to utilize the property of silicon that causes a difference in the film thickness of the oxide film grown during wet oxidation between the case where boron is introduced and the case where boron is not introduced.

【0015】例えば図2に示すように、ホウ素が 1.0×
1016〔atom/cm3 〕程度導入されているシリコンと
2.5×1020〔atom/cm3 〕程度導入されているシリコ
ンとでは、1000〔℃〕の温度条件下で40〔分〕ウエツト
酸化した際に形成される酸化膜の膜厚に差が生じること
になる。すなわち濃度の高いシリコンの方が濃度の低い
シリコンに比して数10〔nm〕程度膜厚が厚くなる。因に
ホウ素の場合には酸化温度が低いほど酸化速度に差が生
じる。
For example, as shown in FIG. 2, boron is 1.0 ×
Silicon introduced about 10 16 [atom / cm 3 ]
About 2.5 × 10 20 [atom / cm 3 ] is introduced, and there is a difference in the film thickness of the oxide film formed by wet oxidation for 40 [min] under the temperature condition of 1000 [℃]. become. That is, the film thickness of the high-concentration silicon becomes thicker than the low-concentration silicon by about several tens of nm. In the case of boron, the lower the oxidation temperature is, the more difference the oxidation rate is.

【0016】従つてホウ素を導入した工程の後、レジス
ト10を取り除いてウエハをウエツト酸化すると、図1
(D)に示すように、ホウ素が導入されていない標準耐
圧トランジスタ形成領域3Aには膜厚の薄いゲート酸化
膜11Aが形成されるのに対し、ホウ素が導入されてい
る高耐圧トランジスタ形成領域3Bには膜厚の厚いゲー
ト酸化膜11Bが形成されることになる。
Accordingly, after the step of introducing boron, the resist 10 is removed and the wafer is wet-oxidized.
As shown in (D), the thin gate oxide film 11A is formed in the standard breakdown voltage transistor formation region 3A in which boron is not introduced, whereas the high breakdown voltage transistor formation region 3B in which boron is introduced is formed. The gate oxide film 11B having a large film thickness is formed on the substrate.

【0017】以上の工程によれば、1回の酸化工程によ
つて膜厚の異なるゲート酸化膜11A及び11Bを同時
に作り分けることができ、従来に比して一段と工程数を
削減することができる。またゲート酸化膜11Bの膜厚
は導入するホウ素のドーズ量によつて制御できるためゲ
ート酸化膜の膜厚制御を従来に比して一段と簡易にする
ことができる。
According to the above steps, the gate oxide films 11A and 11B having different film thicknesses can be formed simultaneously by one oxidation step, and the number of steps can be further reduced as compared with the conventional method. . Further, since the film thickness of the gate oxide film 11B can be controlled by the dose amount of boron to be introduced, the film thickness control of the gate oxide film can be further simplified as compared with the conventional case.

【0018】なお上述の実施例においては、 1.0×10
16〔atom/cm3 〕程度のホウ素が導入されているシリコ
ンと 2.5×1020〔atom/cm3 〕程度のホウ素が導入さ
れているシリコンとを1000〔℃〕の温度条件下で40
〔分〕間ウエツト酸化することを例にとりホウ素の導入
による効果を述べたが、酸化膜の膜厚はプロセス条件
(酸化時間や酸化温度)によつても異なるためホウ素の
ドーズ量やプロセス条件は要求される膜厚や膜厚差に応
じて最適なものを用いれば良い。因にドーズ量及び酸化
温度に対する酸化膜の検量線を予め求めておくとドーズ
量を容易に決定することができる。
In the above embodiment, 1.0 × 10
Silicon containing about 16 [atom / cm 3 ] of boron and silicon containing about 2.5 × 10 20 [atom / cm 3 ] of boron at a temperature of 1000 [° C.] 40
The effect of introducing boron was described using wet oxidation for [minutes] as an example. However, since the thickness of the oxide film varies depending on the process conditions (oxidation time and oxidation temperature), the dose amount of boron and the process conditions are The optimum film may be used depending on the required film thickness and film thickness difference. Incidentally, if the calibration curve of the oxide film with respect to the dose amount and the oxidation temperature is obtained in advance, the dose amount can be easily determined.

【0019】また上述の実施例においては、ホウ素を高
耐圧トランジスタ形成領域3Bに導入する場合について
述べたが、本発明はこれに限らず、燐を導入する場合に
も適用し得る。この場合、図3に示す特性曲線が得られ
る。またホウ素や燐に限らず他の不純物を導入しても良
い。
Further, in the above-mentioned embodiment, the case where boron is introduced into the high breakdown voltage transistor forming region 3B has been described, but the present invention is not limited to this, and can be applied to the case where phosphorus is introduced. In this case, the characteristic curve shown in FIG. 3 is obtained. In addition to boron and phosphorus, other impurities may be introduced.

【0020】さらに上述の実施例においては、ウエツト
酸化によつてゲート酸化膜を形成する場合について述べ
たが、本発明はこれに限らず、ドライ酸化や水素燃焼酸
化等によつて酸化する場合にも適用し得る。
Furthermore, in the above-mentioned embodiments, the case where the gate oxide film is formed by wet oxidation has been described, but the present invention is not limited to this, and in the case where oxidation is performed by dry oxidation, hydrogen combustion oxidation or the like. Can also be applied.

【0021】また上述の実施例においては、不純物をシ
リコン基板1中に導入することによりシリコン基板上に
膜厚の異なる酸化膜をそれぞれ形成する場合について述
べたが、この不純物の導入にはイオン注入や拡散処理を
用いれば良い。
Further, in the above-mentioned embodiment, the case where the oxide films having different film thicknesses are respectively formed on the silicon substrate by introducing the impurities into the silicon substrate 1 has been described. Or diffusion processing may be used.

【0022】さらに上述の実施例においては、膜厚を厚
くしたい方のシリコン面にのみ不純物を導入する場合に
ついて述べたが、本発明はこれに限らず、いずれのシリ
コン面にも要求される膜厚に応じて濃度の異なる不純物
を導入しても良い。
Furthermore, in the above-mentioned embodiments, the case where the impurities are introduced only into the silicon surface of which the film thickness is desired to be increased has been described, but the present invention is not limited to this, and the film required for any silicon surface. Impurities having different concentrations may be introduced depending on the thickness.

【0023】さらに上述の実施例においては、シリコン
基板上に標準耐圧トランジスタと高耐圧トランジスタを
形成する方法について述べたが、本発明はこれに限ら
ず、シリコン基板上に膜厚の異なる酸化膜を形成する工
程を含む半導体製造装置の製造方法に広く適用し得る。
Further, in the above-mentioned embodiments, the method of forming the standard breakdown voltage transistor and the high breakdown voltage transistor on the silicon substrate has been described, but the present invention is not limited to this, and oxide films having different thicknesses are formed on the silicon substrate. It can be widely applied to a method of manufacturing a semiconductor manufacturing device including a step of forming.

【0024】[0024]

【発明の効果】上述のように本発明によれば、不純物が
導入されたシリコン面には不純物が導入されていないシ
リコン面に比して酸化膜が速く形成される性質を用いる
ことにより膜厚の異なる酸化膜を1回の酸化工程によつ
て形成することができ、従来に比して工程数の少ない半
導体装置の製造方法を実現することができる。
As described above, according to the present invention, the film thickness is improved by using the property that the oxide film is formed faster on the silicon surface in which impurities are introduced than in the silicon surface in which impurities are not introduced. Different oxide films can be formed by a single oxidation step, and a semiconductor device manufacturing method with a smaller number of steps than the conventional method can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明による半導体装置の製造方法の一実施例
を示す工程図である。
FIG. 1 is a process chart showing an embodiment of a method for manufacturing a semiconductor device according to the present invention.

【図2】不純物の濃度と酸化膜の成長速度との関係を示
す特性曲線図である。
FIG. 2 is a characteristic curve diagram showing the relationship between the concentration of impurities and the growth rate of an oxide film.

【図3】不純物の濃度と酸化膜の成長速度との関係を示
す特性曲線図である。
FIG. 3 is a characteristic curve diagram showing the relationship between the concentration of impurities and the growth rate of an oxide film.

【図4】従来の半導体装置の製造方法を示す工程図であ
る。
FIG. 4 is a process chart showing a conventional method of manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1……シリコン基板、2……素子間分離酸化膜、3A…
…標準耐圧トランジスタ形成領域、3B……高耐圧トラ
ンジスタ形成領域、4、10……レジスト、5A、5
B、11A、11B……ゲート酸化膜。
1 ... Silicon substrate, 2 ... Element isolation oxide film, 3A ...
... Standard breakdown voltage transistor formation region, 3B ... High breakdown voltage transistor formation region, 4,10 ... resist, 5A, 5
B, 11A, 11B ... Gate oxide film.

【手続補正書】[Procedure amendment]

【提出日】平成5年12月10日[Submission date] December 10, 1993

【手続補正1】[Procedure Amendment 1]

【補正対象書類名】図面[Document name to be corrected] Drawing

【補正対象項目名】図1[Name of item to be corrected] Figure 1

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図1】 [Figure 1]

【手続補正2】[Procedure Amendment 2]

【補正対象書類名】図面[Document name to be corrected] Drawing

【補正対象項目名】図4[Name of item to be corrected] Fig. 4

【補正方法】変更[Correction method] Change

【補正内容】[Correction content]

【図4】 [Figure 4]

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】第1の膜厚の酸化膜が形成される第1の酸
化膜形成領域と、上記第1の膜厚に比して薄い第2の膜
厚の酸化膜が形成される第2の酸化膜形成領域とを有す
る半導体装置の製造方法において、 シリコン面が共に露出された上記第1及び第2の酸化膜
形成領域のうち上記第2の酸化膜形成領域のシリコン面
をレジストパターンによつて覆う工程と、 上記第1の酸化膜形成領域のシリコン面に不純物を導入
する工程と、 上記レジストパターンを除去した後、上記第1及び第2
の酸化膜形成領域を同時に酸化する工程とを具えること
を特徴とする半導体装置の製造方法。
1. A first oxide film forming region in which an oxide film having a first film thickness is formed, and a second oxide film in which a second film thickness is formed thinner than the first film thickness. In the method of manufacturing a semiconductor device having a second oxide film forming region, a silicon pattern of the second oxide film forming region of the first and second oxide film forming regions exposed in the silicon surface is used as a resist pattern. Covering step, a step of introducing impurities into the silicon surface of the first oxide film forming region, and the first and second steps after removing the resist pattern.
And a step of simultaneously oxidizing the oxide film forming region of the above.
【請求項2】上記不純物を拡散工程によつて導入するこ
とを特徴とする請求項1に記載の半導体装置の製造方
法。
2. The method for manufacturing a semiconductor device according to claim 1, wherein the impurities are introduced by a diffusion process.
【請求項3】上記第1及び第2の酸化膜形成領域をそれ
ぞれウエツト酸化法によつて酸化することを特徴とする
請求項1又は請求項2に記載の半導体装置の製造方法。
3. The method of manufacturing a semiconductor device according to claim 1, wherein the first and second oxide film forming regions are each oxidized by a wet oxidation method.
JP5341698A 1993-12-09 1993-12-09 Manufacture of semiconductor device Pending JPH07161820A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5341698A JPH07161820A (en) 1993-12-09 1993-12-09 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5341698A JPH07161820A (en) 1993-12-09 1993-12-09 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH07161820A true JPH07161820A (en) 1995-06-23

Family

ID=18348086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5341698A Pending JPH07161820A (en) 1993-12-09 1993-12-09 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH07161820A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100334390B1 (en) * 1998-12-28 2002-07-18 박종섭 Manufacturing method for dual gate oxide
KR100424603B1 (en) * 2000-07-21 2004-03-24 산요덴키가부시키가이샤 Method of manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100334390B1 (en) * 1998-12-28 2002-07-18 박종섭 Manufacturing method for dual gate oxide
KR100424603B1 (en) * 2000-07-21 2004-03-24 산요덴키가부시키가이샤 Method of manufacturing semiconductor device
US6861372B2 (en) 2000-07-21 2005-03-01 Sanyo Electric Co., Ltd. Semiconductor device manufacturing method

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