JPS6190466A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6190466A JPS6190466A JP21236884A JP21236884A JPS6190466A JP S6190466 A JPS6190466 A JP S6190466A JP 21236884 A JP21236884 A JP 21236884A JP 21236884 A JP21236884 A JP 21236884A JP S6190466 A JPS6190466 A JP S6190466A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polycrystalline silicon
- oxidation
- polycrystalline
- silicon film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 230000003647 oxidation Effects 0.000 claims abstract description 23
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 9
- 239000012212 insulator Substances 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 230000003064 anti-oxidating effect Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 44
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 21
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 12
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 9
- 229910052681 coesite Inorganic materials 0.000 abstract description 8
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 8
- 239000000377 silicon dioxide Substances 0.000 abstract description 8
- 229910052682 stishovite Inorganic materials 0.000 abstract description 8
- 229910052905 tridymite Inorganic materials 0.000 abstract description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 6
- 239000001301 oxygen Substances 0.000 abstract description 6
- 229910052760 oxygen Inorganic materials 0.000 abstract description 6
- 239000010453 quartz Substances 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 3
- 150000002500 ions Chemical class 0.000 abstract 1
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 84
- 238000007796 conventional method Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、少なくともその表面が絶縁物から成る基板上
に形成された半導体膜を酸化することによりこの半導体
膜を薄膜化するようにした半導体装置の製造方法に関し
、多結晶シリコン薄膜トランジスタの製造に用いて最適
なものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor device in which a semiconductor film formed on a substrate, at least the surface of which is made of an insulator, is thinned by oxidizing the semiconductor film. Regarding the manufacturing method, this method is most suitable for use in manufacturing polycrystalline silicon thin film transistors.
従来の技術
従来、多結晶シリコン超薄膜トランジスタ（ＴＰＴ）の
製造にあたっては、まず第５図に示すように例えば石英
基板１上にＳｉＯ□膜２及び所定形状の多結晶シリコン
膜３（素子形成領域）を順次形成し、次いで酸素雰囲気
中において熱酸化（ゲート酸化）を行うことにより、こ
の多結晶シリコン膜３の表面に第５Ｂ図に示すようにＳ
ｉＯ２膜４（ゲート酸化膜）を形成すると共に、この多
結晶シリコン膜３を所定膜厚に薄膜化するようにしてい
る。2. Description of the Related Art Conventionally, in manufacturing a polycrystalline silicon ultra-thin film transistor (TPT), first, as shown in FIG. By sequentially forming S and then performing thermal oxidation (gate oxidation) in an oxygen atmosphere, S is formed on the surface of this polycrystalline silicon film 3 as shown in FIG. 5B.
While forming the iO2 film 4 (gate oxide film), the polycrystalline silicon film 3 is thinned to a predetermined thickness.
ところがこの酸化の際には、酸素は、多結晶シリコン膜
３の上部から侵入してこの多結晶シリコン膜３の端部の
下方から例えば矢印Ａ（第５Ａ図参照）で示す経路で侵
入してこの多結晶シリコン膜３を下部からも酸化する。However, during this oxidation, oxygen enters from the upper part of the polycrystalline silicon film 3 and enters from below the edge of the polycrystalline silicon film 3 along the path shown by arrow A (see FIG. 5A), for example. This polycrystalline silicon film 3 is also oxidized from the bottom.
その結果、多結晶シリコン膜３の端部におけるＳｉＯ□
膜４の膜厚Ｘは、第５Ｂ図に示すように、多結晶シリコ
ン膜３の上面におけるＳｉｎｇ膜４の膜厚に比べて極め
て大きくなるので、この分だけ多結晶シリコン膜３の幅
が小さくなってしまう。例えば、第５Ａ図の状態におけ
る多結晶シリコン膜３の膜厚を８００人とすると、ゲー
ト酸化により膜厚１０００人のＳｉｎｇ膜４を形成した
場合、このＸの値は約１．０μｍにもなる。このため、
石英基ｖｉＩ上にＴＰＴを集積化する場合には、各ＴＰ
Ｔを構成する多結晶シリコン膜３０面積を大きくする必
要があり、従ってＴＰＴの集積密度を高くするのが難し
い。As a result, SiO□ at the edge of the polycrystalline silicon film 3
As shown in FIG. 5B, the film thickness X of the film 4 is extremely large compared to the film thickness of the Sing film 4 on the upper surface of the polycrystalline silicon film 3, so the width of the polycrystalline silicon film 3 is reduced by this amount. turn into. For example, if the thickness of the polycrystalline silicon film 3 in the state shown in FIG. 5A is 800, and the Sing film 4 with a thickness of 1,000 is formed by gate oxidation, the value of X will be about 1.0 μm. . For this reason,
When integrating TPT on quartz base viI, each TP
It is necessary to increase the area of the polycrystalline silicon film 30 constituting the T, and therefore it is difficult to increase the integration density of the TPT.
発明が解決しようとする問題点
本発明は、上述の問題にかんがみ、従来のＴＰＴ等の半
導体装置の製造方法が有する上述のような欠点を是正し
た半導体装置の製造方法を提供することを目的とする。Problems to be Solved by the Invention In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing a semiconductor device that corrects the above-mentioned drawbacks of the conventional method for manufacturing semiconductor devices such as TPT. do.
問題点を解決するための手段
本発明に係る半導体装置の製造方法は、少なくともその
表面が絶縁物から成る基板（例えば石英基板１）上に形
成された半導体膜（例えば多結晶シリコン膜３ａ）を酸
化することによりこの半導体膜を薄膜化するようにした
半導体装置の製造方法において、上記半導体膜を選択的
に除去して所定形状の素子形成領域を形成し、次いでこ
の所定形状の素子形成領域の周囲に耐酸化処理を施し、
この後上記酸化を行うようにしている。Means for Solving the Problems A method for manufacturing a semiconductor device according to the present invention includes a semiconductor film (for example, polycrystalline silicon film 3a) formed on a substrate (for example, quartz substrate 1) at least the surface of which is made of an insulator. In a method of manufacturing a semiconductor device in which the semiconductor film is thinned by oxidation, the semiconductor film is selectively removed to form an element formation region of a predetermined shape, and then the element formation region of the predetermined shape is removed. Oxidation-resistant treatment is applied to the surrounding area,
After this, the above oxidation is performed.
作用
このようにするこ゛とによって、酸化時に素子形成領域
の端部の下方から酸素がこの素子形成領域に侵入するの
を効果的に防止することができる。By doing this, it is possible to effectively prevent oxygen from entering the element forming region from below the end portion of the element forming region during oxidation.
実施例
以下本発明に係る半導体装置の製造方法を多結晶シリコ
ンＴＰＴの製造に適用した実施例につき図面を参照しな
がら説明する。EXAMPLE Hereinafter, an example in which the method for manufacturing a semiconductor device according to the present invention is applied to manufacturing a polycrystalline silicon TPT will be described with reference to the drawings.
まず本発明の第１実施例を第１Ａ図〜第１Ｄ図に基づい
て説明する。First, a first embodiment of the present invention will be described based on FIGS. 1A to 1D.
第１Ａ図に示すように、まず石英基板１に例えばＣＶＤ
法によりＳｉＯ□膜２及び多結晶シリコン膜３を順次被
着形成した後、この多結晶シリコン膜３上に所定形状の
フォトレジスト６を形成する。As shown in FIG. 1A, first, a quartz substrate 1 is coated with, for example, CVD.
After a SiO□ film 2 and a polycrystalline silicon film 3 are sequentially deposited by a method, a photoresist 6 having a predetermined shape is formed on the polycrystalline silicon film 3.
次にこのフォトレジスト６をマスクとして所定のエツチ
ングを行うことにより、第１Ｂ図に示すように所定形状
の多結晶シリコン膜３ａ（素子形成領域）を形成し、次
いで再びフォトレジスト６をマスクとしてＳｉｎｇ膜２
にＮ２゛ （窒素）をイオン注入する（ＳｉＯ２膜２中
のＮを０で表す）。この結果、５ｉ０２膜２のうちの上
記Ｎが注入された部分はＳｉＮ膜７となる。Next, using the photoresist 6 as a mask, a predetermined etching process is performed to form a polycrystalline silicon film 3a (element formation region) having a predetermined shape as shown in FIG. 1B. membrane 2
N2 (nitrogen) is ion-implanted into the SiO2 film 2 (N in the SiO2 film 2 is represented by 0). As a result, the portion of the 5i02 film 2 into which the N is implanted becomes the SiN film 7.
次にフォトレジスト６を除去した後、熱酸化を行うこと
により多結晶シリコン膜３ａの表面にＳｉＯ□膜４を形
成する。この熱酸化の際には、多結晶シリコン膜３ａの
端部下方からのこの多結晶シリコン膜３ａへの酸素の侵
入が上記ＳｉＮ膜７により効果的に防止される結果、こ
の多結晶シリコン膜３ａの側面におけるＳｉＯ□膜４の
膜厚はこの多結晶シリコン膜３ａの上面におけるＳｉＯ
□膜４の膜厚とほぼ同一となっている。この後、ＴＰＴ
の公知の製造方法に従って、第１Ｄ図に示すようにゲー
ト酸化膜８、ゲート電極９、例えばｎ゛層から成るソー
ス領域１０及びドレイン領域１１等を形成して、目的と
するＴＰＴを完成させる。Next, after removing the photoresist 6, thermal oxidation is performed to form a SiO□ film 4 on the surface of the polycrystalline silicon film 3a. During this thermal oxidation, the SiN film 7 effectively prevents oxygen from entering the polycrystalline silicon film 3a from below the edge of the polycrystalline silicon film 3a. The thickness of the SiO□ film 4 on the side surface of the SiO
□The film thickness is almost the same as that of film 4. After this, TPT
As shown in FIG. 1D, a gate oxide film 8, a gate electrode 9, a source region 10 and a drain region 11 made of, for example, an n layer are formed according to a known manufacturing method to complete the desired TPT.
このように、上述の第１実施例によれば、多結晶シリコ
ン膜３ａの周囲のＳｉｎｇ膜２にＮＺ ”をイオン注入
することによりＳｉＮ膜７を形成しているので、ゲート
酸化の際にこの多結晶シリコン膜３ａの側面に形成され
るＳｉＯ□膜４の膜厚を従来に比べて極めて小さくする
ことができる。このため、酸化によりチャネル幅（紙面
と垂直な方向の多結晶シリコン膜３ａの幅）等が狭くな
るのを防止することができるのみならず、この多結晶シ
リコン膜３ａの面積を小さくすることが可能であるので
、ＴＰＴを高密度に集積化することが可能である。As described above, according to the first embodiment, the SiN film 7 is formed by ion-implanting NZ'' into the Sing film 2 around the polycrystalline silicon film 3a. The thickness of the SiO□ film 4 formed on the side surface of the polycrystalline silicon film 3a can be made extremely small compared to the conventional method.For this reason, the channel width (the thickness of the polycrystalline silicon film 3a in the direction perpendicular to the plane of the paper) can be reduced by oxidation. Not only can the width (width) etc. be prevented from becoming narrow, but also the area of this polycrystalline silicon film 3a can be reduced, so it is possible to integrate TPTs at a high density.
次に本発明の第２実施例を第２Ａ図及び第２Ｂ図に基づ
いて説明する。Next, a second embodiment of the present invention will be described based on FIGS. 2A and 2B.
まず第１Ａ図に示すと同様な工程を経た後、第１実施例
と同様にフォトレジスト６をマスクとして多結晶シリコ
ン膜３をエツチングし、この多結晶シリコン膜３のうち
の上記フォトレジスト６で覆われていない部分が第２Ａ
図に示すように薄くなった段階でエツチングを停止する
。なお以下においては、この多結晶シリコン膜３のうち
の膜厚の大きい部分（素子形成領域）を３ａで将来し、
膜厚の小さい部分を３ｂで将来する。次にフォトレジス
ト６をマスクとして、比較的高いエネルギーでＮ２°を
イオン注入することにより、多結晶シリコン膜３ｂの下
方のＳｉＯ□膜２にＮをドープしてこのＳｉＯ□膜２の
一部をＳｉＮ膜７に変える。First, after going through the same steps as shown in FIG. 1A, the polycrystalline silicon film 3 is etched using the photoresist 6 as a mask in the same way as in the first embodiment, and the photoresist 6 of the polycrystalline silicon film 3 is etched. The uncovered part is 2nd A
Etching is stopped when the thickness becomes thin as shown in the figure. In the following, a thicker part of the polycrystalline silicon film 3 (element formation region) will be referred to as 3a.
The parts with small film thickness will be treated with 3b. Next, using the photoresist 6 as a mask, N2° is ion-implanted at relatively high energy to dope N into the SiO□ film 2 below the polycrystalline silicon film 3b, and partially remove the SiO□ film 2. Change to SiN film 7.
次にフォトレジスト６を除去した後、熱酸化を行う。こ
の熱酸化により、第２Ｂ図に示すように、素子形成領域
となる多結晶シリコン膜３ａの表面に所定膜厚のＳｉＯ
□膜４が形成されると共に、薄い多結晶シリコン膜３ｂ
はＳｉｎｇ膜４に連なるＳｉＯ□膜１２に変わる。この
後、第１実施例で述べたと同様に工程を進めて、目的と
するＴＰＴを完成させる。Next, after removing the photoresist 6, thermal oxidation is performed. As a result of this thermal oxidation, as shown in FIG. 2B, a predetermined thickness of SiO
□While the film 4 is formed, the thin polycrystalline silicon film 3b
changes into a SiO□ film 12 connected to the Sing film 4. Thereafter, the steps are carried out in the same manner as described in the first embodiment to complete the desired TPT.
この第２実施例によれば、薄い多結晶シリコン膜３ｂの
下方のＳｉＯ□膜２の上部をＮ２゛のイオン注入により
ＳｉＮ膜７に変えているので、第１実施例と同様にゲー
ト酸化により多結晶シリコン膜３ａの表面に形成される
ＳｉＯ□膜４のその側面における。厚さをその上面にお
ける厚さと同程度とすることができる。従って、第１実
施例と同様に、酸化による多結晶シリコン膜３ａの幅の
減少量を従来。According to the second embodiment, since the upper part of the SiO□ film 2 below the thin polycrystalline silicon film 3b is changed to the SiN film 7 by N2'' ion implantation, gate oxidation is performed as in the first embodiment. On the side surface of the SiO□ film 4 formed on the surface of the polycrystalline silicon film 3a. The thickness can be comparable to the thickness at its top surface. Therefore, similarly to the first embodiment, the amount of decrease in the width of the polycrystalline silicon film 3a due to oxidation is reduced from the conventional amount.
に比べて極めて小さくすることができる。またこのため
、第１実施例と同様に多結晶シリコン膜３ａの面積を小
さくすることが可能であるで、ＴＦＴを高密度に集積化
することが可能である。It can be made extremely small compared to . Further, as in the first embodiment, it is possible to reduce the area of the polycrystalline silicon film 3a, and it is possible to integrate TFTs at a high density.
以上本発明を実施例につき説明したが、本発明は上述の
第１及び第２実施例に限定されるものではなく、本発明
の技術的思想に基づく種々の変形が可能である。例えば
、上述の第２実施例においでは、第２Ａｌ１ｇに示す工
程において比較的高いエネルギーでＮ２＋をイオン注入
することにより多結晶シリコン膜３ｂの下方のＳｊＯ□
膜２の上部をＳｉＮ膜７に変えたが、低エネルギーでＮ
２１をイオン注入することにより、第３図に示すように
多結晶シリコン膜３ｂをＳｉＮ膜７に変えることも可能
である。また上述の２つの実施例においては、半導体膜
として多結晶シリコン膜３を用いたが、非晶質シリコン
膜等の他の種類の半導体膜を用いでもよい。Although the present invention has been described above with reference to embodiments, the present invention is not limited to the above-described first and second embodiments, and various modifications can be made based on the technical idea of the present invention. For example, in the second embodiment described above, by ion-implanting N2+ with relatively high energy in the step shown in the second Al1g, the SjO□ below the polycrystalline silicon film 3b is
The upper part of film 2 was changed to SiN film 7, but N
By ion-implanting 21, it is also possible to change the polycrystalline silicon film 3b to a SiN film 7 as shown in FIG. Further, in the above two embodiments, the polycrystalline silicon film 3 was used as the semiconductor film, but other types of semiconductor films such as an amorphous silicon film may be used.
なお上述の２つの実施例に代えて、第４図に示すように
、ＳｉＯ□膜２上にあらかじめ所定形状の
゛ＳｉＮ膜７を形成し、次いで多結晶シリコン膜１４
を形成し、この後酸化を行うようにしても上述の２つの
実施例と同様な効果が得られる。Note that instead of the above two embodiments, as shown in FIG.
゛SiN film 7 is formed, then polycrystalline silicon film 14 is formed.
The same effects as in the two embodiments described above can be obtained by forming and then performing oxidation.
発明の効果
本発明に係る半導体装置の製造方法によれば、半導体膜
を選択的に除去して所定形状の素子形成領域を゛形成し
１次いでこの所定形状の素子形成領域の周囲に耐酸化処
理を施し、この後酸化を行うようにしているので、酸素
が素子形成領域の端部の下方からこの素子形成領域に侵
入するのを効果的に防止することができ、このため素子
形成領域の側面に形成される酸化膜の厚さを従来に比べ
て極めて小さくすることができる。従って、この分だけ
素子形成領域の面積を従来に比べて小さくすることが可
能であるので、基板上に素子を高密度に集積化すること
が可能である。Effects of the Invention According to the method for manufacturing a semiconductor device according to the present invention, a semiconductor film is selectively removed to form an element formation region of a predetermined shape, and then an oxidation-resistant treatment is performed around the element formation region of a predetermined shape. Since oxidation is performed after this, it is possible to effectively prevent oxygen from entering the element forming area from below the edge of the element forming area. The thickness of the oxide film formed can be made extremely smaller than in the past. Therefore, it is possible to reduce the area of the element formation region by this amount compared to the conventional method, and therefore it is possible to integrate elements on the substrate at a high density.
第１Ａ図〜第１Ｄ図は本発明の第１実施例を工程順に示
す断面図、第２Ａ図及び第２Ｂ図は本発明の第２実施例
を工程順に示す断面図、第３図は本発明の変形例を示す
第２Ａ図と同様な断面図、第４図は本発明と同様な目的
を達成するための実施例とは異なる方法を説明するため
の断面図、第５Ａ図及び第５Ｂ図は従来の多結晶シリコ
ン薄膜トランジスタの製造方法の一例を工程順に示す断
面図である。
なお図面に用いた符号において、
１−・−・・−・・・−・・−石英基板３−−−−−・
−一一−−−−−−−−−・多結晶シリコン膜（半導体
膜）４・・−・・・−・・−・−・−・ＳｉＯ□膜７・
−・・・・−−一−−−−−・・−５ｉＮ膜８・−・・
・・−・−・・・−・−・ゲート酸化膜９−・・・・・
−・−・−・−・−ゲート電極１０・−・・−・・−・
−・−・−・−ソース領域１１・−・・−・・・・−・
・・−・・・ドレイン領域である。1A to 1D are sectional views showing the first embodiment of the present invention in the order of steps, FIGS. 2A and 2B are sectional views showing the second embodiment of the invention in the order of steps, and FIG. 3 is the sectional view of the first embodiment of the present invention. FIG. 4 is a sectional view illustrating a method different from the embodiment for achieving the same object as the present invention; FIGS. 5A and 5B; FIG. 1A and 1B are cross-sectional views showing an example of a conventional method for manufacturing a polycrystalline silicon thin film transistor in the order of steps. In addition, in the symbols used in the drawings, 1-・-・・・・・・・−Quartz substrate 3−−−−−・
−11−−−−−−−−・Polycrystalline silicon film (semiconductor film) 4・・−・−・・−・−・−・SiO□ film 7・
−・・−−1−−−−−・・−5iN film 8・−・・
・・−・−・・・−・−・Gate oxide film 9−・・・・
−・−・−・−・−Gate electrode 10・−・・−・・−・
−・−・−・−Source area 11・−・・−・・・・−・
. . . Drain region.
Claims (1)
れた半導体膜を酸化することによりこの半導体膜を薄膜
化するようにした半導体装置の製造方法において、上記
半導体膜を選択的に除去して所定形状の素子形成領域を
形成し、次いでこの所定形状の素子形成領域の周囲に耐
酸化処理を施し、この後上記酸化を行うようにしたこと
を特徴とする半導体装置の製造方法。In a method for manufacturing a semiconductor device, the semiconductor film formed on a substrate at least the surface of which is made of an insulator is thinned by oxidizing the semiconductor film, and the semiconductor film is selectively removed to form a predetermined shape. 1. A method of manufacturing a semiconductor device, comprising: forming an element formation region, then applying anti-oxidation treatment to the periphery of the element formation region having a predetermined shape, and then performing the oxidation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21236884A JPS6190466A (en) | 1984-10-09 | 1984-10-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21236884A JPS6190466A (en) | 1984-10-09 | 1984-10-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6190466A true JPS6190466A (en) | 1986-05-08 |
Family
ID=16621399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21236884A Pending JPS6190466A (en) | 1984-10-09 | 1984-10-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6190466A (en) |
-
1984
- 1984-10-09 JP JP21236884A patent/JPS6190466A/en active Pending
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