JPH022634A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having an insulating film which is deposited on an electrode, that is, a gate and is formed so that an upper part of its film is thicker than that of conventional ones to avoid defective breakdown strength by causing an upper edge part of the electrode to be formed into a smooth projection shape. CONSTITUTION:In the case of a semiconductor device having a three-layer structure; electrode 13 - gate insulating film 12 semiconductor 11, an upper part of the electrode 13 is formed a smooth projection shape. For example, a gate oxide film 12 is formed on the semiconductor substrate 11 and doping is performed by forming a gate polysilicon film 13 on the above film 12. An SiO2 film 14 of a first layer, an Si3N4 film 15, and an SiO2 film 16 of a second layer are allowed to grow and they are etched so that the three-layer structure 17 corresponding to dimensions of the electrode may remain. Once its structure is thermally oxidized, outside gate polysilicon of the structure 17 forms an SiO2 film 18. Then, the SiO2 film 18, polysilicon 13, and the gate oxide film 12 are etched by the use of the three-layer structure 17 as a mask. After that, the Si3N4 film 15 is removed to grow an SiO2 film 19 and then, the SiO2 film 19 is etched by using a resist 20 as a mask.

Description

[Detailed description of the invention] Semiconductor devices, particularly electrode-gate insulating film-semiconductor (MOS)
Regarding the electrode structure of a semiconductor device having a structure of An object of the present invention is to provide a semiconductor device having a structure of electrode-gate insulating film-semiconductor (industrial application field). Insulating film semiconductor (
This invention relates to an electrode structure of a semiconductor device having a MOS (MOS) structure.

[Prior Art] In recent years, self-alignment technology has been increasingly used as semiconductor devices become smaller. The conventional technology will be explained with reference to FIG. 3. First, as shown in FIG.
95 on semiconductor (silicon) substrate 1 (resistance 10Ω・cm)
Perform gate oxidation for 0°C1HCj2.45 minutes and
A gate oxide film 2 with a thickness of 3000 nm is formed, a gate polysilicon 3 for forming an electrode is grown to a thickness of 3000 nm, and phosphorus (P) is grown at an accelerating voltage of 50 KeV and 8×1015.
Ions are implanted at a dose of cm-2 to make the sheet resistance of polysilicon about 30Ω/hole. Next, a 5iOz film 4 is grown to a thickness of about 2000 nm by chemical vapor deposition, and the gate polysilicon is patterned to form electrodes.

Next, arsenic (8s) was applied to the substrate 1 as shown in FIG.
') Accelerating voltage 60KeV, dose ff15X101
The source/drain 5 is formed by ion implantation at 5 cm-2, and then a 5-in2 film 6 is grown to a thickness of approximately 3000 nm on the entire surface by CVO method, an electrode contact window is opened in it, and a metal wiring 7 is formed. Form.

[Problem to be solved by the invention]

The electrode contact window described above is formed by forming a resist film 8 on the 5iO7 film 6, patterning it, etching the SiO□ film 6 using the obtained resist pattern as a mask, and opening the electrode contact window. Next, wiring metal is deposited and patterned to form metal wiring 7.

In order to form the electrode contact window by self-alignment, referring to FIG. 4, after forming the resist film 8 on the SiO□ film 6, the electrode contact window is formed by anisotropic dry etching until the electrode window is opened. etching.

FIG. 5 shows a state in which a metal wiring (or polysilicon wiring, etc.) 7 is formed after opening an electrode contact window in such a process. In this structure, the thickness of the insulating film (SiO□ film 6) becomes thinner in the area surrounded by circle A in the figure, causing a problem of poor breakdown voltage.

Therefore, in the MO5 structure, the present invention aims to make the insulating film thicker in the upper part of the insulating film deposited on the electrode (M), that is, the gate, than in the conventional example, in order to prevent breakdown voltage failure in the upper part of the insulating film deposited on the electrode (M), that is, the gate. An object of the present invention is to provide a formed semiconductor device.

[Means for Solving the Problem] The above problem is achieved by providing a device having an electrode-gate insulating film-semiconductor structure, characterized in that the upper edge of the electrode has a convex and smooth shape. The problem is solved by a semiconductor device that

[Effect]

That is, the present invention provides an electrode (
The gate polysilicon that will become the electrode (gate) is thermally oxidized to SiO□ except for the gate formation area, and this SiO□ is removed to form the gate. The upper edge becomes a smooth shape, and then the SiO□ deposited on the entire surface is anisotropically etched to leave Sin as sidewalls on both sides of the electrode (gate), so that the entire surface of the electrode (gate) is is made of N-uniform SiO□, which solves the conventional problem of poor breakdown voltage.

(Example] Hereinafter, the present invention will be specifically explained with reference to illustrated embodiments.

FIG. 1 is a sectional view showing the steps of the method of the present invention.

Refer to FIG. 1(a): Gate oxidation is performed on a semiconductor (silicon) substrate 11 in the same manner as in the conventional example to form a gate oxide film 12 with a thickness of 250 nm, and an electrode (gate) is formed on it. A gate polysilicon film 13 is formed by growing polysilicon to a thickness of 3000 nm, and doping the gate polysilicon film 13 so that the sheet resistance is about 30Ω/gate as in the conventional example. Next, a first layer of SiO□ film 14 is grown to a thickness of about 3,000 layers using the CVD method, and on top of that a silicon nitride (Si3N4) film 15 is grown to a thickness of about 2,000 layers using the CVD method. The second layer 5i(h film 16 is grown to a thickness of approximately 3000 nm. Next, the SiO□ film 16.5iJn film 15, the SiO□I!
) SiO corresponding to the dimensions of the electrode (gate) using gas
□ Etching is performed so that the three-layer structure 17 of film 16/SiJ and film 15/5in2 film 14 remains.

See FIG. 1(b): Next, the gate polysilicon is thermally oxidized to a thickness of approximately 3000 nm. The conditions at that time are, for example, 950'C and about 380 minutes in a wet atmosphere. In this thermal oxidation, since the 5iJ4 film 15 has oxidation resistance, the outer gate polysilicon of the three-layer structure 17 shown in FIG. The polysilicon below is not oxidized and becomes the electrode (gate).

Refer to FIG. 1(C): Next, using (SiCffia +CJ22) gas, for example, and using the three-layer structure 17 as a mask, the 5i02 film 18, the gate polysilicon 13 under it, and the gate oxide film 12 are removed.
etching. At this time, S on the 5iJn film 15
The iO□ film 16 is also etched.

Refer to FIG. 1(d). Remove the Si:I N film 15 using diphosphoric acid, and remove the C
A SiO□ film 19 was grown to a thickness of approximately 3000 nm using the VO method, and the resist 20 coated on the entire surface was patterned to form electrode contact windows, and the SiO film 19 was grown using anisotropic etching.
When the O□ film 19 is etched, a portion of the grown SiO□ remains on both sides of the polysilicon 13 that will serve as the electrode (gate), forming sidewalls.

Thereafter, wiring diagram metal is deposited and patterned to form source/drain electrodes (metal wiring) in the same manner as in the conventional example.

In the step (thermal oxidation of the gate polysilicon) described above with reference to FIG. The remaining gate polysilicon 1, which will become the electrode (gate) of the three-layer structure 17, is formed when the SiO□ film 18 is etched in the step described with reference to FIG. 1(C).
3 has a smooth convex edge.

And, on both sides of this gate polysilicon, SiO□
remains as a sidewall, so the entire surface of the gate polysilicon has a uniform thickness of Si.
In the conventional example, as shown in FIG. 2(a), the upper edge of the electrode (gate) is covered with SiO□.
□While the film became thinner, in the example of the present invention, the film became thinner, as shown in Fig. 2 [
]) As shown in Figure 1), it is smooth on the entire surface of the gate polysilicon that will become the electrode (gate)! Since the 5i02 film is uniformly present, the problem of poor gate breakdown voltage in the conventional example is solved.

[Effects of the Invention] As described above, according to the present invention, in the MO5 structure, the surface of the metal, that is, the gate polysilicon, is smoothly formed into a dome shape at its upper edge, and the insulating film ( Since the SiO□ film) is formed with a uniform thickness on the gate polysilicon, the conventional self-alignment technology can be stably applied.
This can be applied to all other semiconductor devices having the O3 structure.

15 is a Si3N4 film, 16 is a second layer SiO□ film, 17 is a three-layer structure, 18 is a SiO□ film, 19 is a SiO□ film, 20 is resist shows.

[Brief explanation of the drawing]

Figures 1 (a) to (d) are cross-sectional views of the embodiment of the present invention, Figure 2 is a cross-sectional view comparing the conventional example and the embodiment of the present invention, and Figures 3 (a) and (b) are cross-sectional views of the conventional example. , FIG. 4 is a sectional view of a conventional example, and FIG. 5 is a sectional view showing problems in the conventional example. In the figure, 11 is a semiconductor substrate, 12 is a gate oxide film, 13 is a gate polysilicon, 14 is a first layer SiO□ film,

Claims (1)

[Scope of Claim] A semiconductor device having an electrode-gate insulating film-semiconductor structure, characterized in that the upper edge of the electrode has a convex and smooth shape.