JPS5817662A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5817662A
JPS5817662A JP11506581A JP11506581A JPS5817662A JP S5817662 A JPS5817662 A JP S5817662A JP 11506581 A JP11506581 A JP 11506581A JP 11506581 A JP11506581 A JP 11506581A JP S5817662 A JPS5817662 A JP S5817662A
Authority
JP
Grant status
Application
Patent type
Prior art keywords
films
poly
si
layer
oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11506581A
Inventor
Kazuhiro Komori
Jun Sugiura
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/1052Memory structures and multistep manufacturing processes therefor not provided for in groups H01L27/1055 - H01L27/112

Abstract

PURPOSE:To enable minute patterning requiring no over-etching, to prevent leakage and the degradation of dielectric resistance through an oxide film, to form the gate electrode of a minute pattern and to improve the degree of integration by uniformly growing the oxide film onto the surface of a poly Si layer functioning as a gate in an EPROM. CONSTITUTION:The gate oxide films 5 are each shaped through thermal oxidation in a P type silicon substrate 1, and the poly Si layer 6 of the first layer is grown on the whole surface. The poly Si layer 6 is etched by using masks 7. In this case, etching is controlled so that the poly layer 6 is left in approximately 500Angstrom thickness at a position where there is no mask, and comparatively thick poly Si layers 6a1, 6a2 and 6a3 and thin poly Si layers 6b in approximately 500Angstrom thickness are formed continuously. SiO2 Films 8 as layer insulating films are shaped to the surfaces of the thick sections 6a1-6a3 among said poly Si layers through heat treatment in a thermal oxidation atmosphere, and the thin sections 6b are oxidized completely and changed into SiO2 films 9 unified with said gate oxide films 5, and the films on field SiO2 films 2 are turned into SiO2 9 unified with the field SiO2 films. The approximately uniform SiO2 films 8 can be shaped to the surfaces of the poly Si layers 6a1-6a3 through the thermal oxidation process.
JP11506581A 1981-07-24 1981-07-24 Manufacture of semiconductor device Pending JPS5817662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11506581A JPS5817662A (en) 1981-07-24 1981-07-24 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11506581A JPS5817662A (en) 1981-07-24 1981-07-24 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5817662A true true JPS5817662A (en) 1983-02-01

Family

ID=14653301

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11506581A Pending JPS5817662A (en) 1981-07-24 1981-07-24 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5817662A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5188976A (en) * 1990-07-13 1993-02-23 Hitachi, Ltd. Manufacturing method of non-volatile semiconductor memory device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5188976A (en) * 1990-07-13 1993-02-23 Hitachi, Ltd. Manufacturing method of non-volatile semiconductor memory device

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