JP2002075907A - Semiconductor device and its manufacturing method - Google Patents
Semiconductor device and its manufacturing methodInfo
- Publication number
- JP2002075907A JP2002075907A JP2000260515A JP2000260515A JP2002075907A JP 2002075907 A JP2002075907 A JP 2002075907A JP 2000260515 A JP2000260515 A JP 2000260515A JP 2000260515 A JP2000260515 A JP 2000260515A JP 2002075907 A JP2002075907 A JP 2002075907A
- Authority
- JP
- Japan
- Prior art keywords
- film
- polysilicon film
- oxide film
- thermal oxide
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Electrodes Of Semiconductors (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、ＣＣＤ（Ｃｈａ
ｒｇｅ Ｃｏｕｐｌｅｄ Ｄｅｖｉｃｅ）などの半導体
装置およびその製造方法に関する。The present invention relates to a CCD (Cha).
The present invention relates to a semiconductor device such as a rge coupled device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】ＣＣＤの電荷転送部の電極構造は、ゲー
ト電極を形成するポリシリコン膜と層間絶縁膜である熱
酸化膜と転送電極を形成するポリシリコン膜の積層構造
をしている。図３は、ＣＣＤの電荷転送部の要部断面図
である。ｐ基板５１上にゲート酸化膜５２を形成し、こ
のゲート酸化膜５２上に第１ポリシリコン膜５３でゲー
ト電極を形成する。この第１ポリシリコン膜５３上に、
層間絶縁膜となるＳｉ（シリコン）熱酸化膜５４を形成
し、ゲート酸化膜５２上とＳｉ熱酸化膜５４上に第２ポ
リシリコン膜５５で転送電極を形成する。ＣＣＤの電極
は円Ｃで示すように第１ポリシリコン膜５３／Ｓｉ熱酸
化膜５４／第２ポリシリコン膜５５の積層構造となって
いる。尚、図中のＶ１、Ｖ３、Ｖ５はゲート電極に接続
する端子、Ｖ２、Ｖ４、Ｖ６は転送電極に接続する端子
である。2. Description of the Related Art The electrode structure of a charge transfer portion of a CCD has a laminated structure of a polysilicon film forming a gate electrode, a thermal oxide film serving as an interlayer insulating film, and a polysilicon film forming a transfer electrode. FIG. 3 is a sectional view of a main part of a charge transfer section of the CCD. A gate oxide film 52 is formed on a p-substrate 51, and a gate electrode is formed on the gate oxide film 52 using a first polysilicon film 53. On this first polysilicon film 53,
An Si (silicon) thermal oxide film serving as an interlayer insulating film is formed, and a transfer electrode is formed of a second polysilicon film 55 on the gate oxide film 52 and the Si thermal oxide film. The electrodes of the CCD have a laminated structure of a first polysilicon film 53 / a thermally oxidized Si film 54 / a second polysilicon film 55 as shown by a circle C. In the drawings, V1, V3, and V5 are terminals connected to the gate electrode, and V2, V4, and V6 are terminals connected to the transfer electrode.
【０００３】つぎに、動作について簡単に説明する。図
示しない左側で、光などの信号が電子量に変換され、Ｖ
１の下にその電子が送られてきたとする。Ｖ１、Ｖ３、
Ｖ５に正電圧を印加すると、この電子はＶ１の下に保持
される。つぎに、Ｖ１、Ｖ３、Ｖ５を０Ｖとして、Ｖ
２、Ｖ４、Ｖ６に正電圧を印加すると、Ｖ１の下の電子
はＶ２の下に移動する。Ｖ２、Ｖ４、Ｖ６を０Ｖとし
て、再びＶ１、Ｖ３、Ｖ５に正電圧を印加すると、Ｖ２
の下の電子はＶ３の下に移動する。このことを繰り返す
ことで、電子をＶ１からＶ２へ、Ｖ２からＶ３へと移動
させることができる。この電子の移動によって、信号を
転送することができる。Next, the operation will be briefly described. On the left side (not shown), a signal such as light is converted into an amount of electrons, and V
Suppose that the electron was sent under 1. V1, V3,
When a positive voltage is applied to V5, the electrons are held below V1. Next, V1, V3, and V5 are set to 0 V, and V
When a positive voltage is applied to 2, V4, and V6, electrons below V1 move below V2. When V2, V4, and V6 are set to 0 V and positive voltages are again applied to V1, V3, and V5, V2
The electrons below move below V3. By repeating this, electrons can be moved from V1 to V2 and from V2 to V3. A signal can be transferred by the movement of the electrons.
【０００４】図４は、従来のＣＣＤの電荷転送部の電極
構造の製造方法で、同図（ａ）から同図（ｅ）は工程順
に示した要部工程断面図である。ｐ基板５１（Ｓｉ基
板）上にゲート酸化膜５２を形成し、続いて減圧ＣＶＤ
（Ｃｈｅｍｉｃａｌ Ｖａｐｏｒ Ｄｅｐｏｓｉｔｉｏ
ｎ）法により、第１ポリシリコン膜５３を形成する（同
図（ａ））。FIGS. 4A to 4E show a conventional method for manufacturing an electrode structure of a charge transfer section of a CCD. FIGS. A gate oxide film 52 is formed on a p-substrate 51 (Si substrate), followed by low pressure CVD.
(Chemical Vapor Deposition
A first polysilicon film 53 is formed by the method n) (FIG. 3A).
【０００５】つぎに、図示しないレジストを被覆し、こ
のレジストをパターニングし、パターニングされたレジ
ストをマスクに第１ポリシリコン膜５３をエッチングし
て、第１ポリシリコン膜５３からなるゲート電極を形成
する（同図（ｂ））。つぎに、レジスト５３を除去し、
９００℃程度で熱酸化を行い、ｐ基板５１表面および第
１ポリシリコン膜５３表面にＳｉ熱酸化膜５４（ＳｉＯ
2 ）を形成する。このＳｉ熱酸化膜５４の厚みは、酸化
速度（酸化レート）の違いから、第１ポリシリコン膜５
３表面に形成されるＳｉ熱酸化膜５４の方が、ゲート酸
化膜５２表面に形成されるＳｉ熱酸化膜より２倍から４
倍程度厚くなる（同図（ｃ））。同図（ｃ）ではゲート
酸化膜５２上に形成されたＳｉ熱酸化膜はゲート酸化膜
５２の中に含めた。Next, a resist (not shown) is coated, the resist is patterned, and the first polysilicon film 53 is etched using the patterned resist as a mask to form a gate electrode made of the first polysilicon film 53. (FIG. 2B). Next, the resist 53 is removed,
Thermal oxidation is performed at about 900 ° C., and a Si thermal oxide film 54 (SiO 2 film) is formed on the surface of the p-substrate 51 and the surface of the first polysilicon film 53.
2 ) Form. The thickness of the Si thermal oxide film 54 depends on the oxidation rate (oxidation rate).
3 The thickness of the Si thermal oxide film 54 formed on the surface is two to four times larger than that of the Si thermal oxide film formed on the surface of the gate oxide film 52.
It is about twice as thick (FIG. 3 (c)). In FIG. 3C, the Si thermal oxide film formed on the gate oxide film 52 is included in the gate oxide film 52.
【０００６】つぎに、全面に、減圧ＣＶＤ法により、第
２ポリシリコン膜５５を形成し、つぎに、レジスト５６
を被覆し、このレジスト５６をパターニングし、パター
ニングされたレジスト５６をマスクに第２ポリシリコン
膜５５をエッチングし、第２ポリシリコン膜５５からな
る転送電極を形成する（同図（ｄ））。つぎに、レジス
ト５６を除去することで、第１ポリシリコン膜５３／Ｓ
ｉ熱酸化膜５４／第２ポリシリコン膜５５の積層構造が
ｐ基板５１上にゲート酸化膜５２を介して形成される
（同図（ｅ））。尚、図５（ａ）は図４（ｂ）の拡大
図、図５（ｂ）は図４（ｃ）の拡大図である。Next, a second polysilicon film 55 is formed on the entire surface by a low-pressure CVD method.
And the resist 56 is patterned, and the second polysilicon film 55 is etched using the patterned resist 56 as a mask to form a transfer electrode composed of the second polysilicon film 55 (FIG. 4D). Next, by removing the resist 56, the first polysilicon film 53 / S
A laminated structure of i thermal oxide film 54 / second polysilicon film 55 is formed on p substrate 51 via gate oxide film 52 (FIG. 4E). 5 (a) is an enlarged view of FIG. 4 (b), and FIG. 5 (b) is an enlarged view of FIG. 4 (c).
【０００７】[0007]
【発明が解決しようとする課題】しかし、前記の製造方
法では、図５（ａ）の円Ｆに示すように、第１ポリシリ
コン膜５３のエッジ部は直角となり鋭い。さらに、９０
０℃程度の熱酸化工程後では、図５（ｂ）の円Ｇに示す
ように、このエッジ部の形状はさらに鋭角５７となる。
これは、熱酸化工程では、応力開放が進まずエッジ部で
の酸化が遅くなるためである。また、このエッジ部が丸
まった状態でなく、鋭角５７の状態では、Ｓｉ熱酸化膜
５４の膜厚は、エッジ部で薄くなる。そのため、積層構
造に電圧が印加されると、このエッジ部のＳｉ熱酸化膜
５４に電界集中が起こり、また、この箇所のＳｉ熱酸化
膜５４が薄いこともあって、Ｓｉ熱酸化膜５４の信頼性
は低下し、半導体装置の信頼性も低下する。この発明の
目的は、前記の課題を解決して、エッジ部のＳｉ熱酸化
膜内で電界集中が起こりにくい半導体装置を提供するこ
とにある。However, in the above-described manufacturing method, the edge portion of the first polysilicon film 53 is a right angle and sharp as shown by a circle F in FIG. In addition, 90
After the thermal oxidation process at about 0 ° C., the shape of this edge portion becomes an acute angle 57 as shown by a circle G in FIG.
This is because in the thermal oxidation step, stress release does not proceed, and oxidation at the edge portion is delayed. Further, when the edge is not rounded but is at an acute angle 57, the thickness of the Si thermal oxide film 54 becomes thinner at the edge. Therefore, when a voltage is applied to the laminated structure, electric field concentration occurs in the Si thermal oxide film 54 at the edge portion, and since the Si thermal oxide film 54 at this portion is thin, the Si thermal oxide film 54 The reliability is reduced, and the reliability of the semiconductor device is also reduced. An object of the present invention is to solve the above-mentioned problem and to provide a semiconductor device in which electric field concentration hardly occurs in a Si thermal oxide film at an edge portion.
【０００８】[0008]
【課題を解決するための手段】前記の目的を達成するた
めに、絶縁膜上に選択的にポリシリコン膜を形成し、該
ポリシリコン膜の表面にシリコン熱酸化膜を形成した半
導体装置において、前記ポリシリコン膜の上部表面と側
面とが交わる稜線部の断面形状を丸まった状態にする。In order to achieve the above object, a semiconductor device in which a polysilicon film is selectively formed on an insulating film and a silicon thermal oxide film is formed on the surface of the polysilicon film, The cross-sectional shape of the ridge portion where the upper surface and the side surface of the polysilicon film intersect is made to be in a rounded state.
【０００９】また、絶縁膜上に選択的にポリシリコン膜
を形成し、該ポリシリコン膜の表面にシリコン熱酸化膜
を形成した半導体装置の製造方法において、半導体基板
上に絶縁膜を形成する工程と、該絶縁膜上にポリシリコ
ン膜を全面に形成する工程と、前記半導体基板を酸素雰
囲気中で熱処理を行い、続いて、窒素雰囲気中において
熱処理を行い第１シリコン熱酸化膜を前記ポリシリコン
膜上に形成する工程と、全面にレジストを被覆する工程
と、該レジストを選択的に除去する工程と、該レジスト
をマスクに前記第１シリコン熱酸化膜をエッチングし、
前記レジスト外周端部近傍の前記第１シリコン熱酸化膜
の端部の形状をテーパー状に加工する工程と、前記の第
１シリコン熱酸化膜をマスクに、前記ポリシリコン膜を
異方性エッチングし、該ポリシリコン膜の表面の外周端
部をテーパー状に加工する工程とを含む製造方法とす
る。Further, in a method of manufacturing a semiconductor device in which a polysilicon film is selectively formed on an insulating film and a silicon thermal oxide film is formed on the surface of the polysilicon film, a step of forming the insulating film on the semiconductor substrate Forming a polysilicon film on the entire surface of the insulating film; and performing a heat treatment on the semiconductor substrate in an oxygen atmosphere, and subsequently performing a heat treatment in a nitrogen atmosphere to form the first silicon thermal oxide film on the polysilicon film. Forming a film on the film, covering the entire surface with a resist, selectively removing the resist, etching the first silicon thermal oxide film using the resist as a mask,
Processing the edge of the first silicon thermal oxide film in the vicinity of the outer peripheral edge of the resist into a tapered shape; and performing anisotropic etching of the polysilicon film using the first silicon thermal oxide film as a mask. And processing the outer peripheral edge of the surface of the polysilicon film into a tapered shape.
【００１０】また、前記のテーパー状に加工する工程に
続いて、熱酸化処理を行い、前記ポリシリコン膜のテー
パー部を丸め、該ポリシリコン膜上に第２シリコン熱酸
化膜を形成する工程を含む製造方法とする。また、前記
のテーパー状に加工する工程に続いて、前記第１シリコ
ン酸化膜を除去する工程と、熱酸化処理を行い、前記ポ
リシリコン膜のテーパー部を丸め、該ポリシリコン膜上
に第２シリコン熱酸化膜を形成する工程とを含む製造方
法とする。In addition, following the step of processing into a tapered shape, a step of performing a thermal oxidation process to round a tapered portion of the polysilicon film and forming a second silicon thermal oxide film on the polysilicon film is included. Manufacturing method. Further, following the step of processing into a tapered shape, a step of removing the first silicon oxide film and a thermal oxidation treatment are performed to round a tapered portion of the polysilicon film, and a second layer is formed on the polysilicon film. And a step of forming a silicon thermal oxide film.
【００１１】[0011]
【発明の実施の形態】図１は、この発明の一実施例の半
導体装置の製造方法で、同図（ａ）から同図（ｃ）は工
程順に示した要部工程断面図である。ここでは、積層構
造の製造方法について説明する。ｐ基板１上に、ゲート
酸化膜２を形成し、続いて、第１ポリシリコン膜３を形
成し、その後、８００℃から１１００℃程度の温度で、
１分から２０分程度、数％の酸素雰囲気中で熱処理を行
い、その後、８００℃から１１００℃程度の温度で、１
分から２０分程度、窒素雰囲気中において熱処理を行
う。前者の短時間で数％の酸素雰囲気中の熱酸化処理に
より、第１ポリシリコン膜３上に、数ｎｍから数十ｎｍ
程度の第１Ｓｉ熱酸化膜１１が形成される（同図
（ａ））。1A to 1C show a method of manufacturing a semiconductor device according to an embodiment of the present invention. FIGS. 1A to 1C are sectional views showing main steps in the order of steps. Here, a method for manufacturing a laminated structure will be described. A gate oxide film 2 is formed on a p-substrate 1, a first polysilicon film 3 is formed, and then a temperature of about 800 ° C. to 1100 ° C.
Heat treatment is performed for about 1 minute to about 20 minutes in an oxygen atmosphere of several percent, and then at a temperature of about 800 ° C. to about 1100 ° C.
The heat treatment is performed in a nitrogen atmosphere for about 20 to 20 minutes. By the former thermal oxidation treatment in a short period of time in an oxygen atmosphere of several%, the first polysilicon film 3 has a thickness of several nm to several tens nm.
The first Si thermal oxide film 11 is formed to the extent of FIG.
【００１２】つぎに、レジスト１３を被覆し、パターニ
ングした後、このレジスト１３をマスクにドライエッチ
ャーで、第１Ｓｉ熱酸化膜１１をエッチングする。この
エッチングで、第１Ｓｉ熱酸化膜１１の形状はテーパー
状１２になる（同図（ｂ））。つぎに、第１ポリシリコ
ン膜３を、前記のレジスト１３および第１Ｓｉ熱酸化膜
１１をマスクに、ＥＣＲ（Ｅｌｅｃｔｒｏｎ Ｃｙｃｌ
ｏｔｒｏｎ Ｒｅｓｏｎａｎｃｅ）エッチャーにて、異
方性エッチングを行う。この異方性エッチングでは、Ｓ
ｉとＳｉＯ2 のエッチング選択比を所定の値に設定する
と、テーパー状となった第１Ｓｉ熱酸化膜１１が、第１
ポリシリコン膜３をエッチングするときのマスクとして
機能し、ゲート電極となる第１ポリシリコン膜３のエッ
ジ部をテーパー状１４に加工できる（同図（ｃ））。同
図（ｃ）の円Ａの拡大図が図２（ａ）である。Next, after the resist 13 is coated and patterned, the first Si thermal oxide film 11 is etched by a dry etcher using the resist 13 as a mask. By this etching, the shape of the first Si thermal oxide film 11 becomes a tapered shape 12 (FIG. 2B). Next, an ECR (Electron Cycle) is formed on the first polysilicon film 3 by using the resist 13 and the first Si thermal oxide film 11 as a mask.
An anisotropic etching is performed using an etcher. In this anisotropic etching, S
When the etching selectivity of i and SiO 2 is set to a predetermined value, the tapered first Si thermal oxide film 11
The edge portion of the first polysilicon film 3 serving as a gate electrode functions as a mask when the polysilicon film 3 is etched, and can be processed into a tapered shape 14 (FIG. 3C). FIG. 2A is an enlarged view of the circle A in FIG.
【００１３】つぎに、熱酸化工程を行うことで、第１ポ
リシリコン膜３のエッジ部は丸まった形状となり、この
丸まった第１ポリシリコン膜３上に第２Ｓｉ熱酸化膜４
が形成される（同図（ｄ））。丸まった第１ポリシリコ
ン膜３上に第２Ｓｉ熱酸化膜４が形成されるので、第１
ポリシリコン膜３のエッジ部の第２Ｓｉ熱酸化膜４が薄
くなることがない。同図（ｄ）の円Ｂの拡大図が図２
（ｂ）である。図２（ｂ）に丸まった状態１５に示され
る。尚、第２Ｓｉ熱酸化膜４を形成する前に第１Ｓｉ熱
酸化膜１１を除去しても、除去しなくてもよい。Next, by performing a thermal oxidation step, the edge portion of the first polysilicon film 3 has a rounded shape, and the second Si thermal oxide film 4 is formed on the rounded first polysilicon film 3.
Is formed (FIG. 2D). Since the second Si thermal oxide film 4 is formed on the rounded first polysilicon film 3, the first
The second Si thermal oxide film 4 at the edge of the polysilicon film 3 does not become thin. FIG. 2D is an enlarged view of the circle B in FIG.
(B). FIG. 2B shows a state 15 that is rounded. Note that the first Si thermal oxide film 11 may or may not be removed before the formation of the second Si thermal oxide film 4.
【００１４】つぎに、転送電極となる第２ポリシリコン
膜５を第１ポリシリコン膜３上に前記の第２Ｓｉ熱酸化
膜４を介して形成すると、積層構造が形成される（同図
（ｅ））。この積層構造は、第１ポリシリコン膜３のエ
ッジ部が丸まっており、この箇所の第２Ｓｉ熱酸化膜４
の厚みも薄くならないので、積層構造に電圧を印加した
とき、第２Ｓｉ熱酸化膜中で電界集中が起こらず、半導
体装置の信頼性が向上する。尚、図１（ｅ）が、図３に
相当する半導体装置となる。Next, when a second polysilicon film 5 serving as a transfer electrode is formed on the first polysilicon film 3 with the second Si thermal oxide film 4 interposed therebetween, a laminated structure is formed (see FIG. )). In this laminated structure, the edge portion of the first polysilicon film 3 is rounded, and the second Si thermal oxide film 4 at this portion is rounded.
Does not become thin, electric field concentration does not occur in the second Si thermal oxide film when a voltage is applied to the laminated structure, and the reliability of the semiconductor device is improved. FIG. 1E shows a semiconductor device corresponding to FIG.
【００１５】[0015]
【発明の効果】この発明において、第１ポリシリコン膜
のエッジ部を丸くし、且つ、エッジ部でのＳｉ熱酸化膜
の薄膜化を防止することで、エッジ部でのＳｉ熱酸化膜
内の電界集中が起こらず、半導体装置の信頼性を向上さ
せることができる。According to the present invention, the edge portion of the first polysilicon film is rounded and the thickness of the Si thermal oxide film at the edge portion is prevented from being reduced. Electric field concentration does not occur, and the reliability of the semiconductor device can be improved.
【図１】この発明の一実施例の半導体装置の製造方法
で、（ａ）から（ｅ）は工程順に示した要部工程断面図FIG. 1A to FIG. 1E are cross-sectional views of a main part of a method of manufacturing a semiconductor device according to an embodiment of the present invention, in which steps are shown in the order of steps.
【図２】図１（ｃ）、（ｄ）の拡大図FIG. 2 is an enlarged view of FIGS. 1 (c) and 1 (d).
【図３】ＣＣＤの電荷転送部の要部断面図FIG. 3 is a sectional view of a main part of a charge transfer unit of the CCD.
【図４】従来のＣＣＤの電荷転送部の電極構造の製造方
法で、（ａ）から（ｅ）は工程順に示した要部工程断面
図4A to 4E are cross-sectional views of a main part process in a conventional method for manufacturing an electrode structure of a charge transfer portion of a CCD, which are shown in the order of processes.
【図５】図４（ｂ）、（ｃ）の拡大図FIG. 5 is an enlarged view of FIGS. 4 (b) and (c).
１ ｐ基板 ２ ゲート酸化膜 ３ 第１ポリシリコン膜 ４ 第２Ｓｉ熱酸化膜 ５ 第２ポリシリコン膜 １１ 第１Ｓｉ熱酸化膜 １２、１４ テーパー状 １３ レジスト １５ 丸まった状態 ５１ ｐ基板 ５２ ゲート酸化膜 ５３ 第１ポリシリコン膜 ５４ Ｓｉ熱酸化膜 ５５ 第２ポリシリコン膜 ５６ レジスト ５７ 鋭角 REFERENCE SIGNS LIST 1 p substrate 2 gate oxide film 3 first polysilicon film 4 second Si thermal oxide film 5 second polysilicon film 11 first Si thermal oxide film 12, 14 tapered 13 resist 15 curled state 51 p substrate 52 gate oxide film 53 First polysilicon film 54 Si thermal oxide film 55 second polysilicon film 56 resist 57 acute angle
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 ＦＩ テーマコート゛(参考） Ｈ０１Ｌ 21/339 Ｆターム(参考） 4M104 BB01 CC05 DD66 DD71 DD78 EE05 EE09 FF06 GG09 GG17 HH20 4M118 AA10 AB10 BA22 BA25 DA18 EA17 EA20 5F004 AA16 DB02 DB03 EA29 EB02──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 7 Identification symbol FI Theme coat ゛ (Reference) H01L 21/339 F-term (Reference) 4M104 BB01 CC05 DD66 DD71 DD78 EE05 EE09 FF06 GG09 GG17 HH20 4M118 AA10 AB10 BA22 BA25 DA18 EA17 EA20 5F004 AA16 DB02 DB03 EA29 EB02
Claims (4)
し、該ポリシリコン膜の表面にシリコン熱酸化膜を形成
した半導体装置において、 前記ポリシリコン膜の上部表面と側面とが交わる稜線部
の断面形状を丸まった状態にすることを特徴とする半導
体装置。1. A semiconductor device in which a polysilicon film is selectively formed on an insulating film and a silicon thermal oxide film is formed on the surface of the polysilicon film, wherein a ridge line where an upper surface and a side surface of the polysilicon film intersects. A semiconductor device wherein a cross-sectional shape of a portion is rounded.
し、該ポリシリコン膜の表面にシリコン熱酸化膜を形成
した半導体装置の製造方法において、 半導体基板上に絶縁膜を形成する工程と、該絶縁膜上に
ポリシリコン膜を全面に形成する工程と、前記半導体基
板を酸素雰囲気中で熱処理を行い、続いて、窒素雰囲気
中において熱処理を行い第１シリコン熱酸化膜を前記ポ
リシリコン膜上に形成する工程と、全面にレジストを被
覆する工程と、該レジストを選択的に除去する工程と、
該レジストをマスクに前記第１シリコン熱酸化膜をエッ
チングし、前記レジスト外周端部近傍の前記第１シリコ
ン熱酸化膜の端部の形状をテーパー状に加工する工程
と、前記の第１シリコン熱酸化膜をマスクに、前記ポリ
シリコン膜を異方性エッチングし、該ポリシリコン膜の
表面の外周端部をテーパー状に加工する工程とを含むこ
とを特徴とする半導体装置の製造方法。2. A method for manufacturing a semiconductor device, wherein a polysilicon film is selectively formed on an insulating film and a silicon thermal oxide film is formed on a surface of the polysilicon film, wherein a step of forming the insulating film on the semiconductor substrate is performed. Forming a polysilicon film on the entire surface of the insulating film; and performing a heat treatment on the semiconductor substrate in an oxygen atmosphere, and subsequently performing a heat treatment in a nitrogen atmosphere to form the first silicon thermal oxide film on the polysilicon film. A step of forming on a film, a step of coating the entire surface with a resist, and a step of selectively removing the resist;
Etching the first silicon thermal oxide film using the resist as a mask, and processing the end of the first silicon thermal oxide film in the vicinity of the peripheral edge of the resist into a tapered shape; Using the oxide film as a mask, anisotropically etching the polysilicon film, and processing the outer peripheral edge of the surface of the polysilicon film into a tapered shape.
て、熱酸化処理を行い、前記ポリシリコン膜のテーパー
部を丸め、該ポリシリコン膜上に第２シリコン熱酸化膜
を形成する工程を含むことを特徴とする請求項２に記載
の半導体装置の製造方法。3. A step of forming a second silicon thermal oxide film on the polysilicon film by performing a thermal oxidation process to round the tapered portion of the polysilicon film after the step of processing into a taper shape. The method for manufacturing a semiconductor device according to claim 2, wherein the method includes:
て、前記第１シリコン酸化膜を除去する工程と、熱酸化
処理を行い、前記ポリシリコン膜のテーパー部を丸め、
該ポリシリコン膜上に第２シリコン熱酸化膜を形成する
工程とを含むことを特徴とする請求項２に記載の半導体
装置の製造方法。4. A step of removing the first silicon oxide film and performing a thermal oxidation process following the step of processing into a tapered shape to round the tapered portion of the polysilicon film.
Forming a second silicon thermal oxide film on the polysilicon film.
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| JP4639445B2 JP4639445B2 (en) | 2011-02-23 |
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| JP2007294908A (en) * | 2006-03-30 | 2007-11-08 | Matsushita Electric Ind Co Ltd | Nanowire transistor, and method of fabricating same |
| KR20190126876A (en) * | 2017-03-22 | 2019-11-12 | 어드밴스드 마이크로 디바이시즈, 인코포레이티드 | Polysilicon's Oscillating Capacitor Architecture for Improved Capacitance |
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| JPH03293724A (en) * | 1990-04-12 | 1991-12-25 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| JPH0766421A (en) * | 1993-08-31 | 1995-03-10 | Ryoden Semiconductor Syst Eng Kk | Thin-film transistor and its manufacture |
| JPH08181146A (en) * | 1994-12-22 | 1996-07-12 | Sony Corp | Manufacture of semiconductor device |
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| JPH022634A (en) * | 1988-06-17 | 1990-01-08 | Fujitsu Ltd | Semiconductor device |
| JPH03293724A (en) * | 1990-04-12 | 1991-12-25 | Oki Electric Ind Co Ltd | Manufacture of semiconductor element |
| JPH0766421A (en) * | 1993-08-31 | 1995-03-10 | Ryoden Semiconductor Syst Eng Kk | Thin-film transistor and its manufacture |
| JPH08181146A (en) * | 1994-12-22 | 1996-07-12 | Sony Corp | Manufacture of semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007294908A (en) * | 2006-03-30 | 2007-11-08 | Matsushita Electric Ind Co Ltd | Nanowire transistor, and method of fabricating same |
| US8368049B2 (en) | 2006-03-30 | 2013-02-05 | Panasonic Corporation | Nanowire transistor and method for fabricating the same |
| KR20190126876A (en) * | 2017-03-22 | 2019-11-12 | 어드밴스드 마이크로 디바이시즈, 인코포레이티드 | Polysilicon's Oscillating Capacitor Architecture for Improved Capacitance |
| CN110462822A (en) * | 2017-03-22 | 2019-11-15 | 超威半导体公司 | For improving the oscillating capacitor framework of capacitor in polysilicon |
| KR102454955B1 (en) * | 2017-03-22 | 2022-10-14 | 어드밴스드 마이크로 디바이시즈, 인코포레이티드 | Oscillating Capacitor Architecture in Polysilicon for Improved Capacitance |
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| Publication number | Publication date |
|---|---|
| JP4639445B2 (en) | 2011-02-23 |
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