JPH0766421A - Thin-film transistor and its manufacture - Google Patents

Abstract

PURPOSE:To prevent the deterioration in gate withstand voltage due to electric field concentration in the upper end portion of a gate electrode. CONSTITUTION:On the substrate 1, a ground insulating film 2 is formed, on which a gate electrode 31 is selectively formed. The gate electrode 31 and the ground insulating film 2 are covered with a gate insulating film 5. On the gate insulating film 5, the following are formed; a polysilicon film 64 where a channel is formed in the vicinity of the gate electrode 31, and a source 62 and a drain 63 in the vicinity of the ground insulating film 2. The upper end portion C of the gate electrode 31 is rounded, its angle is larger than or equal to 90 deg.. Thereby electric field concentration in the upper end portion C of the gate electrode 31 can be prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a thin film transistor used for a static memory, a liquid crystal display and the like and a method for manufacturing the thin film transistor.

[0002]

2. Description of the Related Art FIG. 53 is a sectional view showing the structure of a conventional thin film transistor (bottom gate type (lower surface control electrode type)) 200. Such a technique is disclosed in, for example, Japanese Laid-Open Patent Publication No. 3-21.
It is disclosed in Japanese Patent No. 8640.

An insulating film 2 is formed on a substrate 1, and a gate electrode 3 made of polysilicon is selectively formed on the insulating film 2. A gate insulating film 5 is formed on these structures, and a semiconductor is formed on the gate insulating film 5. This semiconductor is made of, for example, silicon, and has a body polysilicon film 61 in which a channel of a transistor is formed, a source 62 and a drain 63 of the transistor.

Next, a method of manufacturing the conventional thin film transistor 200 will be described. As shown in FIG. 54, the substrate 1
After depositing the base insulating film 2 and the polysilicon film 3a on the
A resist pattern 4 is formed by the lithography technique. For example, the base insulating film 2 is 1 μm, the polysilicon film 3
a is deposited to a thickness of 2000 angstroms. Next, as shown in FIG. 55, the polysilicon film 3a is etched along the resist pattern 4 by the anisotropic etching method to form the gate electrode 3.

Next, after removing the resist pattern 4,
As shown in FIG. 56, the gate insulating film 5 and the polysilicon film 6 are deposited. For example, as the gate insulating film 5, SiH ₄ —N ₂ O gas is used, and an oxide film is used by CVD at a temperature of 800 ° C.
Deposit to a thickness of 00 Å. Further, the polysilicon film 6 is also deposited to a thickness of 500 angstrom. Then, boron is implanted by the lithography technique and the ion implantation technique to form the source 62 and the drain 63 in the left and right polysilicon films 6 of the gate electrode 3 and the body polysilicon film 61 in the polysilicon film 6 above the gate electrode.
Are respectively formed (FIG. 57).

Next, the operation will be described. Although there are N-type and P-type transistors, the P-type will be described here. First, source 62 has 0V (ground) and drain 63
A negative voltage is applied to. If the voltage of the gate electrode 3 is 0 V (ground) in this state, no current flows between the source 62 and the drain 63. On the other hand, when a gate voltage higher than the threshold value of the body polysilicon film 61 is applied to the gate electrode 3, the surface of the body polysilicon film 61 on the gate side is P-inverted, and a current flows from the source 62 to the drain 63. The above is the basic operation of the thin film transistor.

[0007]

By the way, when a gate voltage is applied to the gate electrode 3, an electric field is generated in the gate insulating film 5. FIG. 58 is an enlarged cross-sectional view of the portion A of FIG. 53, and the lines of electric force 8 in the gate insulating film 5 extending from the channel to the gate are indicated by arrows.

Since the conventional thin film transistor 200 is constructed as described above, the angle θ formed by the upper end of the gate electrode 3 is about 90 ° as shown in FIG. When a large negative voltage such as a voltage equal to or more than the value is applied, the lines of electric force 8 concentrate at the end portion.

Therefore, the dielectric breakdown of the gate insulating film 5 occurs at this end portion, and there has been a problem that a withstand voltage lower than the original dielectric breakdown voltage of the gate insulating film 5 can be obtained.

FIG. 59 is a sectional view showing a post-process in the case where the polysilicon film 6 is oxidized to be thinned. in this case,
As shown in the figure, the oxidizer 10 is used for oxidation, but the body polysilicon film 61 is locally thinned at the end portion as compared with the others. For this reason, there have been problems such as breaking the wire.

Further, in the thin film transistor, it is necessary to thin the gate insulating film 5. The thin film transistor is used as a load in, for example, an SRAM memory cell, reduces leakage and power consumption, and improves storage operation speed as compared with a high resistance load type SRAM memory cell. 60 and 61
FIG. 3 is a circuit diagram of a high resistance load type SRAM memory cell and a type of SRAM memory cell using a transistor as a load. As can be seen by comparing the two figures, when the transistor is used as a load, the number of transistors is increased by two, so that the memory cell is enlarged and the wiring becomes complicated.

On the other hand, although it is desirable to form the load transistor in bulk, it is not necessary to have the performance of other transistors forming the memory cell. Therefore, in order to save the cell area, it is desirable that the cell has a two-layer structure and a transistor serving as a load is formed in the upper layer. Therefore, a thin film transistor made of polysilicon is used for the SRAM memory cell, not a bulk transistor which is difficult to form in an upper layer via an insulating layer like a single crystal. Since the number of steps of the bottom gate type is smaller than that of the top gate type even in the thin film transistor, the latter is often used.

When the thin film transistor is used as described above, it is necessary to thin the gate insulating film as the size of the SRAM memory cell is reduced. In this case, the condition of the reliability of the breakdown voltage of the gate insulating film becomes strict due to the increase of the electric field. To alleviate this, it is necessary to improve the edge portion of the gate insulating film.

The present invention has been made to solve the above-mentioned problems, and improves the dielectric breakdown voltage of the gate insulating film 5 and also localizes at the end portion when the body polysilicon film 61 is oxidized. It is an object of the present invention to obtain a thin film transistor that is not thinned or broken, and to provide a manufacturing method thereof.

[0015]

A first aspect of a thin film transistor according to the present invention is a substrate having at least an upper surface thereof having an insulating property, a gate electrode selectively formed on the substrate, a gate electrode and a gate. The electrode includes a gate insulating film formed on the upper surface of the substrate which allows exposure, and an active layer made of a semiconductor formed on the gate insulating film. The angle of the upper end of the gate electrode is larger than 90 °.

For example, the upper end of the gate electrode has a recess. Alternatively, the gate electrode further includes a side wall which is in contact with the side surface of the gate electrode and the substrate and which becomes narrower from the substrate toward the upper surface of the gate electrode and is covered with the gate insulating film. The sidewall may be insulative or conductive.

Alternatively, for example, the gate electrode has a gate nucleus formed on the substrate and a conductive material covering the gate nucleus. The gate core may be insulative. The sidewalls of the gate nuclei are preferably tapered.

Second Embodiment of Thin Film Transistor According to the Present Invention
And a substrate having an insulating surface at least on its upper surface,
The semiconductor device includes an insulating film formed on the substrate, a gate electrode which is included in the insulating film and selectively formed on the substrate, and an active layer made of a semiconductor formed on the insulating film.

A first aspect of the method of manufacturing a thin film transistor according to the present invention is: (a) a step of selectively forming an electrode material on a substrate having an insulating surface at least on the upper surface thereof;
(B) a step of oxidizing the electrode material and rounding the upper end thereof to form a gate electrode; and (c) a step of forming a gate insulating film on the upper surface of the substrate where the gate electrode and the gate electrode are exposed. And (d) a step of forming an active layer made of a semiconductor on the gate insulating film.

A second aspect of the method of manufacturing a thin film transistor according to the present invention is that in the step (b), (b) the electrode material is isotropically etched to round the upper end portion to form a gate electrode. It is an alternative to the process.

A third aspect of the method for manufacturing a thin film transistor according to the present invention is: (a) a step of depositing an electrode material on a substrate having an insulating surface at least, and (b) selecting a resist on the electrode material. And (c) isotropic etching using the resist as a mask to etch the electrode material without exposing the substrate,
(D) A step of performing anisotropic etching using the resist as a mask to selectively leave an electrode material on the substrate to form a gate electrode; and (e) a gate electrode and a top surface of the substrate on which the gate electrode is exposed. The method further includes a step of forming a gate insulating film on the gate and (f) a step of forming an active layer made of a semiconductor on the gate insulating film.

A fourth aspect of the method of manufacturing a thin film transistor according to the present invention is: (a) a step of depositing an electrode material on a substrate having an insulating surface at least, and (b) an auxiliary film on the electrode material. The step of forming, (c) the step of selectively forming a resist on the auxiliary film, and (d) the isotropic etching using the resist as a mask to selectively leave the auxiliary film to have a size larger than that of the resist. The step of shaping the
(E) a step of performing isotropic etching using the resist and the shaped auxiliary film as a mask to etch the electrode material without exposing the substrate; and (f) anisotropic etching using the resist as a mask, the electrode material And (g) forming a gate insulating film on the upper surface of the substrate where the gate electrode and the gate electrode are exposed, and (h) gate insulating Forming an active layer made of a semiconductor on the film.

A fifth aspect of the method of manufacturing a thin film transistor according to the present invention is: (a) a step of selectively forming a conductive electrode material on a substrate having an insulating surface at least, and (b) A step of polishing the upper end portion of the electrode material with an abrasive to form a gate electrode, and (c) a step of forming a gate insulating film on the upper surface of the substrate where the gate electrode and the gate electrode are exposed. , (D) forming an active layer made of a semiconductor on the gate insulating film.

A sixth aspect of the method of manufacturing a thin film transistor according to the present invention is: (a) a step of selectively forming a gate electrode on a substrate having at least an upper surface thereof having an insulating property; A step of forming an insulating auxiliary film having the same height as that of the gate electrode on the substrate in contact with the gate electrode, and (c) the gate insulating film on the structure obtained by the step (b). And (d) a step of forming an active layer made of a semiconductor on the structure obtained in step (c).

A seventh aspect of the method of manufacturing a thin film transistor according to the present invention is: (a) a step of selectively forming a gate electrode on a substrate having an insulating surface at least, and (b) at least a gate electrode. And (c) anisotropically etching the auxiliary film to contact the side surface of the gate electrode and the substrate, and the side wall becomes narrower from the substrate toward the upper surface of the gate electrode. And (d) a step of forming a gate insulating film on the structure obtained by the steps (a) to (c), and (e) forming an active layer made of a semiconductor on the gate insulating film. And a process.

Preferably, in the step (c) in the seventh aspect, the etching rate of the auxiliary film is higher than the etching rate of the gate electrode.

More preferably, the auxiliary film contains a semiconductor material as one of the components. For example, the auxiliary film may be single crystal, polycrystal,
It consists essentially of amorphous and / or microcrystalline silicon.

Alternatively, preferably, the auxiliary film is made of a material substantially different from the material forming the gate electrode. For example, the auxiliary film is a silicon compound containing at least one of oxygen, nitrogen, phosphorus, boron, carbon and an organic material. Or III
-Group V compound. Or it is a chalcogen compound.

An eighth aspect of the method of manufacturing a thin film transistor according to the present invention is: (a) a step of forming an auxiliary film on the substrate; and (b) selectively forming a first mask on the auxiliary film. And (c) anisotropic etching is performed using the first mask to selectively leave the auxiliary film on the substrate,
Forming a protruding gate nucleus with respect to the substrate,
(D) forming a conductive material covering the gate nucleus, and (e)
A step of forming a second mask larger than the first mask on the conductive material, and (f) anisotropic etching using the second mask to selectively leave the conductive material to leave the gate nucleus. Together with the step of forming a gate electrode, (g) a step of forming a gate insulating film on the structure obtained in steps (a) to (f), and (h) an active layer made of a semiconductor on the gate insulating film. Forming a layer.

Preferably, the upper surface of the substrate is insulative, the auxiliary film is conductive, and in step (c), the part of the auxiliary film which is not covered with the first mask is removed. .

Alternatively, preferably, the auxiliary film is insulative, and in the step (c), a part of the auxiliary film which is not covered with the first mask is thinned by anisotropic etching. Left behind.

[0032]

In the first aspect of the thin film transistor according to the present invention, since the angle formed by the upper end portion of the gate electrode is larger than 90 °, it is less than the angle formed by the upper end portion of the gate electrode in the conventional case. is there. Therefore, the electric field concentration in the gate insulating film in the vicinity of this end is relaxed. Further, even if the active layer is oxidized, it is not locally thinned at this end. Here, the “angle formed by the upper end portion of the gate electrode” means the tangent line at one point of the “upper end portion of the gate electrode” and the line showing the upper surface of the “gate electrode” in the cross section of the gate electrode. It is defined as the angle formed.

Second Embodiment of Thin Film Transistor in the Present Invention
In this mode, the thickness of the gate insulating film on the side surface of the gate electrode is equivalently increased, and the electric field concentration in the gate insulating film is reduced. Further, since the active layer is formed in a flat shape, it does not become thin locally even if it is oxidized.

Further, in the first aspect of the method of manufacturing a thin film transistor according to the present invention, when the gate electrode is formed, the electrode material constituting the gate electrode is oxidized and the upper end portion of the gate electrode is rounded. Is suitable for manufacturing the first aspect of the thin film transistor in.

Further, in the second aspect of the method of manufacturing a thin film transistor according to the present invention, when the gate electrode is formed, the electrode material constituting the gate electrode is isotropically etched. Since the etching rate is locally increased and this portion is rounded, it is suitable for manufacturing the first aspect of the thin film transistor of the invention.

In the third aspect of the method of manufacturing a thin film transistor according to the present invention, the upper end of the gate electrode is removed by isotropic etching. Therefore, the desirable aspect of the first aspect of the thin film transistor according to the present invention. Suitable for manufacturing.

Further, in the fourth aspect of the method of manufacturing a thin film transistor according to the present invention, isotropic etching in the region surrounded by the resist and the etched auxiliary film progresses so much that the upper end of the gate electrode is made gentler. ,
The effect of isotropic etching in the third aspect can be further enhanced.

In the fifth aspect of the method of manufacturing a thin film transistor according to the present invention, the upper end of the gate electrode is removed by polishing, which is suitable for the production of the first aspect of the thin film transistor according to the present invention.

Further, in the sixth aspect of the method of manufacturing a thin film transistor according to the present invention, since the insulating auxiliary film has the same height as the gate electrode, the active layer is formed in a flat shape, and the thin film transistor according to the present invention. Second
Suitable for the production of the above embodiment.

In the seventh aspect of the method of manufacturing a thin film transistor according to the present invention, since the side wall substantially relaxes the angle formed by the upper end of the gate electrode, the thin film transistor according to the first aspect of the present invention. Suitable for manufacturing. In particular, by delaying the etching of the gate electrode when forming the side wall by etching, the side wall and the gate electrode can be formed well.

Further, in the eighth aspect of the method of manufacturing a thin film transistor according to the present invention, even if the angle formed by the upper end of the gate nucleus is steep, the conductive material covering the edge substantially alleviates this angle. Therefore, it is suitable for manufacturing the first aspect of the thin film transistor in the present invention.

[0042]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> FIG. 1 is a sectional view of a thin film transistor 100 according to a first embodiment of the present invention. Board 1
A base insulating film 2 is formed on the base insulating film 2, and a gate insulating film 31 is selectively formed on the base insulating film 2.

Unlike the conventional thin film transistor 200 shown in FIG. 53, the upper end portion of the gate electrode 31 has about 3 edges.
It is rounded to a diameter of 00 Å. For this reason,
When a gate voltage is applied to the gate electrode 31, the electric field is prevented from concentrating at this end, and the breakdown voltage does not deteriorate at this end. Therefore, the breakdown voltage of the thin film transistor 100 is improved. Further, even if the polysilicon film 6 is oxidized, it is not thinned locally in the vicinity of the upper end of the gate electrode 31 to cause disconnection.

<Second Embodiment> FIGS. 2 to 5 are sectional views showing a method of manufacturing a thin film transistor 100 according to a second embodiment of the present invention.

Similar to the conventional technique, first, the base insulating film 2 and the polysilicon film 3a are sequentially deposited on the substrate 1, and then the resist pattern 4 is selectively formed by the lithography technique (FIG. 2). The polysilicon film 3a is deposited to a thickness of 2400 angstrom, for example. Then, using the resist pattern 4 as a mask, anisotropic etching such as reactive ion etching is performed to pattern the polysilicon film 3a. As a result, the polysilicon film 3b remains (FIG. 3). At this point, the upper end of the polysilicon film 3b has an acute angle of about 90 °.

Next, the polysilicon film 3b is oxidized to form an oxide film 30 with a thickness of, for example, 500 Å. This oxidation is performed at 800 to 1000 ° C. in an oxygen atmosphere by using, for example, annealing in a furnace. At this time, the upper end of the polysilicon film 3b is oxidized from both the upper side and the lateral side, so that the upper end is rounded to form the gate electrode 31 and the oxide film 30 so as to cover the gate electrode 31 (see FIG. 4). After that, the oxide film 30 is etched to expose the gate electrode 31 (FIG. 5). This etching is performed by plasma etching using CF ₄ —O ₂ gas, for example.

In the subsequent steps, the gate insulating film 5 and the polysilicon film 6 are deposited and the source 62, the drain 63, and the body polysilicon film 64 are formed by the lithography technique and the ion implantation technique, as in the conventional case. The thin film transistor 100 shown in FIG. 1 is formed.

Although the width of the gate electrode 31 becomes narrower than that of the polysilicon film 3b due to the oxidation, when the polysilicon film 3b is formed by the lithography technique and the anisotropic etching, it becomes thicker in advance by the thinness (for example, 600 angstroms thick for the final gate size)
It should be formed. Further, the film thickness becomes thin due to oxidation, but if this is also deposited in advance (for example, 300 angstroms thick with respect to the size of the gate to be finally obtained), there is no problem.

<Third Embodiment> FIGS. 6 and 7 are sectional views showing a method of manufacturing a thin film transistor 100 according to a third embodiment of the present invention.

In the second embodiment, the polysilicon film 3b is left in the same manner as shown in FIGS. 2 and 3 (that is, in the same manner as the conventional technique). After that, the polysilicon film 3b is etched from the entire surface by an isotropic etching method (FIG. 6). This etching is performed by 300 angstroms by plasma etching using CF ₄ —O ₂ gas, for example. At this time, the upper end portion of the polysilicon film 3b is etched from both the upward direction and the lateral direction. Therefore, the etching is accelerated, and the gate electrode 31 having a rounded upper end is formed (FIG. 7).

Although the size of the gate electrode 31 becomes smaller than the size of the polysilicon film 3b due to the isotropic etching on the entire surface, the size of the polysilicon film 3b is set in advance as described in the second embodiment. If it is large, for example, 600 angstroms thick and 300 angstroms thick with respect to the size of the gate to be finally obtained, no problem will occur.

<Fourth Embodiment> FIGS. 8 to 11 are sectional views showing a method of manufacturing a thin film transistor according to a fourth embodiment of the present invention. After depositing the base insulating film 2 and the polysilicon film 3a in this order on the substrate 1 in the same manner as the conventional technique, the resist pattern 4 is selectively formed by the lithography technique (FIG. 8).

Then, the polysilicon film 3a is etched by using the resist pattern 4 as a mask by an etching method having an isotropic etching direction. At this time, the polysilicon film 3a not covered with the resist pattern 4 is not entirely removed, but etching is stopped by leaving the polysilicon film 3a to a thickness of, for example, half. Such an isotropic etching method includes, for example, a method of exciting CF ₄ gas with plasma to perform etching. Since the etching is performed in an isotropic direction, a concave portion 301 exposed in a smooth curve is formed in the polysilicon film 3a below the end portion of the resist pattern 4 (FIG. 9).

Then, using the resist pattern 4 as a mask, the polysilicon film 3a is subjected to anisotropic etching such as reactive ion etching. The etching in this case is performed until the underlying insulating film 2 is exposed. This forms the gate electrode 32 (FIG. 10), but the recess 3
Since 01 was formed below the resist pattern 4, it was left without being subjected to anisotropic etching.
Therefore, the angle of the upper end of the gate electrode 32 is 90 °.
Will be wider than.

After that, the resist pattern 4 is removed by the same process as the conventional process, and the gate insulating film 5 and the polysilicon film 6 are formed.
Is deposited, and the source 62, the drain 63, and the body polysilicon film 65 are formed by the lithography technique and the ion implantation technique.
To form a thin film transistor 101 (see FIG.
1).

The thin film transistor 10 thus formed
Also in No. 1, the electric field is not concentrated at the upper end portion of the gate electrode 32, so that the dielectric breakdown voltage is improved. Further, even if the polysilicon film 6 is heat-treated, the upper end portion of the electrode 32 is not locally thinned to cause disconnection.

In the third embodiment, since the corners of the gate are directly rounded by oxidation, two steps of oxidation and etching are sufficient. However, the accuracy of the finished size of the gate by etching is relatively poor. On the other hand, in the fourth embodiment, since the photolithography process is required before etching, the number of processes is large, but the accuracy of the finished dimension of the gate is relatively excellent.

The gate electrode 3 is formed by isotropic etching.
2 is formed, the size of the formed gate polysilicon film 32 becomes smaller than the size of the resist pattern 4, and a fine pattern cannot be formed. for that reason,
It is necessary to combine anisotropic etching without etching the polysilicon film 3a by isotropic etching.

Further, the recess 3 provided in the gate electrode 32
It is desirable that the isotropic etching is not excessive so that the angle θ formed by 01 and the side surface of the gate electrode 32 does not become small, specifically, becomes larger than 90 °.

<Fifth Embodiment> In the fourth embodiment, the upper end of the gate electrode 32 is prevented from being sharpened by the isotropic etching, but the effect can be further enhanced by the fifth embodiment.

12 to 15 are sectional views showing a method of manufacturing a thin film transistor which is a fifth embodiment of the present invention. As shown in FIG. 12, a base insulating film 2 and a polysilicon film 3a are deposited on a substrate 1, and a silicon oxide film 7 is further deposited on the polysilicon film 3a to a thickness of 500 angstroms, for example. Then, the resist pattern 4 is selectively formed on the silicon oxide film 7 by using a lithography technique.

Next, the silicon oxide film 7 is etched with hydrofluoric acid. Since the etching direction is isotropic, the silicon oxide film 7 is etched under the end portion of the resist pattern 4 so that the silicon oxide film 71 remains and an undercut 701 is generated, as shown in FIG. Undercut 7
The length UC of 01 is, for example, 300 Å.

Next, similarly to the fourth embodiment, isotropic etching is performed to form a recess 302 on the polysilicon film 3a (FIG. 14), and anisotropic etching is performed to form the gate electrode 33. Formed (FIG. 15).

FIG. 16 is a sectional view for explaining a comparison between the fourth embodiment and this fifth embodiment. The fifth embodiment is characterized in that the silicon oxide film 7 is wet-etched with hydrofluoric acid to form an undercut 701, and then the polysilicon film 3a is etched by isotropic etching.

Without the undercut 701, the hemisphere is etched from the end of the pattern (silicon oxide film 7) to form the recess 301 as shown by the broken line. On the other hand, when there is the undercut 701, the etching gas 9 enters the undercut 701 and the etching proceeds from the end portion 71a of the silicon oxide film 71.
Moreover, since the amount of the etching gas 9 entering the undercut 701 is smaller than the amount of the etching gas 9 advancing to the polysilicon film 3a other than the undercut 701,
The etching from the end 71a is slow.

From the above results, the shape of the concave portion 302 formed when the undercut 701 is present is the concave portion 301.
The angle of the upper end portion of the gate electrode 33 is more obtuse than that of the gate electrode 32, and has a more desirable shape.

After that, the resist pattern 4 and the silicon oxide film 71 are removed, and the process shown in FIG. 11 in the fourth embodiment is performed to complete the thin film transistor 101.

Since it is necessary to prevent the etching gas 9 from entering the undercut 701, the silicon oxide film 7
It is desirable to form a thin film of 100 to 1000 angstroms.

The silicon oxide film 7 may be replaced with a silicon nitride film. However, in that case, phosphoric acid or the like is used instead of hydrofluoric acid as an etching liquid for forming the undercut 701.

<Sixth Embodiment> FIGS. 17 to 23 are sectional views showing a method of manufacturing a thin film transistor according to a sixth embodiment of the present invention in the order of steps. Similarly to the conventional technique, first, the base insulating film 2 and the polysilicon film 3a are sequentially deposited on the substrate 1 (FIG. 17). The polysilicon film 3a is previously thickly deposited, for example, to a thickness of, for example, about 2000 angstroms for a polishing step described later.

Then, the resist pattern 4 is selectively formed by the lithography technique (FIG. 18), etching is performed using this as a mask, and the polysilicon film 3a is patterned to leave the polysilicon film 3b (FIG. 19). After that, the resist pattern 4 is removed and the polysilicon film 3b is exposed (FIG. 20).

After this, a polishing step is performed as shown in FIG. Polysilicon particles 11 as an abrasive are mixed with pure water and sprayed onto the structure shown in FIG. 20, and at the same time, a brush scrubber 12 having a brush made of Teflon is rotated in the direction shown by arrow P while the arrow is shown. Proceed in the direction indicated by Q.

By bringing the brush scrubber 12 into contact with the structure shown in FIG. 20 and scanning, the corners 303 of the polysilicon film 3b can be dropped and shaped into a broken line. At this time, the polysilicon film 3 is shaped by shaping.
The polysilicon film 3a was previously thickly deposited so that the thickness b may be thin. Then, the polysilicon film 3b shaped by this polishing step is left as the gate electrode 34 on the base insulating film 2 (FIG. 22). Although it depends on how the polysilicon film 3b and the brush scrubber 12 are overlapped with each other, when the brush scrubber 12 does not come into contact with the base insulating film 2, the base insulating film 2 is hardly scraped. Further, even when they are in contact with each other, the polishing rate is small, so that the amount of polishing of the base insulating film 2 is small, which is not a problem. For example, the polishing rate of the polysilicon film 3b is 500 to
It is 1000 angstrom / min, and that of the base insulating film 2 is 100 angstrom / min. Therefore, it is sufficient that the thickness of the base insulating film 2 is 1000 angstrom.

Although polysilicon particles are used as the polishing material here, any material may be used as long as it does not adversely affect the transistor to be formed. For example, abrasives such as those used in chemical mechanical polishing (eg aluminum oxide, colloidal silicon oxide)
May be used.

After the polishing process is completed and the gate electrode 34 is formed, a process such as washing with water is performed so that the polishing material does not remain. Then, the gate insulating film 5 and the polysilicon film 6 are deposited (FIG. 23). After that, the source, drain, and body polysilicon films are formed by the lithography technique and the ion implantation technique to complete the thin film transistor.

The thin film transistor obtained by the method of manufacturing the thin film transistor according to the sixth embodiment also has an upper portion of the gate electrode 34 similarly to the thin film transistors obtained by the method of manufacturing the thin film transistor according to the second to fifth embodiments. Since the angle formed by the edges of the thin film transistor becomes gentle, the electric field is not concentrated there, and the gate breakdown voltage of the thin film transistor is improved. Further, even when the polysilicon film 6 is oxidized by the heat treatment after forming the thin film transistor, only the upper end portion is not thinned.

<Seventh Embodiment> FIG. 24 is a sectional view showing a method of manufacturing a thin film transistor, which is a seventh embodiment of the present invention. A polishing cloth 13 is used instead of the brush scrubber 12 in the sixth embodiment, and the corners of the upper end portion of the polysilicon film 3b are removed by the chemical mechanical polishing method. The polishing cloth 13 is made of polyester, for example. By pressing the polishing cloth 13 in the direction indicated by the arrow R and rotating it in the direction indicated by the arrow S,
Perform polishing. For example, the polishing cloth 13 has a pressure of 0.3 kgf / c.
pressing in m ² approximately, for about 1 minute.

Also by such polishing, the polysilicon film 3b can be shaped into the shape shown by the broken line, and the structure shown in FIG. 22 can be obtained. Therefore, the same effect as that of the sixth embodiment can be obtained.

<Eighth Embodiment> FIGS. 25 to 30 are sectional views showing, in the order of steps, a method of manufacturing a thin film transistor according to an eighth embodiment of the present invention. First, the base insulating film 2 is deposited on the substrate 1 in the same manner as the conventional technique. Further, a polysilicon film is deposited and patterned into a gate electrode shape to form a gate electrode 35 with a thickness of, for example, 2000 angstrom (FIG. 25). 1st to 7th
Unlike the embodiment, the upper end of the gate electrode 35 has an angle of about 90 °.

On top of this, an oxide film 14a is deposited by the CVD method or the like (FIG. 26). Next, while using a chemical such as hydrofluoric acid, the oxide film 14a is polished into a thin film by using a rigid polishing plate to expose the gate electrode 35 (FIG. 27).

Since hydrofluoric acid has no etching effect on polysilicon, when the gate electrode 35 is exposed, polishing cannot proceed any further. That is, the gate electrode 35
Serves as an etching stopper to complete the polishing, and the buried oxide film 14 is left. At this time, the gate electrode 35
The upper surfaces of the buried oxide film 14 and the buried oxide film 14 have the same height when viewed from the base insulating film 2.

Next, the gate insulating film 5 is formed by the CVD method or the like.
For example, it is formed to a thickness of 500 Å (see FIG. 2).
8) Further, a polysilicon film 6 is deposited as an active layer (FIG. 29). Next, a low concentration impurity is introduced into the polysilicon film 6 above the gate electrode 35 to form a channel formation region 67. In addition, the channel formation region 67
P-type impurities at a high concentration on both ends of, for example, 1 × 10
^The source region 66 and the drain region 68 are provided by introducing ²⁰ / cm ³ (FIG. 30).

Similar to FIG. 58, FIG. 31 shows the gate electrode 3
5 shows an electric field distribution in the vicinity of 5. Since the polysilicon film 6 is formed flat, the gate electrode 3
Since it is equivalent to that the gate insulating film 5 is thick on the side wall of 5, the electric field concentration in the gate insulating film 5 due to the angle of the upper end of the gate electrode 35 does not occur. Also,
Even when the polysilicon film 6 is oxidized to be thinned, it is possible to avoid local thinning.

The channel length of the eighth embodiment is shorter than that of the other embodiments.

<Ninth Embodiment> FIGS. 32 to 35 are sectional views showing the basic steps of a method of manufacturing a thin film transistor according to the ninth embodiment of the present invention in the order of steps. First, the base insulating film 2 is deposited on the substrate 1 in the same manner as the conventional technique. Further, a polysilicon film is deposited and patterned into a gate electrode shape to form a gate electrode 35 (FIG. 32). Hereinafter, in this embodiment, the step of patterning the polysilicon film will be referred to as "electrode forming step".

Next, the side wall material 15a is deposited so as to cover the gate electrode 35 (FIG. 33). A polysilicon film deposited by, for example, a CVD method is used for the side wall material 15a, but various materials can be used as described later. Here, it is deposited to a thickness of approximately 2000 angstroms.

Next, the side wall material 15a is subjected to etching having a directionality (anisotropic) such as reactive ion etching to expose the underlying insulating film 2. As can be seen from FIG. 33, since the side wall material 15a is deposited thicker in the vicinity of the end portion of the gate electrode 35 than in other portions,
The side wall material 15a is left on the side surface of the gate electrode 35 by anisotropic etching to form the side wall 15 (FIG. 3).
4). The side wall 15 has, for example, an arcuate shape having a radius R of approximately 2000 angstroms. Hereinafter, in this embodiment, the step of forming the side wall 15 will be referred to as a "frame forming step".

In the subsequent steps, as in the conventional case, the gate insulating film 5 and the polysilicon film are sequentially deposited, and the source 62, the drain 63, and the source 62 are formed by the lithography technique and the ion implantation technique.
Forming the body polysilicon 69, the thin film transistor 1
02 is completed (FIG. 35).

Generally, in a thin film transistor, the thickness of the gate electrode 35 itself, the thickness of the gate insulating film 5 (mainly composed of a silicon oxide film), the body semiconductor thin film formed on the gate insulating film 5 (for example, body polysilicon). When the thickness of the film 69) is very thin, about several tens of angstroms to several μm, the electric field strength generated by a small applied voltage of about 5 V is tens of thousands V / cm to tens of millions of V in each film.
/ Cm is reached. Therefore, even if it has a bottom gate type structure like the thin film transistor 102, when the step between the gate electrode 35 and the base insulating film 2 is alleviated by the side wall 15, it is very effective in improving the breakdown voltage. . This effect can be obtained regardless of the material of each part and the scale and function of the integrated circuit.

The process of this embodiment is basically as described above, but there are various variations depending on the material used for the side wall material. Hereinafter, each material used for the sidewall material will be described.

(1) When using the same material as the gate electrode: Taking the case where the gate electrode 35 is formed of a polysilicon film as an example, this is the case where a polysilicon film is used for the side wall material 15a.

In this case, the anisotropic etching in the framing step can be performed under substantially the same etching conditions as the anisotropic etching in the electrode forming step preceding this.
Therefore, the same device can be used for both steps. This is a large number of processes, such as hundreds of processes, such as the manufacturing process of an LSI, and when the manufacturing device used for each process is very expensive, the process can be simplified and the number of manufacturing devices can be increased. Since it can be saved, industrial advantages such as shortened construction period and reduced manufacturing cost are very large.

The gate electrode 35 is not limited to polysilicon, but may be W-Si, Ti-Si, Mo-Si, Pt-S.
compounds of refractory metal such as i, Pd-Si, Co-Si, Ni-Si and silicon, Al-Si, Al-Cu-S
compounds of relatively low melting point metals such as i and silicon, W, T
refractory metal itself such as i and Mo, Al, Cu, P
The low melting point metal itself such as d or Sn, or a mixture of these various metals or metal silicides or a multilayer film of several kinds of films can be used. In the above description, the gate electrode 35
However, the present invention is not limited to this example, and even when the gate electrode 35 is formed by using these metals or the like, the same material as the gate electrode 35 is used. If is used for the side wall material 15a, the effect is the same as above. (2) In the case of a material similar to the gate electrode: the gate electrode 35
Taking as an example the case where is formed from a polysilicon film,
This corresponds to the case where silicon of different phase states such as single crystal, amorphous, and microcrystal is used as the side wall material 15a.

(A) Amorphous silicon (amorphous silicon) and microcrystalline silicon (microcrystalline silicon)
Etc. are generally formed by a plasma CVD method using a silane-based gas at a temperature lower than that of the polysilicon film which is the material of the gate electrode.

By the way, etching "unevenness" (mainly etching) caused by non-uniformity of the etching process, non-uniformity of the thickness of the side wall material 15a within the wafer, and non-uniformity of wiring thickness of the gate electrode 35 within the wafer. In some cases, overetching may be performed for a short time in order to eliminate the (shortage). In this case, if a material having almost the same etching rate as that of polysilicon is used as described above,
Even if the gate electrode 35 is over-etched, there is an advantage that the side wall material 15a does not project and remain.

(B) When the gate electrode 35 is made of polysilicon, the use of a single crystal film for the side wall material 15a seems to be meaningless in terms of process and technology. The method for forming crystalline silicon is a composite CV such as photo CVD.
In some cases, the method D may be possible to grow at a temperature lower than that of the polysilicon forming the gate electrode 35.

Using a single crystal film for the side wall material 15a
Rather, the case of a material different from the gate electrode described below
Would be useful to.

(3) In case of a material different from the gate electrode: The temperature for forming the side wall material 15a needs to be equal to or lower than the melting point of the gate electrode 35. Therefore, when the gate electrode 35 is made of polysilicon as described above, the sidewall material 15a can be made of amorphous silicon or the like.

However, conversely, the material forming the gate electrode 35 is a film forming temperature of single crystal silicon (900 to 1150 ° C. in the case of vapor phase growth of Si, vapor phase growth that also uses photoexcitation, plasma excitation, etc.). In the case of a material with a melting point (or other phase transition point) higher than about 600 ° C,
A single crystal silicon film can be used as the sidewall material 15a. For example, high melting point metals such as W, Mo, Ti, TiW, alloys thereof, WSi _x , MoSi _x , TiS.
i _x (x ≧ 1) In this case, the gate electrode 35 is made of those silicide compounds.

When the material different from the gate electrode is used for the side wall material 15a, the exposed area of the side wall material 15a at the end of etching becomes larger than that when the same material as the gate electrode or a similar material is used. Therefore, it is easy to detect the endpoint.

There are the following criteria for selecting what to use for the side wall material 15a, and theoretically there should be one that satisfies all the items, but at the current technical level (especially industrial Since it is very difficult to satisfy all of these items in consideration of mass productivity, the design criteria of the semiconductor element to be manufactured (the minimum processing dimension of the element inside the element dimension, the three-dimensional internal structure, It is selected in consideration of required performance) and manufacturing cost.

First, the in-plane uniformity of film thickness and film quality should be good. Secondly, between film thickness and film quality (between each wafer when a plurality of Si wafers are simultaneously formed) or between batches (each when a plurality or a single Si wafer is divided into several times) Good uniformity of film formation process. Third, the chemical composition of the film is considered. Fourthly, the uniformity of the throwing power of the film at the step portion (step coverage) is good. These are the selection criteria.

Since the gate electrode 35 is generally made of polysilicon, the material of the side wall material 15a will be described below taking this case as an example.

(A) In the case of silicon oxide film: The silicon oxide film is a film having a composition stoichiometrically close to that of SiO ₂ formed by the CVD method using a silane-based gas.
It is easy to deposit evenly on a stepped portion such as the gate electrode 35, and the framing process can be performed more uniformly.

As the CVD method, a thermal CVD method using a thermochemical reaction of the above gas, a plasma CVD method using plasma,
An optical CVD method using a photochemical reaction, a composite CVD method combining them (optical plasma CVD, etc.), or the like is used.
In particular, the silicon oxide film obtained by the CVD method has several steps better in terms of film thickness and film quality than other films such as in-plane or between batches, and has a very stable accumulation of technology in industry.

Among these CVD methods, the thermal CVD method is
For example, when a SiH ₄ / N ₂ O mixed gas is used, a silicon oxide film having a relatively stoichiometric composition (represented by the composition of SiO ₂ ) is easily formed and a film having a uniform film quality is obtained. .

TEOS gas (Tetra-Etho)
An oxygen-rich film (SiO _x : x> 2) can be formed by using xy-Silane-based gas. However, the film forming temperature is 700 to 900 ° C., which is higher than that of other CVD methods, and the number of heating steps is increased.
The manufacture of SI has some disadvantages.

On the other hand, the plasma CVD method is 300 to 700.
There is an advantage that the film forming temperature is about 0 ° C., which is lower than that of the thermal CVD. However, there is a disadvantage that it is difficult to obtain a stoichiometric silicon oxide film, and stress and strain easily occur.

Although various methods for forming a silicon oxide film have merits and demerits as described above, a method suitable for the design of a semiconductor element to be manufactured, that is, a film forming temperature required in the process,
The object of the present invention can be achieved by considering the internal stress and the magnitude of strain, the uniformity of the film, and the stoichiometric composition that largely influences the anisotropic etching conditions in the subsequent process. .

(B) Silicon nitride film: The same applies to the silicon nitride film as the above-mentioned silicon oxide film. That is, the silicon nitride film is generally formed by a CVD method using a silane-based gas, and there are several kinds of CVD methods for forming a silicon nitride film, which are almost the same as those for the silicon oxide film. Moreover, the uniformity of the film thickness and the film quality can be obtained as in the case of the silicon oxide film.

Heat C using silane gas and ammonia gas
The VD film is a low-stress film which is stoichiometrically close to Si ₃ N ₄ . In the case of thermal CVD, it is possible to form a film at a temperature about 50 to 100 ° C. lower than that of a silicon oxide film, but the reaction temperature is higher than in the case of forming a film by the plasma CVD method in which the same gas system is used for film formation.

Therefore, even when the silicon nitride film is formed, as in the case of forming the silicon oxide film, the internal stress and strain magnitude of the film forming temperature required in the process, the film uniformity, etc. The object of the present invention can be achieved by selecting the film forming method according to the above.

It is easy to control the shape of the side wall 15 by utilizing the fact that the etching selection ratio between polysilicon and the silicon nitride film is small. Side wall material 1 using silicon nitride film
When etching 5a, due to the non-uniformity of the etching and the non-uniformity of the film thickness, the underlying polysilicon (which constitutes the gate electrode 35) is partially exposed to form a silicon nitride film to be etched. The area may be greatly reduced. However, since the selection ratio between the etching of the silicon nitride film and the etching of polysilicon is small, the etching rate seen from the etching gas hardly changes, and eventually the silicon nitride film can be uniformly etched, and the shape of the side wall 15 is changed. Control is also easy.

(C) In the case of a silicon compound containing oxygen and nitrogen (hereinafter abbreviated as SiON for simplicity) thin film: technological progress is slightly delayed as compared with the above-mentioned silicon oxide film and silicon nitride film. Therefore, the uniformity is industrially degraded. However, since the silicon oxide film and the silicon nitride film have intermediate properties, this SiON film may be suitable depending on the patterning shape of polysilicon and the size and area ratio of the step portion.

The SiON film is formed, for example, by low temperature plasma CVD of SiH ₄ --N ₂ gas system,
It can be etched with phosphoric acid held at 180 ° C.

(D) In the case of a silicon compound containing at least one of boron and phosphorus: In this case, a silicon oxide film PSG (Phospho-Silicate-Gla) containing phosphorus is used.
ss), a silicon oxide film containing both phosphorus and boron, B
PSG (Boron-Phospho-Silicat)
Since e-Glass) is a general film, they will be described as an example.

In the case of PSG, a film containing about several percent of P atoms has a softening property at the time of heating of 7 as compared with a pure silicon oxide film.
It is as low as 00-900 ° C. Therefore, there is an advantage that the step portion can be flattened by re-flowing in the heating process after the film formation. Further, the film forming temperature is as low as 400 to 600 ° C. when the atmospheric pressure CVD method is used, and the film is formed so as to fill up the step portion during the film forming, so that a certain degree of flatness is already secured immediately after the film forming. It also has the advantage that it can be done.

Since the behavior against anisotropic dry etching is almost the same as that of a pure silicon oxide film, PS
G is also suitable for controlling the shape of the side wall 15.

BPSG is a material in which PSG contains boron atoms in the same amount as about several percent as phosphorus atoms. Softness is better than PSG, and flatness by reflow is better. Therefore, it is suitable for controlling the shape of the side wall 15 as in the case of the PSG.

In addition to the above PSG and BPSG, there is a material which is generally called SOG (Spin-On-Glass) and which is liquid at room temperature and contains various impurities such as B, P, As and Sb. This SOG is a mixture of a silanol (Si-OH) type substance in an alcohol type solvent,
Desolvation and dehydration reactions occur at high temperatures, resulting in the above PSG, BP
It becomes a silicon oxide film containing a few percent of impurities similar to SG. Therefore, the present invention can be applied even if this SOG is used for the side wall material 15a.

In the process of baking the SOG film, some molecules of the organic solvent such as alcohol and carbon atoms may remain in the SOG film. However, unless an extremely high electric field or high frequency is applied to the film, the SOG fired film has almost the same properties as the silicon oxide film formed by another method. SO
When a liquid material such as G is used, even if the surface of the wafer to be formed is highly uneven, the film can be formed with better flatness than the film formed by the CVD method.
It is desirable as the side wall material 15a.

The "silicon compound thin film containing an organic substance" referred to in the present invention is a general term for a silicon oxide film formed by using an organic solvent as a base and a liquid as a base material such as SOG.

(E) In the case of an organic polymer compound film: A polyimide film, a silicone varnish film or the like has a high viscosity, has a relatively high curing point, and has good coverage of the step portion near the end of the gate electrode 35. An organic compound can also be used for the side wall material 15a. Alternatively, an organic compound containing silicon or another semiconductor material can be used.

These films can also be formed in the same process as in the case of SOG, in that a liquid material is applied and baked. Similar to SOG, it has excellent flatness and high viscosity, so that it is easy to form a thick film of several μm to several tens of μm.

After a chemical reaction such as solvent removal, dehydration reaction, polymerization or condensation occurs, an insulating film which is chemically, thermally and electrically stable is formed. In particular, the polyimide resin exhibits insulating properties comparable to those of silicon oxide film.

Further, the dry etching of the organic polymer compound film can be easily carried out by using a gas of oxygen containing CF ₄ type or SF ₆ type.

(F) Carbon Silicon Compound Film Single crystal carbon silicon (hereinafter abbreviated as SiC) has a melting point higher than that of silicon in both α phase and β phase, and is a material that is chemically very stable at room temperature. is there. At the current state of the art, it is difficult to obtain a single crystal film as compared with silicon, but a polycrystalline, amorphous, or microcrystalline SiC film is relatively simple, as with a silicon film by sputtering or CVD. Can be obtained. Further, doping of impurities into the SiC film is easy. Therefore, it can be used as the side wall material 15a in the same manner as in the case of the above-described polysilicon.

(G) In the case of a III-V group compound: As described above, if the film can be formed at a temperature lower than the melting point of the material forming the gate electrode 35, it is adopted as the material of the side wall material 15a. Can be applied to examples.

The III-V semiconductor compound is GaAs,
Widely known compounds such as InP, their complex compounds, B
A wide bandgap semiconductor compound having a wide band width such as N, BP, and GaN, and further a composite compound thereof and the like.

GaAs, InP, etc. include MOCVD, MBE (Mol, etc.), including crystal growth such as vapor phase growth and liquid phase growth.
electrical Beam Epitaxy) method, ICB
In the (Ion Cluster Beam) method, the sputtering method, the vapor deposition, or the like, a polysilicon film is formed (500 to 70
0 ° C) or lower temperature (RT ~ 500)
The film can be formed at (° C).

Similar to the case of SiC, the crystal growth temperature of BN, BP, GaN, etc. is often higher than that of polysilicon, and therefore the formation of a single crystal film is not suitable for this embodiment. However, when forming a polycrystalline or amorphous film by a sputtering method or the like, it is possible at a relatively low temperature.

(H) In the case of chalcogen compound: As in the case of the III-V group compound, a chalcogen compound can be used as the side wall material 15a in view of low temperature film formation and etching selectivity. Among chalcogen compounds, α
-Se, α-Te, α-S, α-As ₂ Se ₃ , α-A
s ₂ Se ₃ , α-GeSe ₂ (α-indicates amorphous), a polycrystal phase thereof, a microcrystal phase thereof, a mixture thereof, or the like can be formed into a film by a relatively simple method.

The chalcogen compound is a group VI element S, S
Since e, Te and the like have a low melting point of about 120 to 450 ° C., their compounds themselves are also about 100 to 60.
Many of them have a low melting point of 0 ° C, and if a single crystal is not desired, CVD is relatively easy in both liquid phase and gas phase reactions.
Film formation can be performed at a relatively low temperature including sputtering and sputtering.

(I) Others: As an oxide type, Ta
O _x , TlO _x , WO _x , MoO _x , TiBa _x O _y ,
It is also possible to adopt TiO _x or VO _x as the side wall material 15a and apply it to this embodiment.

When the side wall material 15a is an insulator, the upper end of the gate electrode 35 remains sharp.
Due to the existence of the side wall 15, the gate insulating film 5 is separated from the bent portion, and the electric field concentration is reduced. Also, the side wall material 15
When a is a conductor, the side wall 15 functions integrally with the gate electrode 35, so that the electric field concentration is alleviated as in the other embodiments.

<Tenth Embodiment> FIGS. 36 to 41 are sectional views showing, in the order of steps, a method for manufacturing a thin film transistor, which is a tenth embodiment of the present invention. First, the base insulating film 2 and the polysilicon film 3a are sequentially deposited on the substrate 1. afterwards,
A resist pattern 41 having a shape smaller than that of the finally formed gate electrode is formed by a lithography technique (FIG. 3).
6).

Next, using the resist pattern 41 as a mask, anisotropic etching is performed on the polysilicon film 3a until the underlying insulating film 2 is exposed (FIG. 37). As a result, the polysilicon film 3a becomes a polysilicon film 3b which becomes a gate nucleus.
Is shaped into

Next, the resist pattern 41 is removed, and the polysilicon film 16a is deposited by the LP-CVD method (FIG. 38). Since the polysilicon film 16a is isotropically deposited on the polysilicon film 3b in the LP-CVD method, the polysilicon film 16a gently curves at the upper end of the polysilicon film 3b.

On the polysilicon film 16a, a resist pattern 4 having a shape larger than the resist pattern 41 is formed.
2 is formed by the lithography technique (FIG. 39). For example, the exposure accuracy is ± 0.1 μm, and the polysilicon film 3
If the width b is 1 μm and the polysilicon film 16a is deposited to a thickness of 0.6 μm, the resist pattern 4
The width of 2 is selected to be 1.2 to 1.4 μm, for example 1.3 μm.

Then, using the resist pattern 42 as a mask, the polysilicon film 16a is etched by anisotropic etching until the underlying insulating film 2 is exposed, and the polysilicon film 16 is left. The polysilicon film 3b and the polysilicon film 16 form a gate electrode 36 (FIG. 40). The shape of the gate electrode 36 reflects the shape of the gate polysilicon film 16a at the time of deposition, and the upper end portion thereof does not have a sharp edge.

The subsequent steps are the same as in the conventional case. The resist pattern 42 is removed, and the gate insulating film 5 and a polysilicon film as an active layer are sequentially deposited. Then, the source 62, the drain 63, and the body polysilicon 64 are formed by using the lithography technique and the ion implantation technique, and the thin film transistor 103 is completed (FIG. 41).

Similar to the thin film transistor 100, the thin film transistor 103 does not have a sharp edge at the upper end of the gate electrode 36, so that the same effect as that of the first embodiment can be obtained. That is, the breakdown voltage is improved, and disconnection can be avoided even when the active layer is thinned by oxidation.

Although an example of using polysilicon as the material of the gate core and the thin film wrapping the gate core is shown, other materials may be used, or materials different from each other may be used. For example, an oxide film can be used for the gate nucleus, and aluminum silicide can be used as a thin film that wraps it.

<Eleventh Embodiment> FIGS. 42 to 47 are sectional views showing, in the order of steps, a method for manufacturing a thin film transistor, which is an eleventh embodiment of the present invention. First, after depositing the base insulating film 2 on the substrate 1, a resist pattern 41 having a shape smaller than the gate to be finally formed is formed by a lithography technique (FIG. 42).

Next, the underlying insulating film 2 is partially etched by anisotropic etching using the resist pattern 41 as a mask (FIG. 43). For example, etching is performed until the thickness of the base insulating film 2 becomes 1/4 of that. This allows
The base insulating film 2 is shaped into the gate nucleus 2a existing below the resist pattern 41 and the other portion 2b.

Then, the resist pattern 41 is removed,
The polysilicon film 16a is deposited by the LP-CVD method (FIG. 44). Further, a resist pattern 42 is formed thereon by a lithography technique (FIG. 45). As in the tenth embodiment, the shape of the resist pattern 42 is larger than that of the resist pattern 41.

Then, using the resist pattern 42 as a mask, the polysilicon film 16a is exposed until the underlying insulating film 2 is exposed.
Is anisotropically etched. Thereby, the gate nucleus 2a
The polysilicon film 16 that covers is left. This forms the gate electrode 37 with the gate nucleus 2a (FIG. 46).

The subsequent steps are the same as in the conventional case, the resist pattern 42 is removed, and the gate insulating film 5 and the polysilicon film as the active layer are sequentially formed. Then, the source 62 and the drain 6 are formed by using the lithography technique and the ion implantation technique.
3 and body polysilicon 64 are formed to complete the thin film transistor 104 (FIG. 47).

Similar to the thin film transistor 100, the thin film transistor 104 does not have a sharp edge at the upper end of the gate electrode 36, so that the same effect as that of the first embodiment can be obtained. That is, the breakdown voltage is improved, and disconnection can be avoided even when the active layer is thinned by oxidation.
Moreover, as compared with the tenth embodiment, there is an advantage that the step of forming the gate nucleus is simplified.

Next, the relationship between the film thickness of the gate nucleus 2a and the film thickness of the polysilicon film 16a will be examined. This also applies when the polysilicon film 3b in the tenth embodiment is used as the gate nucleus.

The patterning conditions for the polysilicon film 16a shown in FIG. 45 will be described below. Figure 4
8 is an enlarged view of a part of the sectional view in the step shown in FIG. The height (the film thickness of the gate nucleus 2a) at which the gate nucleus 2a projects from the other portion 2b of the base insulating film 2 is S, and the thickness of the polysilicon film 16a deposited on the base insulating film 2 is T. Hereinafter, description will be made corresponding to the two-dimensional expression shown in this cross-sectional view.

The point O is the upper end of the gate nucleus 2a.
Since the polysilicon film 16a is isotropically deposited, the upper surface of the polysilicon film 16a near the point O draws an arc around the point O from the upper surface of the gate nucleus 2a. Gate electrode 3 obtained by patterning the polysilicon film 16a
In order to make the upper end of 7 larger than 90 °, it is necessary to perform patterning at the arc portion.

For example, if patterning is performed at the point A on the arc, the angle θ formed by the foot B of the perpendicular line drawn from the point A perpendicular to the extension of the upper surface of the gate nucleus 2a and the tangent AC of the arc at the point A is determined. Must be greater than 90 °.

A foot of a perpendicular line perpendicular to the extension of the upper surface of the gate nucleus 2a from a point A'on an arc where θ = 90 ° is B '.
And Since the angle θ increases as the point A moves from the point A ′ to the end point A ″ of the arc, patterning needs to be performed between the points A ′ and A ″.

Next, the relationship between the film thickness T of the polysilicon film 16a and the film thickness S of the gate nucleus 2a which gives the largest patterning margin will be described.

Letting B ″ be the foot of a perpendicular line perpendicular to the extension of the upper surface of the gate nucleus 2a from the end point A ″ of the arc, the patterning margin of the polysilicon film 16a is obtained as B ″ B ′.

When the thickness T of the polysilicon film 16a is larger than the thickness S of the gate nucleus 2a, the patterning margin B ″
B'is given by the following equation.

[0158]

[Equation 1]

Of these, the triangle A "B" O has the angle A "B" O which is a right angle, and therefore the length of B "O is given by the following equation.

[0160]

[Equation 2]

Also, since B'O has a triangle A'B'O having a right angle A'B'O, the length of B'O is represented by the following equation.

[0162]

[Equation 3]

The maximum patterning margin is T
= S, and the patterning margin is T. For example, when the film thickness S of the gate nucleus 2a is 2000 angstroms and the film thickness T of the polysilicon film 16a is 2000 angstroms, a patterning margin for making the upper end portion of the gate nucleus 2a larger than 90 °. B ″ B ′ is 2000 Å. The closer the patterning position A is to A ″, the larger θ becomes, and the electric field concentration is further alleviated. However, since the exposure accuracy of the exposure process is ± 500 Å, OB = 150
It was set to 0 angstrom.

When the thickness T of the polysilicon film 16 is smaller than the thickness S of the gate nucleus 2a, the exposure accuracy of the exposure process is more restricted as the thickness T of the polysilicon becomes thinner.

<Twelfth Embodiment> FIG. 49 is a sectional view of a thin film transistor 105 according to a twelfth embodiment of the present invention. A base insulating film 2 is formed on a substrate 1, and a gate nucleus 3c made of polysilicon is selectively formed on the base insulating film 2. Furthermore, above the gate nucleus 3c,
A polysilicon film 17 is formed, and both form a gate electrode 38. The base insulating film 2, the gate nucleus 3c, and the polysilicon film 17 are covered with the gate insulating film 5, and a body polysilicon film 64, a source 62, and a drain 63 in which a channel region is formed are provided on the gate insulating film 5. Has been.

As compared with the thin film transistors 103 and 104 shown in the tenth to eleventh embodiments in which the side surface of the gate nucleus 3b (2a) is perpendicular to the base insulating film 2, the thin film transistor 105 has a side surface of the gate nucleus 3c. Is inclined, the gate electrode 38 having a gentler edge can be obtained, and a more desirable shape can be obtained.

A method of tapering the gate core 3c is known, for example, Kazuo Maeda, "LSI Process Technology" P2.
Published in 76. FIG. 50 is a cross-sectional view showing how the etching of the polysilicon film 3 formed on the base insulating film 2 proceeds. On the polysilicon film 3, a thin film 18 having an etching rate three times slower than that of the polysilicon film 3 is provided. On the thin film 18,
A resist pattern 43 is selectively formed.

As described above, two kinds of films having different etching rates are sequentially deposited from a film having a slow etching rate, and a resist pattern is further formed and etching is performed to obtain the tapered gate nucleus 3c. Etching progresses with the lapse of time, and the etching surface has a curve E ₁ ,
_{E 2, E 3, E 4} , remained to E _5, a polysilicon film 3
The gate nuclei 3c are gradually tapered to form the gate nuclei 3c.

As described above, the patterning position is limited in order to pattern the polysilicon film on the gate nucleus so that the upper end of the gate electrode has an angle larger than 90 °. However, the patternable area of the gate, i.e. the patterning margin, is increased by tapering the gate core.

51 and 52 are sectional views showing patterning margins. For example, when an angle of 100 ° is given to the upper end portion of the gate electrode, the patterning margin M ₁ of the polysilicon film 16a formed on the tapered gate nucleus 3c (FIG. 51) is a gate without a taper. It can be set wider than the patterning margin M ₂ of the polysilicon film 16a formed on the nucleus 3b.

It is needless to say that the thin film transistors described in the above first to twelfth embodiments can be applied not only to PMOS transistors but also to NMOS transistors.

[0172]

As described above, according to the thin film transistor of the present invention, the electric field is not concentrated at the upper end portion of the gate electrode, and the dielectric breakdown voltage of the gate insulating film is improved.

Further, when the active layer is oxidized, it is possible to avoid local thinning and disconnection.
The manufacturing yield of thin film transistors can be improved.

Also, according to the method of manufacturing a thin film transistor of the present invention, the thin film transistor of the present invention can be manufactured appropriately.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 3 is a sectional view showing a second embodiment of the present invention in process order.

FIG. 4 is a sectional view showing a second embodiment of the present invention in process order.

FIG. 5 is a sectional view showing a second embodiment of the present invention in the order of steps.

FIG. 6 is a sectional view showing a third embodiment of the present invention in the order of steps.

FIG. 7 is a cross-sectional view showing the third embodiment of the present invention in the order of steps.

FIG. 8 is a sectional view showing a fourth embodiment of the present invention in the order of steps.

FIG. 9 is a sectional view showing a fourth embodiment of the present invention in the order of steps.

FIG. 10 is a sectional view showing a fourth embodiment of the present invention in the order of steps.

FIG. 11 is a sectional view showing a fourth embodiment of the present invention in the order of steps.

FIG. 12 is a sectional view showing a fifth embodiment of the present invention in the order of steps.

FIG. 13 is a sectional view showing a fifth embodiment of the present invention in the order of steps.

FIG. 14 is a sectional view showing a fifth embodiment of the present invention in the order of steps.

FIG. 15 is a sectional view showing a fifth embodiment of the present invention in the order of steps.

FIG. 16 is a sectional view for explaining the fifth embodiment of the present invention.

FIG. 17 is a sectional view showing a sixth embodiment of the present invention in the order of steps.

FIG. 18 is a sectional view showing a sixth embodiment of the present invention in the order of steps.

FIG. 19 is a sectional view showing a sixth embodiment of the present invention in the order of steps.

FIG. 20 is a sectional view showing a sixth embodiment of the present invention in the order of steps.

FIG. 21 is a sectional view showing a sixth embodiment of the present invention in the order of steps.

FIG. 22 is a sectional view showing a sixth embodiment of the present invention in the order of steps.

FIG. 23 is a sectional view showing a sixth embodiment of the present invention in the order of steps.

FIG. 24 is a sectional view showing a seventh embodiment of the present invention.

FIG. 25 is a sectional view showing an eighth embodiment of the present invention in the order of steps.

FIG. 26 is a sectional view showing an eighth embodiment of the present invention in the order of steps.

FIG. 27 is a sectional view showing an eighth embodiment of the present invention in process order.

FIG. 28 is a sectional view showing an eighth embodiment of the present invention in the order of steps.

FIG. 29 is a sectional view showing an eighth embodiment of the present invention in the order of steps.

FIG. 30 is a sectional view showing an eighth embodiment of the present invention in the order of steps.

FIG. 31 is a sectional view showing an electric field distribution in the eighth embodiment.

FIG. 32 is a sectional view showing the ninth embodiment of the present invention in the order of steps.

FIG. 33 is a sectional view showing the ninth embodiment of the present invention in the order of steps.

FIG. 34 is a sectional view showing the ninth embodiment of the present invention in the order of steps.

FIG. 35 is a sectional view showing a ninth embodiment of the present invention in the order of steps.

FIG. 36 is a sectional view showing a tenth embodiment of the present invention in the order of steps.

FIG. 37 is a sectional view showing a tenth embodiment of the present invention in the order of steps.

FIG. 38 is a sectional view showing a tenth embodiment of the present invention in the order of steps.

FIG. 39 is a sectional view showing a tenth embodiment of the present invention in the order of steps.

FIG. 40 is a sectional view showing a tenth embodiment of the present invention in the order of steps.

FIG. 41 is a sectional view showing a tenth embodiment of the present invention in the order of steps.

FIG. 42 is a sectional view showing the eleventh embodiment of the present invention in the order of steps.

FIG. 43 is a sectional view showing an eleventh embodiment of the present invention in the order of steps.

FIG. 44 is a sectional view showing an eleventh embodiment of the present invention in the order of steps.

FIG. 45 is a sectional view showing an eleventh embodiment of the present invention in the order of steps.

FIG. 46 is a sectional view showing an eleventh embodiment of the present invention in the order of steps.

FIG. 47 is a sectional view showing an eleventh embodiment of the present invention in the order of steps.

FIG. 48 is a sectional view for explaining the tenth to eleventh embodiments of the present invention.

FIG. 49 is a sectional view showing a twelfth embodiment of the present invention.

FIG. 50 is a sectional view illustrating a twelfth embodiment of the present invention.

FIG. 51 is a sectional view illustrating a twelfth embodiment of the present invention.

52 is a sectional view for explaining a twelfth embodiment of the present invention.

FIG. 53 is a cross-sectional view showing the structure of a conventional thin film transistor.

FIG. 54 is a cross-sectional view showing the method of manufacturing the conventional thin film transistor.

FIG. 55 is a cross-sectional view showing the method of manufacturing the conventional thin film transistor.

FIG. 56 is a cross-sectional view showing the method of manufacturing the conventional thin film transistor.

FIG. 57 is a cross-sectional view showing the method of manufacturing the conventional thin film transistor.

FIG. 58 is an enlarged view of a part of FIG. 53.

FIG. 59 is a cross-sectional view illustrating a conventional technique.

FIG. 60 is a circuit diagram illustrating a conventional technique.

FIG. 61 is a circuit diagram illustrating a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Substrate 2 Base insulating film 2a Gate nucleus 3a, 6, 16a Polysilicon film 31-38 Gate electrode 301 Recesses 4, 41, 42 Resist pattern 5 Gate insulating film 64, 65, 67, 69 Body polysilicon film 7 Silicon oxide film 14 Buried oxide film 15 Side wall 15a Side wall material 100-105 Thin film transistor

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Shigeto Maekawa 4-1-1 Mizuhara, Itami-shi, Hyogo Prefecture LS Electric Co., Ltd. LSE Research Laboratory (72) Inventor Shigenobu Maeda 4-1-1 Mizuhara, Itami-shi, Hyogo Prefecture Mitsubishi Electric Co., Ltd. LSI Research Center (72) Inventor Yasuo Yamaguchi 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. LSI Research Center (72) Inventor Mikio Ikeda Mizuhara, Itami City, Hyogo Prefecture 4-chome Mitsubishi Electric Co., Ltd. LSI Research Institute (72) Inventor Tadashi Minato 4-1-1 Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Co., Ltd. LSI Research Center (72) Inventor Tsuneo Yasuda 4-1, Mizuhara, Itami City, Hyogo Prefecture Mitsubishi Electric Corporation LSI Research Laboratory

Claims (26)

[Claims] 1. A substrate having at least an upper surface thereof insulating, a gate electrode selectively formed on the substrate, and the gate electrode and the upper surface of the substrate on which the gate electrode allows exposure. A thin film transistor comprising a formed gate insulating film and an active layer made of a semiconductor formed on the gate insulating film, wherein an angle of an upper end portion of the gate electrode is larger than 90 °. 2. The thin film transistor according to claim 1, wherein the upper end of the gate electrode has a recess. 3. The thin film transistor according to claim 1, further comprising a sidewall that is in contact with a side surface of the gate electrode and the substrate, has a width that decreases from the substrate toward an upper surface of the gate electrode, and is covered with the gate insulating film. . 4. The thin film transistor according to claim 3, wherein the sidewall is insulative. 5. The thin film transistor according to claim 3, wherein the sidewall is conductive. 6. The thin film transistor according to claim 1, wherein the gate electrode includes a gate nucleus formed on the substrate, and a conductive material that covers the gate nucleus. 7. The thin film transistor according to claim 6, wherein the gate nucleus is insulative. 8. The thin film transistor according to claim 6, wherein the gate nucleus has a tapered side wall. 9. A substrate having at least an upper surface thereof having an insulating property, an insulating film formed on the substrate, and a gate electrode included in the insulating film and selectively formed on the substrate. A thin film transistor comprising: an active layer made of a semiconductor formed on the insulating film. 10. (a) a step of selectively forming an electrode material on a substrate having an insulating surface at least on the upper surface thereof; and (b) oxidizing the electrode material to round the upper end portion thereof to form a gate. A step of forming an electrode, (c) a step of forming a gate insulating film on the gate electrode and the upper surface of the substrate where the gate electrode is exposed, and (d) a semiconductor on the gate insulating film. And a step of forming an active layer composed of. 11. (a) a step of selectively forming a conductive electrode material on a substrate having an insulating surface at least on its upper surface; and (b) isotropic etching of the electrode material to form an upper portion thereof. Forming a gate electrode by rounding the end of the gate electrode, (c) forming a gate insulating film on the gate electrode and the upper surface of the substrate where the gate electrode is exposed, and (d) the gate And a step of forming an active layer made of a semiconductor on the insulating film. 12. (a) a step of depositing an electrode material on a substrate having at least an upper surface thereof insulating, (b) a step of selectively forming a resist on the electrode material, and (c) the resist. Is used as a mask to etch the electrode material without exposing the substrate, and (d) anisotropic etching is performed using the resist as a mask to selectively select the electrode material on the substrate. Forming a gate electrode by leaving it above, (e) forming a gate insulating film on the gate electrode and the upper surface of the substrate where the gate electrode is exposed, (f) the gate insulation And a step of forming an active layer made of a semiconductor on the film. 13. (a) depositing an electrode material on a substrate having at least an upper surface thereof insulating, (b) forming an auxiliary film on the electrode material, (c) on the auxiliary film. And (d) isotropic etching using the resist as a mask to selectively leave the auxiliary film and shape the resist to a smaller size than the resist. e) a step of performing isotropic etching using the resist and the shaped auxiliary film as a mask to etch the electrode material without exposing the substrate, and (f) anisotropic etching using the resist as a mask. And (g) leaving the electrode material selectively on the substrate to form a gate electrode, and (g) exposing the gate electrode and the gate electrode on the upper surface of the substrate where the gate electrode is exposed. A method of manufacturing a thin film transistor, comprising: a step of forming an edge film; and (h) a step of forming an active layer made of a semiconductor on the gate insulating film. 14. (a) a step of selectively forming a conductive electrode material on a substrate having an insulating surface at least on its upper surface, and (b) an end portion of the upper portion of the electrode material using an abrasive. And (c) forming a gate insulating film on the upper surface of the substrate where the gate electrode and the gate electrode are exposed, and (d) the gate insulating film. And a step of forming an active layer made of a semiconductor thereon. 15. A step of (a) selectively forming a gate electrode on a substrate having at least an upper surface thereof having an insulating property, and (b) a height equal to the height of the gate electrode as viewed from the substrate. Forming an insulative auxiliary film on the substrate in contact with the gate electrode; (c) forming a gate insulating film on the structure obtained in the step (b); and (d) And a step of forming an active layer made of a semiconductor on the structure obtained in the step (c). 16. (a) A step of selectively forming a gate electrode on a substrate having an insulating surface at least on the upper surface thereof, and (b) a step of forming an auxiliary film covering at least an end portion of the gate electrode. (C) anisotropically etching the auxiliary film to form a sidewall that is in contact with the side surface of the gate electrode and the substrate and has a width that narrows from the substrate toward the upper surface of the gate electrode. A thin film transistor comprising: d) forming a gate insulating film on the structure obtained by the steps (a) to (c); and (e) forming an active layer made of a semiconductor on the gate insulating film. Manufacturing method. 17. The method of manufacturing a thin film transistor according to claim 16, wherein in the step (c), the etching rate of the auxiliary film is higher than the etching rate of the gate electrode. 18. The method of manufacturing a thin film transistor according to claim 17, wherein the auxiliary film contains a semiconductor material as one of its components. 19. The method of manufacturing a thin film transistor according to claim 18, wherein the auxiliary film is substantially made of at least one of single crystal, polycrystal, amorphous, and microcrystal silicon. 20. The method of manufacturing a thin film transistor according to claim 17, wherein the auxiliary film is made of a material substantially different from a material forming the gate electrode. 21. The method of claim 20, wherein the auxiliary film is a silicon compound containing at least one of oxygen, nitrogen, phosphorus, boron, carbon and an organic material. 22. The method of claim 20, wherein the auxiliary film is a III-V group compound. 23. The method of manufacturing a thin film transistor according to claim 20, wherein the auxiliary film is a chalcogen compound. 24. (a) a step of forming an auxiliary film on the substrate; (b) a step of selectively forming a first mask on the auxiliary film; (c) the first mask Anisotropic etching is performed by using, and the auxiliary film is selectively left on the substrate to form gate nuclei protruding from the substrate, and (d) a conductive material covering the gate nuclei. And (e) forming a second mask larger than the first mask on the conductive material, and (f) performing anisotropic etching using the second mask, A step of selectively leaving the conductive material to form a gate electrode together with the gate nucleus; and (g) a step of forming a gate insulating film on the structure obtained by the steps (a) to (f). And (h) forming an active layer made of a semiconductor on the gate insulating film. Method of manufacturing the thin film transistor and a step. 25. The upper surface of the substrate is insulative, the auxiliary film is conductive, and in the step (c), the first of the auxiliary films is formed.
25. Portions not covered by the mask of claim 25 are removed.
A method for manufacturing the thin film transistor described. 26. The auxiliary film is insulating, and in the step (c), the first of the auxiliary films is formed.
25. The portion not covered with the mask is left thinned by the anisotropic etching.
A method for manufacturing the thin film transistor described.