KR100334390B1 - Manufacturing method for dual gate oxide - Google Patents
Manufacturing method for dual gate oxide Download PDFInfo
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- KR100334390B1 KR100334390B1 KR1019980059548A KR19980059548A KR100334390B1 KR 100334390 B1 KR100334390 B1 KR 100334390B1 KR 1019980059548 A KR1019980059548 A KR 1019980059548A KR 19980059548 A KR19980059548 A KR 19980059548A KR 100334390 B1 KR100334390 B1 KR 100334390B1
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- 230000009977 dual effect Effects 0.000 title abstract 2
- 238000004519 manufacturing process Methods 0.000 title description 5
- 238000000034 method Methods 0.000 claims abstract description 43
- 239000004020 conductor Substances 0.000 claims abstract description 17
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 23
- 229920005591 polysilicon Polymers 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 5
- 238000005121 nitriding Methods 0.000 claims description 5
- 238000009279 wet oxidation reaction Methods 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 2
- 238000003475 lamination Methods 0.000 abstract 2
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 230000007547 defect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
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Abstract
본 발명은 이중 게이트산화막 ( dual gate oxide ) 형성방법에 관한 것으로, 패드산화막과 패드도전체의 적층구조를 형성하고 후속공정으로 트렌치를 형성한 다음, 이를 매립하는 화학기상증착 ( chemical vapor deposition, 이하에서 CVD 라 함 ) 절연막을 형성하고, 상기 트렌치 일측의 적층구조를 식각하고 다른 산화막과 다른 도전층의 적층구조를 형성한 다음, 게이트전극 마스크를 이용한 식각공정으로 게이트산화막의 두께가 서로 다른 이중 게이트산화막을 형성함으로써 반도체소자의 고집적화 및 고속화를 가능하게 하는 기술이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a dual gate oxide, wherein a layer structure of a pad oxide film and a pad conductor is formed, a trench is formed in a subsequent process, and then buried therein. CVD), an insulating layer is formed, the lamination structure of one side of the trench is etched, and a lamination structure of another oxide layer and another conductive layer is formed, and then the double gates having different thicknesses of the gate oxide layer are etched using a gate electrode mask. It is a technology that enables high integration and high speed of semiconductor devices by forming oxide films.
Description
본 발명은 이중 게이트산화막 형성방법에 관한 것으로, 특히 높은 처리속도를 필요로 하는 차세대 고집적 소자에서 이용되는 이중 게이트산화막을 제조하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a double gate oxide film, and more particularly, to a method of manufacturing a double gate oxide film used in a next generation highly integrated device requiring a high processing speed.
종래의 이중 게이트 산화막의 제조는 필드산화막이 형성된 실리콘 기판 상에열산화방법으로 1차적으로 게이트산화막을 형성한 후, 감광막을 이용하여 제2게이트산화막이 형성될 부분의 산화막을 제거하고, 감광막을 제거한 다음, 제2게이트산화막을 일정두께 성장시켜 형성한다.In the conventional manufacturing of the double gate oxide film, a gate oxide film is first formed by a thermal oxidation method on a silicon substrate on which a field oxide film is formed, and then the oxide film of the portion where the second gate oxide film is to be formed is removed using the photosensitive film, and the photosensitive film is removed. After the removal, the second gate oxide film is formed by growing a predetermined thickness.
결국, 제1게이트산화막은 제2게이트산화막이 형성될 동안 좀더 산화되어 이중 게이트산화막이 형성되는 것이다.As a result, the first gate oxide film is further oxidized while the second gate oxide film is formed to form the double gate oxide film.
그러나, 이러한 방법으로는 제1게이트산화막과 제2게이트산화막의 상이한 두께 조절이 쉽지 않은 문제점이 있게 된다. 특히 제1게이트산화막의 두께를 조절하기가 힘들어지게 된다.However, this method has a problem that it is not easy to control the different thickness of the first gate oxide film and the second gate oxide film. In particular, it becomes difficult to control the thickness of the first gate oxide film.
또한, 제1게이트산화막은 감광막을 제거할 때 식각손상을 받게 되어 핀홀 ( pinhole ) 과 같은 결함이 포함될 때 낮은 전기장의 스트레스에서도 작동 불량을 일으키게 되는 로우 필드 브레이크다운 ( low field breakdown ) 이 일어나는 문제점이 있는데, 이것은 게이트산화막 이전의 세정 공정에 따른 거칠기, 오염 및 웨이퍼 자체 결함 등의 영향에 크게 의존한다.In addition, when the first gate oxide film is etched when the photoresist film is removed, a low field breakdown occurs due to a malfunction caused by low electric field stress when a defect such as a pinhole is included. This is largely dependent on the effects of roughness, contamination, and defects of the wafer itself due to the cleaning process before the gate oxide film.
종래의 기술과 같이 제1 및 제2 게이트산화막을 성장시 제2게이트산화막 뿐만아니라 상대적으로 두꺼운 제1게이트산화막도 상기와 같은 결함을 포함하기 쉽게 되는데, 이것은 제1게이트산화막 제조후 제2게이트산화막을 성장시킬때까지 여러 공정들이 포함되고, 일정두께의 제1게이트산화막을 성장시킬 때 생성된 결함들이 제2 게이트산화막을 성장시킬때도 함께 성장되기 때문이다. 따라서, 소자의 특성을 열화시키고 그에 따른 소자의 고속화 및 고집적화를 어렵게 하는 문제점이 있다.As in the prior art, when the first and second gate oxide films are grown, not only the second gate oxide film but also the relatively thick first gate oxide film may easily include the above defects, which is the second gate oxide film after the first gate oxide film is manufactured. This is because a number of processes are included until the growth of the silicon oxide, and defects generated when the first gate oxide film is grown in thickness also grow when the second gate oxide film is grown. Therefore, there is a problem in that deterioration of the characteristics of the device and consequently making it difficult to speed up and integrate high.
본 발명은 상기한 종래기술의 문제점을 해결하기 위하여, 상이한 두께의 제1게이트산화막과 제2게이트산화막을 용이하게 형성하여 고집적 및 고속화용 반도체소자의 제조를 가능하게 하는 이중 게이트산화막 형성방법을 제공하는데 그 목적이 있다.The present invention provides a method of forming a double gate oxide film which enables the fabrication of highly integrated and high-speed semiconductor devices by easily forming first and second gate oxide films having different thicknesses in order to solve the problems of the prior art. Its purpose is to.
도 1a 내지 도 1d 는 본 발명의 실시예에 따른 이중 게이트산화막 형성방법을 도시한 단면도.1A to 1D are cross-sectional views illustrating a method of forming a double gate oxide film according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
1 : 반도체기판2 : 패드산화막, 제1게이트산화막1: semiconductor substrate 2: pad oxide film, first gate oxide film
3 : 패드 다결정실리콘막, 게이트전극용 제1다결정실리콘막3: pad polycrystalline silicon film, first polycrystalline silicon film for gate electrode
4 : 산화막5 : CVD 산화막4: oxide film 5: CVD oxide film
6 : 제2게이트산화막6: second gate oxide film
7 : 게이트전극용 제2다결정실리콘막7: second polycrystalline silicon film for gate electrode
10 : 감광막패턴20 : 트렌치10 photosensitive film pattern 20 trench
이상의 목적을 달성하기 위해 본 발명에 따른 이중 게이트산화막 형성방법은,In order to achieve the above object, a double gate oxide film forming method according to the present invention,
반도체기판 상부에 제1게이트절연막과 제1게이트전극용 제1도전체의 제1적층구조를 형성하는 공정과,Forming a first stacked structure of the first gate insulating film and the first conductor for the first gate electrode on the semiconductor substrate;
소자분리마스크를 이용한 식각공정으로 상기 제1적층구조 및 일정두께의 반도체기판을 식각하여 소자분리용 트렌치를 형성하는 공정과,Forming a trench for device isolation by etching the first stacked structure and the semiconductor substrate having a predetermined thickness by an etching process using an device isolation mask;
상기 트렌치 표면에 절연막을 형성하는 공정과,Forming an insulating film on the trench surface;
상기 트렌치를 매립하는 CVD 절연막을 형성하되, 상기 제1도전체보다 상대적으로 낮은 높이로 형성하는 공정과,Forming a CVD insulating film filling the trench, and forming the CVD insulating film at a relatively lower height than the first conductor;
제2게이트전극이 형성될 부분의 제1도전체와 제1게이트절연막을 식각하는 공정과,Etching the first conductor and the first gate insulating film of the portion where the second gate electrode is to be formed;
상기 반도체기판 표면에 제2게이트절연막을 성장시키고 전체표면상부에 제2게이트전극용 제2도전체를 형성하여 제2적층구조를 형성하는 공정과,Growing a second gate insulating film on the surface of the semiconductor substrate and forming a second conductor for the second gate electrode on the entire surface to form a second stacked structure;
상기 제1적층구조와 제2적층구조를 게이트전극 마스크를 이용한 식각공정으로 식각하여 제1게이트전극과 제2게이트전극을 형성하는 공정을 포함하는 것과,Etching the first stacked structure and the second stacked structure by an etching process using a gate electrode mask to form a first gate electrode and a second gate electrode;
상기 제1게이트절연막은 습식산화방법 또는 질화산화방법을 이용한 열산화공정으로 30 - 100 Å 두께 형성하는 것과,The first gate insulating film is formed by a thermal oxidation process using a wet oxidation method or a nitriding oxidation method to form a thickness of 30-100 Å,
상기 게이트전극용 제1도전체는 도프드 다결정실리콘막을 100 - 2000 Å 두께로 형성하는 것과,The first conductor for the gate electrode may be formed by forming a doped polysilicon film in a thickness of 100-2000 μs,
상기 제2게이트절연막은 습식산화방법 또는 질화산화방법을 이용한 열산화공정으로 30 - 100 Å 두께 형성하는 것과,The second gate insulating film is formed by a thermal oxidation process using a wet oxidation method or a nitriding oxidation method to form a thickness of 30-100 Å,
상기 게이트전극용 제2도전체는 도프드 다결정실리콘막을 100 - 2000 Å 두께로 형성하는 것과,The second conductor for the gate electrode may be formed by forming a doped polysilicon film in a thickness of 100-2000 μs,
상기 게이트전극용 제2도전체는 증착후 상기 제1도전체가 노출되도록 평탄화식각되는 것과,The second conductor for the gate electrode is flattened and etched to expose the first conductor after deposition;
상기 제1게이트절연막과 제2게이트절연막은 그 두께가 서로 상이한 것을 특징으로 한다.The first gate insulating film and the second gate insulating film may be different in thickness from each other.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d 는 본 발명의 실시예에 따른 이중 게이트산화막 형성방법을 도시한 단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a double gate oxide film according to an exemplary embodiment of the present invention.
먼저, 반도체기판(1)의 전체표면상부에 패드산화막(2)과 패드 다결정실리콘막(3)을 각각 일정두께 형성한다.First, a pad oxide film 2 and a pad polysilicon film 3 are respectively formed on the entire surface of the semiconductor substrate 1 at a predetermined thickness.
이때, 상기 패드산화막(2)은 후속공정에서 제1게이트산화막으로 사용되며, 패드 다결정실리콘막(3)은 게이트전극용 도전체로 사용된다.In this case, the pad oxide film 2 is used as a first gate oxide film in a subsequent process, and the pad polysilicon film 3 is used as a conductor for a gate electrode.
그리고, 상기 패드산화막(2)은 습식산화방법 또는 질화산화방법을 이용한 열산화공정으로 30 - 100 Å 정도 형성되고, 상기 패드 다결정실리콘막(3)은 도프드 다결정실리콘으로서 100 - 2000 Å 정도의 두께 형성된 것이다.The pad oxide film 2 is formed by a thermal oxidation process using a wet oxidation method or a nitriding oxidation method, and is formed in a range of about 30-100 kPa, and the pad polysilicon film 3 is a doped polycrystalline silicon of about 100-2000 kPa. It is formed thick.
그 다음에, 상기 패드 다결정실리콘막(3) 상부에 소자분리마스크(도시안됨)를 이용한 노광 및 현상공정으로 감광막패턴(10)을 형성한다.Next, the photosensitive film pattern 10 is formed on the pad polysilicon film 3 by an exposure and development process using an element isolation mask (not shown).
그리고, 상기 감광막패턴(10)을 마스크로하여 상기 패드 다결정실리콘막(3)과 패드 산화막(2) 및 일정두께의 반도체기판(1)을 식각하여 트렌치(20)를 형성한다.The pad polycrystalline silicon film 3, the pad oxide film 2, and the semiconductor substrate 1 having a predetermined thickness are etched using the photoresist pattern 10 as a mask to form a trench 20.
이때, 상기 트렌치(20)는 1000 - 5000 Å 깊이로 형성한다. (도 1a)At this time, the trench 20 is formed to a depth of 1000-5000 Å. (FIG. 1A)
그 다음에, 상기 감광막패턴(10)을 제거하고, 상기 트렌치(20) 표면을 제1열산화시켜 열산화막을 형성한 다음, 이를 HF 계열의 용액으로 제거함으로써 트렌치(20) 표면의 손상을 보상한다.Next, the photoresist pattern 10 is removed, the surface of the trench 20 is first thermally oxidized to form a thermal oxide film, and then the HF-based solution is removed to compensate for the damage to the surface of the trench 20. do.
그리고, 상기 트렌치(20) 표면을 제2열산화시켜 산화막(4)을 형성한다.The oxide film 4 is formed by second thermal oxidation of the surface of the trench 20.
그리고, 상기 트렌치(20)를 매립하는 CVD 산화막(5)을 전체표면상부에 형성하고 화학기계연마 공정으로 평탄화시킨 다음, HF 용액을 이용하여 상기 트렌치(20) 상부의 CVD 산화막(5)을 일정두께 식각한다. (도 1b)Then, the CVD oxide film 5 filling the trench 20 is formed on the entire surface and planarized by a chemical mechanical polishing process, and then the CVD oxide film 5 on the trench 20 is fixed using HF solution. Etch thickness. (FIG. 1B)
그 다음에, 제2게이트전극이 형성될 부분을 노출시키는 마스크(도시안됨)를 이용한 노광 및 현상공정으로 다른 감광막패턴(도시안됨)을 형성하고, 이를 이용하여 상기 도 1b 의 일측에 도시된 패드산화막(2)과 패드 다결정실리콘막(3)을 식각한다.Subsequently, another photoresist pattern (not shown) is formed by an exposure and development process using a mask (not shown) exposing a portion on which the second gate electrode is to be formed, and using the pad shown on one side of FIG. 1B. The oxide film 2 and the pad polysilicon film 3 are etched.
그리고, 상기 다른 감광막패턴을 제거하고, 제2게이트산화막(6)을 열산화시켜 형성하고, 그 상부에 게이트전극용 제2다결정실리콘막(7)을 형성하되, 상기 제2게이트산화막(6)과 제2다결정실리콘막(7)의 성장공정을 연속적으로 실시한다.Then, the other photoresist layer pattern is removed, and the second gate oxide layer 6 is thermally oxidized, and a second polysilicon layer 7 for gate electrode is formed thereon, and the second gate oxide layer 6 is formed. And the growth process of the second polysilicon film 7 are successively performed.
이때, 상기 제2게이트산화막(6)을 습식산화방법 또는 질화산화방법을 이용한 열산화공정에 의해 30 - 100 Å 두께의 범위내에서 상기 패드산화막(2)과 서로 상이한 두께로 형성한다. 그리고, 상기 제2다결정실리콘막(7)은 100 - 2000 Å 두께로 형성한다.At this time, the second gate oxide film 6 is formed in a thickness different from that of the pad oxide film 2 in a range of 30 to 100 mW by a thermal oxidation process using a wet oxidation method or a nitriding oxidation method. The second polysilicon film 7 is formed to a thickness of 100 to 2000 GPa.
그 다음에, 상기 제1게이트산화막(2)이 형성된 부분의 제1다결정실리콘막(3) 상부의 제2다결정실리콘막(7)이 모두 제거되도록 CMP 공정을 실시하여 평탄화시킨다. 이때, 상기 CMP 공정을 실시하지않고 상기 제1 다결정실리콘막(3) 상부에 제2다결정실리콘막(7)을 그대로 방치할 수도 있다.Thereafter, a CMP process is performed to planarize so that all of the second polysilicon film 7 on the first polycrystalline silicon film 3 in the portion where the first gate oxide film 2 is formed is removed. In this case, the second polysilicon film 7 may be left on the first polycrystalline silicon film 3 without performing the CMP process.
한편, 상기 제1게이트산화막(2)과 제2게이트산화막(6)은 그 두께를 서로 상이하게 형성한다. (도 1c)Meanwhile, the first gate oxide film 2 and the second gate oxide film 6 have different thicknesses. (FIG. 1C)
그 다음에, 게이트전극마스크(도시안됨)를 이용한 노광 및 현상공정으로 상기 제1다결정실리콘막(3)과 제2다결정실리콘막(7) 상부에 또다른 감광막패턴(도시안됨)을 형성하고 이를 마스크로하여 패터닝함으로써 이중 게이트전극을 형성한다. 그리고, 상기 또다른 감광막패턴을 제거한다. (도 1d)Next, another photoresist pattern (not shown) is formed on the first polycrystalline silicon film 3 and the second polycrystalline silicon film 7 by an exposure and development process using a gate electrode mask (not shown). The double gate electrode is formed by patterning with a mask. Then, the another photoresist pattern is removed. (FIG. 1D)
이상에서 설명한 바와같이 본 발명에 따른 이중 게이트산화막 형성방법은, 상이한 두께를 갖는 제1게이트산화막과 제2게이트산화막을 제조하기가 용이하며, 식각 손상이 전혀 없는 우수한 특성의 게이트산화막을 만들 수 있게 되어 반도체소자의 고속화 및 고집적화를 가능하게 하는 효과가 있다.As described above, the method of forming the double gate oxide film according to the present invention is easy to manufacture the first gate oxide film and the second gate oxide film having different thicknesses, and to make the gate oxide film of excellent characteristics without any etching damage. Therefore, there is an effect of enabling high speed and high integration of the semiconductor device.
Claims (5)
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| JPH03270167A (en) * | 1990-03-20 | 1991-12-02 | Sony Corp | Manufacture of semiconductor device |
| US5382532A (en) * | 1991-09-17 | 1995-01-17 | Nippon Telegraph And Telephone Corporation | Method for fabricating CMOS semiconductor devices |
| JPH07161820A (en) * | 1993-12-09 | 1995-06-23 | Sony Corp | Manufacture of semiconductor device |
| US5432114A (en) * | 1994-10-24 | 1995-07-11 | Analog Devices, Inc. | Process for integration of gate dielectric layers having different parameters in an IGFET integrated circuit |
| US5723355A (en) * | 1997-01-17 | 1998-03-03 | Programmable Microelectronics Corp. | Method to incorporate non-volatile memory and logic components into a single sub-0.3 micron fabrication process for embedded non-volatile memory |
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| JPH03270167A (en) * | 1990-03-20 | 1991-12-02 | Sony Corp | Manufacture of semiconductor device |
| US5382532A (en) * | 1991-09-17 | 1995-01-17 | Nippon Telegraph And Telephone Corporation | Method for fabricating CMOS semiconductor devices |
| JPH07161820A (en) * | 1993-12-09 | 1995-06-23 | Sony Corp | Manufacture of semiconductor device |
| US5432114A (en) * | 1994-10-24 | 1995-07-11 | Analog Devices, Inc. | Process for integration of gate dielectric layers having different parameters in an IGFET integrated circuit |
| US5723355A (en) * | 1997-01-17 | 1998-03-03 | Programmable Microelectronics Corp. | Method to incorporate non-volatile memory and logic components into a single sub-0.3 micron fabrication process for embedded non-volatile memory |
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