KR970072206A - Method of manufacturing transistor of semiconductor device - Google Patents

Method of manufacturing transistor of semiconductor device Download PDF

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Publication number
KR970072206A
KR970072206A KR1019960011718A KR19960011718A KR970072206A KR 970072206 A KR970072206 A KR 970072206A KR 1019960011718 A KR1019960011718 A KR 1019960011718A KR 19960011718 A KR19960011718 A KR 19960011718A KR 970072206 A KR970072206 A KR 970072206A
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South Korea
Prior art keywords
amorphous region
forming
heat treatment
oxide film
region
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KR1019960011718A
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Korean (ko)
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KR100217899B1 (en
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윤성렬
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김주용
현대전자산업 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen

Abstract

본 발명은 반도체 소자의 트랜지스터 제조 방법에 관한 것으로, 얕은(Shallow) 접합 영역(Junction region)을 형성하기 위하여 게이트 전극 양측부의 실리콘 기판에 비정질 영역을 형성한 후 상기 비정질 영역을 불순물 이온을 주입하여 접한 영역을 형성하므로써 이온 주입시 채널링 현상의 발생이 방지되고, 상기 비정질 영역에서 불순물 이온의 확산 속도가 저하되어 얕은 접합 영역을 형성할 수 있다. 따라서 소자의 동작시 펀치 쓰루우 현상이 발생되지 않아 소자의 신뢰성이 향상될 수 있는 반도체 소자의 트랜지스터 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a transistor of a semiconductor device, in which an amorphous region is formed in a silicon substrate on both sides of a gate electrode in order to form a shallow junction region, and then the amorphous region is implanted with impurity ions The channeling phenomenon can be prevented from occurring during the ion implantation and the diffusion rate of the impurity ions in the amorphous region can be reduced to form a shallow junction region. Thus, the punch-through phenomenon does not occur during operation of the device, and reliability of the device can be improved.

Description

반도체 소자의 트랜지스터 제조 방법Method of manufacturing transistor of semiconductor device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제1A도 내지 제1E도는 본 발명의 제1실시예를 설명하기 위한 소자의 단면도.1A to 1E are sectional views of a device for explaining a first embodiment of the present invention.

Claims (15)

반도체 소자의 트랜지스터 제조 방법에 있어서, 실리콘 기판상에 게이트 산화막 및 폴리실리콘층을 순차적으로 형성한 후 상기 폴리실리콘층 및 게이트 산화막을 순차적으로 패터닝하여 게이트 전극을 형성하는 단계와, 상기 단계로부터 전체 상부면에 산화막을 형성한 후상기 게이트 전극 양측부의 상기 실리콘 기판에 비정질 영역을 형성하는 단계와, 상기 단계로부터 상기비정질 영역의 깊이를 증가시키기 위하여 저온에서 1차 열처리하는 단계와, 상기 단계로부터 상기 비정질 영역의 상부에 불순물 이온을 주입하여 접합 영역을 형성하는 단계와, 상기 단계로부터 상기 주입된 불순물 이온을 활성화시키기 위해 고온에서 2차 열처리하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의트랜지스터 제조 방법.A method of manufacturing a transistor of a semiconductor device, comprising: sequentially forming a gate oxide film and a polysilicon layer on a silicon substrate; sequentially patterning the polysilicon layer and the gate oxide film to form a gate electrode; Forming an amorphous region in the silicon substrate on both sides of the gate electrode after forming an oxide film on the surface of the amorphous region; and performing a first heat treatment at a low temperature to increase the depth of the amorphous region from the step, Forming a junction region by implanting impurity ions into an upper portion of the semiconductor substrate; and performing a second heat treatment at a high temperature to activate the implanted impurity ions from the step. 제1항에 있어서, 상기 산화막은 100 내지 200A의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.The method of claim 1, wherein the oxide layer is formed to a thickness of 100 to 200A. 제1항에 있어서, 상기 비정질 영역은 실리콘 이온 주입에 의해 형성되는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.The method of claim 1, wherein the amorphous region is formed by implanting silicon ions. 제1 또는 제3항에 있어서, 상기 비정질 영역은 0.15 내지 0.2㎛의 깊이로 형성되는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.The method of claim 1 or 3, wherein the amorphous region is formed to a depth of 0.15 to 0.2 탆. 제1항에 있어스 상기 1차 열처리는 상기 비정질 영역의 깊이가 0.25 내지 0.3㎛로 증가되는 시점까지 실시되는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.The method of claim 1, wherein the first heat treatment is performed until a depth of the amorphous region is increased to 0.25 to 0.3 탆. 제1 또는 제5항에 있어서, 상기 1차 열처리는 400내지 600℃의 온도에서 80 내지 100분동안 실시되는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.The method of claim 1 or 5, wherein the first heat treatment is performed at a temperature of 400 to 600 DEG C for 80 to 100 minutes. 제1항에 있어서, 상기 불순물 이온은 붕소인 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.The method of claim 1, wherein the impurity ion is boron. 제1항에 있어서, 상기 2차 열처리는 950 내지 1100℃의 온도에서 5 내지 15초동안 실시되는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.The method of claim 1, wherein the second heat treatment is performed at a temperature of 950 to 1100 캜 for 5 to 15 seconds. 반도체 소자의 트랜지스터 제조 방법에 있어서, 실리콘 기판상에 게이트 산화막 및 폴리실리콘층을 순차적으로 형성한 후 상기 폴리실리콘 층 및 게이트 산화막을 순차적으로 패터닝하여 게이트 전극을 형성한는 단계와, 상기 단계로부터 전체 상부면에 산화막을 형성한 후 상기 게이트 전극 양측부의 상기 실리콘 기판에 비정질 영역을 형성하는 단계와, 상기 단계로부터 상기 비정질 영역에 불순물 이온을 주입하여 접합영역을 형성하는 단계와, 상기 단계로부터 상기 주입된 불순물 이온을 활성화시키기 위하여 고온에서 열처리하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.A method of manufacturing a transistor of a semiconductor device, comprising: sequentially forming a gate oxide film and a polysilicon layer on a silicon substrate, sequentially patterning the polysilicon layer and a gate oxide film to form a gate electrode; Forming an amorphous region in the silicon substrate on both sides of the gate electrode after forming an oxide film on the amorphous region; implanting impurity ions into the amorphous region from the step to form a junction region; And heat treating the semiconductor substrate at a high temperature to activate the impurity ions. 제9항에 있어서, 상기 산화막은 100 내지 200A의 두께로 형성되는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.10. The method of claim 9, wherein the oxide layer is formed to a thickness of 100 to 200A. 제9항에 있어서, 상기 비정질 영역은 BF2이온 주입에 의해 형성되는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.The method of claim 9 wherein the transistor manufacturing method of the semiconductor device which is characterized in that the amorphous regions are formed by BF 2 ion implantation. 제11항에 있어서, 상기 BF2이온 주입시 이온 주입 에너지 60 내지 80KeV이며, 도즈 량은 2.0E15 내지 4.0E15 퀀텀/㎠인 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.12. The method of claim 11, wherein the BF 2 ion implantation energy is 60 to 80 KeV and the dose amount is 2.0E15 to 4.0E15 quantum / cm 2. 제9 또는 제11항에 있어서, 상기 비정질 영역은 0.15 내지 0.2㎛의 깊이로 형성되는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.The method of claim 9 or 11, wherein the amorphous region is formed to a depth of 0.15 to 0.2 탆. 제9항에 있어서, 상기 불순물 이온은 붕소인 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.10. The method of claim 9, wherein the impurity ion is boron. 제9항에 있어서, 상기 열처리는 950 내지 1100℃의 온도에서 5 내지 15초동안 실시되는 것을 특징으로 하는 반도체 소자의 트랜지스터 제조 방법.10. The method of claim 9, wherein the heat treatment is performed at a temperature of 950 to 1100 DEG C for 5 to 15 seconds. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: It is disclosed by the contents of the first application.
KR1019960011718A 1996-04-18 1996-04-18 Method of manufacturing transistor of semiconductor device KR100217899B1 (en)

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KR100217899B1 KR100217899B1 (en) 1999-09-01

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100232206B1 (en) * 1996-12-26 1999-12-01 김영환 Method of manufacturing semiconductor device
KR100251989B1 (en) * 1996-12-30 2000-04-15 김영환 Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100232206B1 (en) * 1996-12-26 1999-12-01 김영환 Method of manufacturing semiconductor device
KR100251989B1 (en) * 1996-12-30 2000-04-15 김영환 Method for manufacturing semiconductor device

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