JPS6211278A - Vertical field effect transistor - Google Patents
Vertical field effect transistorInfo
- Publication number
- JPS6211278A JPS6211278A JP60150394A JP15039485A JPS6211278A JP S6211278 A JPS6211278 A JP S6211278A JP 60150394 A JP60150394 A JP 60150394A JP 15039485 A JP15039485 A JP 15039485A JP S6211278 A JPS6211278 A JP S6211278A
- Authority
- JP
- Japan
- Prior art keywords
- type
- field effect
- effect transistor
- vertical field
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims description 18
- 239000000758 substrate Substances 0.000 abstract description 12
- 230000003071 parasitic effect Effects 0.000 abstract description 8
- 230000002457 bidirectional effect Effects 0.000 abstract description 6
- 230000000694 effects Effects 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 239000012535 impurity Substances 0.000 description 16
- 239000010410 layer Substances 0.000 description 15
- 239000004065 semiconductor Substances 0.000 description 7
- 239000008188 pellet Substances 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
- H01L29/7808—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a breakdown diode, e.g. Zener diode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は縦型電界効果トランジスタに関し、特にゲート
・ソース間に、ゲート保護用のツェナーダイオードを含
む縦型電界効果トランジスタに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a vertical field effect transistor, and more particularly to a vertical field effect transistor including a Zener diode for gate protection between the gate and the source.
従来、縦型電界効果トランジスタの保護ダイオードは、
１ペレ、ト（下層ペレット）上に形成しようとしていた
ため、ゲート・ソース間に寄生ＰＮＰＮサイリスタを形
成するという問題を持っていた。Traditionally, the protection diode of a vertical field effect transistor is
Since it was intended to be formed on one pellet (lower layer pellet), there was a problem in that a parasitic PNPN thyristor was formed between the gate and source.
従来、保護ダイオードを含む縦型電界効果トランジスタ
は第２図に示すように１ペレ、ト（下層ペレット）上に
形成していた。Conventionally, a vertical field effect transistor including a protection diode has been formed on one pellet (lower layer pellet) as shown in FIG.
すなわち、ソース電極９と多結晶シリコンゲート電極８
（アルミニウムゲート電極１０）とドレイン電極１１を
もつ縦型電界効果トランジスタと電極９と電極１０の間
の領域（６，（４）、５．７）により形成される双方向
ツェナー・ダイオードが同一基板上に形成され、ソース
およびゲート電極間にツェナー・ダイオードが挿入され
るよう接続されて構成されていた。That is, the source electrode 9 and the polycrystalline silicon gate electrode 8
A vertical field effect transistor with (aluminum gate electrode 10) and drain electrode 11 and a bidirectional Zener diode formed by the region (6, (4), 5.7) between electrodes 9 and 10 are mounted on the same substrate. A Zener diode was connected between the source and gate electrodes.
上述したように従来の保護ダイオードとして双方向ツェ
ナー・ダイオードを１ペレツト上に一緒に形成した縦型
電界効果トランジスタでは今半導体基板と導電型をｐ型
とすると、ゲー）１０とノース９の間に、Ａの経路すな
わちｐ型不純物領域２、Ｎ型基板１、ｐ型不純物領域４
、Ｎ型不純物領域５、ｐ型不純物領域７に寄生ＰＮＰＮ
Ｐのサイリスタが形成され、サイリスタがオンしてしま
うという問題が発生する。As mentioned above, in a conventional vertical field effect transistor in which a bidirectional Zener diode is formed on one pellet as a protection diode, if the semiconductor substrate and the conductivity type are p-type, there is a gap between gate) 10 and north 9. , A path, that is, p-type impurity region 2, N-type substrate 1, p-type impurity region 4
, parasitic PNPN in the N-type impurity region 5 and the p-type impurity region 7.
A problem arises in that a thyristor P is formed and the thyristor turns on.
本発明は上述した従来の欠点を除去し、寄生サイリスタ
扇果のない保護ダイオード（双方向ツーナー・ダイオー
ド）を持つ縦型電界効果トランジスタを提供することに
ある。The present invention obviates the above-mentioned drawbacks of the prior art and provides a vertical field effect transistor with a protection diode (bidirectional Zuner diode) without parasitic thyristor fans.
本発明の縦型電界効果トランジスタは、表面にソース及
びゲート、裏面にドレインを持つ縦型電界効果トランジ
スタにおいて、縦型電界効果トランジスタを形成した下
層素子表面のソース及びゲートＷ極間に別に形成したツ
ェナー・ダイオードの上層素子を接続一体化することに
より構成される。The vertical field effect transistor of the present invention is a vertical field effect transistor having a source and a gate on the front surface and a drain on the back surface, in which the vertical field effect transistor is formed separately between the source and gate W poles on the surface of the lower layer element on which the vertical field effect transistor is formed. It is constructed by connecting and integrating the upper layer elements of a Zener diode.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例の断面図である。本実施例に
おいてはｎチャンネルＭＯ８ＦＥＴについて説明する。FIG. 1 is a sectional view of an embodiment of the present invention. In this embodiment, an n-channel MO8FET will be explained.
第１図において、ｎ型半導体基板１にｐ型の不純物領域
２を形成し、さらにｐ型不純物領域２内にｎ型のか←の
不純物領域３を形成し、更に多結晶シリコンゲート電極
８を形成し、ｎ型不純物領域３をソースとし、裏面１１
をドレイン電極とするｎチャンネルＭＯ８ＦＥＴを形成
し下層素子とする。下層素子において９はソース電極、
１０はゲート電極である。In FIG. 1, a p-type impurity region 2 is formed in an n-type semiconductor substrate 1, an n-type impurity region 3 is further formed within the p-type impurity region 2, and a polycrystalline silicon gate electrode 8 is further formed. The n-type impurity region 3 is used as a source, and the back surface 11 is
An n-channel MO8FET with the drain electrode as the lower layer element is formed. In the lower layer element, 9 is a source electrode;
10 is a gate electrode.
一方、上層素子としては、下層素子の半導体基板１と逆
導電型のｐ型半導体基板４を準備し、半導体基板内にｎ
型不純物領域５、引続きｐ型不純物領域６及び７を形成
する。しかるときは電極９゜１０を両極とするｐｎｐ双
方向ツェナー・ダイオ−が形成できる。On the other hand, for the upper layer element, a p-type semiconductor substrate 4 of the opposite conductivity type to the semiconductor substrate 1 of the lower layer element is prepared, and an n
Type impurity region 5 and subsequently p-type impurity regions 6 and 7 are formed. In this case, a pnp bidirectional Zener diode can be formed with electrodes 9 and 10 serving as both poles.
そしてツェナー・ダイオードの電極９，１ｏをｎチャン
ネルＭＯ８ＦＥＴのソース電極９、ゲート電極１０と接
続すれば本実施例°は完成する。The present embodiment is completed by connecting the electrodes 9 and 1o of the Zener diode to the source electrode 9 and gate electrode 10 of the n-channel MO8FET.
接続にあたっては上下層の素子を平坦化し、接 。For connection, the elements in the upper and lower layers are flattened and connected.
続部分を露出させる表面平坦化プロセス及び上下層の接
続部分の位置を目合せし、重ね合わせて熱圧着すること
により接続することにより下層素子のｎチャンネルＭＯ
８ＦＥＴのソースとゲート間にチェナー・ダイオードを
接続した一体化されたツェナーダイオードをゲート保護
ダイオードとするｎチャンネルＭＯ８ＦＥＴを得ること
ができる。The n-channel MO of the lower layer element is formed by a surface flattening process that exposes the connecting part, and by aligning the positions of the connecting parts of the upper and lower layers, overlapping them, and connecting them by thermocompression bonding.
An n-channel MO8FET can be obtained in which a Zener diode is connected between the source and gate of the 8FET and an integrated Zener diode is used as a gate protection diode.
このような構造にすることにより本実施例のｎチャンネ
ルＭＯ８ＦＥＴにおいては寄生サイリスタの存在を消滅
させることができる。By adopting such a structure, the existence of a parasitic thyristor can be eliminated in the n-channel MO8FET of this embodiment.
以上説明したように本発明は、下層素子に縦型電界効果
トランジスタ、上層素子に相方向ツェナー・ダイオード
を形成し、上部・下部のコンタクトを取ることにより、
寄生サイスリタ効果のない保護ダイオード（双方向ツェ
ナー・ダイオード）を持つ縦型電界効果トランジスタを
形成することができる。As explained above, the present invention forms a vertical field effect transistor in the lower layer element, a phase direction Zener diode in the upper layer element, and makes upper and lower contacts.
It is possible to form a vertical field effect transistor with a protection diode (bidirectional Zener diode) without parasitic cisitor effects.
第１図は本発明の一実施例の断面図、第２図は従来のツ
ェナー・ダイオードをゲート保護ダイオードとする縦型
電界効果トランジスタの一例の断面図である。
１−・・・・・−導電型の半導体基板（ｎ型半導体基板
）、２・・・・・・基板と逆導電型の不純物領域（ｐ型
不純物領域）、３・・・・・・ｎ型不純物領域、４・・
・・・・ｐ型半導体基板、５・・・・・・ｎ型不純物領
域、６・・・・・・ｐ型不純物領域、７・・・・・・ｐ
型不純物領域、８・・・・・・多結晶シリコンゲート電
極、９・・・・・・ソース電極（ツェナー・ダイオード
の電極）、１０・・・・・・ゲート電極（ツェナー・ダ
イオードの電極）、１１・・・・・・ドレイン電極、１
２・・・・・・層間絶縁膜、１３・・・・・・ゲート電
極、１４・・・・・・Ｉ−間絶縁膜、Ａ・・・・・・寄
生サイリスタの経路、■・・・・・・下層素子、■・・
・・・・上層素子。
代理人 弁理士 内 原 皿′−゛＼町＼−゛
又−一−１・FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a sectional view of an example of a vertical field effect transistor using a conventional Zener diode as a gate protection diode. 1-...-conductivity type semiconductor substrate (n-type semiconductor substrate), 2...... impurity region of opposite conductivity type to the substrate (p-type impurity region), 3......n Type impurity region, 4...
... p-type semiconductor substrate, 5 ... n-type impurity region, 6 ... p-type impurity region, 7 ... p
type impurity region, 8... polycrystalline silicon gate electrode, 9... source electrode (electrode of Zener diode), 10... gate electrode (electrode of Zener diode) , 11...Drain electrode, 1
2...Interlayer insulating film, 13...Gate electrode, 14...I-interlayer insulating film, A...Path of parasitic thyristor, ■... ... lower layer element, ■...
...Upper layer element. Agent Patent Attorney Uchihara Sara'-゛\Machi\-゛Mata-1-1・
Claims (1)
効果トランジスタにおいて、縦型電界効果トランジスタ
を形成した下層素子表面のソース及びゲート電極間に別
に形成したツェナーダイオードの上層素子を接続一体化
したことを特徴とする縦型電界効果トランジスタ。In a vertical field effect transistor having a source on the front surface and a drain on the rear surface of the gate, an upper layer element of a Zener diode formed separately is connected and integrated between the source and gate electrodes on the surface of the lower layer element forming the vertical field effect transistor. Characteristics of vertical field effect transistors.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60150394A JPH0680833B2 (en) | 1985-07-08 | 1985-07-08 | Vertical field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60150394A JPH0680833B2 (en) | 1985-07-08 | 1985-07-08 | Vertical field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6211278A true JPS6211278A (en) | 1987-01-20 |
| JPH0680833B2 JPH0680833B2 (en) | 1994-10-12 |
Family
ID=15496026
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60150394A Expired - Lifetime JPH0680833B2 (en) | 1985-07-08 | 1985-07-08 | Vertical field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0680833B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0218968A (en) * | 1988-07-06 | 1990-01-23 | Nec Corp | Vertical mos field effect transistor |
| US4982266A (en) * | 1987-12-23 | 1991-01-01 | Texas Instruments Incorporated | Integrated circuit with metal interconnecting layers above and below active circuitry |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5825264A (en) * | 1981-08-07 | 1983-02-15 | Hitachi Ltd | Insulated gate type semiconductor device and manufacture thereof |
-
1985
- 1985-07-08 JP JP60150394A patent/JPH0680833B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5825264A (en) * | 1981-08-07 | 1983-02-15 | Hitachi Ltd | Insulated gate type semiconductor device and manufacture thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4982266A (en) * | 1987-12-23 | 1991-01-01 | Texas Instruments Incorporated | Integrated circuit with metal interconnecting layers above and below active circuitry |
| JPH0218968A (en) * | 1988-07-06 | 1990-01-23 | Nec Corp | Vertical mos field effect transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0680833B2 (en) | 1994-10-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |