JPS58194365A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable to take out electric potential of a substrate without increasing any process by a method wherein an electrode region having the parts to make contact between an outside electrode taking out metal formed on the surface of a semiconductor substrate and diffusion regions, and being the same conductive type with said semiconductor substrate in accordance with the junction between the aforementioned metal and the semiconductor substrate is provided to function as the substrate electric potential control electrode. CONSTITUTION:At the MOS transistors formed at both the edge parts A, B of a poly-silicon mask 1 by using mask construction formed by stacking a diffusion mask 2, a contact mask 3 and an aluminum electrode mask 4, an aluminum- silicon alloy grows in both the depth direction and the lateral direction of the substrate 17 at the boundary faces between the N type diffusion regions 12, 13 and the poly-silicon gate 11, and the grown aluminum-silicon alloy parts 15, 16 enable to attain connection between the P type substrate 17.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a substrate electrode can be taken out from the surface of the substrate.

Conventionally, the N-channel MO8-C is connected to an external power source using a dedicated process of forming predetermined external electrodes for direct connection from the surface of the chip to the substrate in order to control the substrate potential. On the other hand, in a device that does not use this dedicated process, it is necessary to simply supply the substrate potential only from the back surface of the substrate.

By the way, in conventional semiconductor devices && K rα
Forming electrodes by employing a dedicated process for connecting and connecting leads to an increase in manufacturing time due to the increase in the number of processes, a decrease in yield due to the complexity of the manufacturing method, and an increase in costs. On the other hand, when the substrate potential is supplied from the surface, trouble occurs due to floating of the substrate potential during a one-wafer test. 2. In order to establish ohmic contact between the silicon chip and the back cage, it is necessary to deposit gold on the package and the back of the chip.

There are many disadvantages such as increased costs and variations in substrate potential due to the difficulty of uniformly bonding the three chips to the package over the entire back surface of the chip.

The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to provide a semiconductor device from which the substrate potential can be taken out without increasing the number of steps.

The present invention will be explained below based on the drawings. Figure 1 shows N
This is a top view of a channel MOS device, showing a mask configuration (mask layout) for connecting electrodes to a substrate. In this layout, diffusion masks 2. By overlapping the contact mask 3 and the aluminum electrode mask 4,
The MOS transistor formed using these mask configurations has an a-a cross-sectional view shown in FIG.
The aluminum of the external electrode aluminum 14 formed covering the source and drain regions 12 and 13 at the interface with the ends of the N-type diffusion regions becomes alloyed with the underlying silicon, thereby forming the N-type diffusion regions 12 and 13. Beyond the alloy region 15.
16 is formed. That is, the N type diffusion region 12,
13 and the polysilicon gate 11, an aluminum-silicon alloy grows both in the depth direction and the lateral direction of the substrate 17, and the grown aluminum-silicon alloy parts 15 and 16 form the P-type substrate 17. connection. To explain in detail, in the contact area between the aluminum 14 and the source-drain 'BIJH2t13 of the substrate 17, the aluminum 14 is alloyed with silicon, and P
Although it becomes a shadow region, since the source/drain regions 12 and 13 are heavily doped with N-type impurities, the contact portion remains N-type. However, at the ends A and B, the source/drain y region 12
, 13 coincide with the ends A and B, the aluminum 14 is diffused toward the substrate 17 side, and the P shadow area 12° 13
will be formed. On the other hand, at the ends C and D, the diffusion mask 2 is larger than the contact mask 3, so the end A
, a P shadow area like that shown in B is not formed.

As described above, the P shadow area 12.13 allows the substrate 17 to
It becomes possible to take out the connector from the surface of the substrate 17.

In FIG. 2, 1B and 19.20 are a gate oxide film, a field oxide film 9, and a surface oxide film, respectively.

Figure 3 shows the aluminum 4 on the chip surface and the roofing plate.
1. In this figure, the same numbers as in FIG. 1 indicate the same parts.

Generally, according to the structure according to the present invention, the larger the interface between the edge of the polysilicon and the edge of the diffused portion, the better the connection and the more stable the substrate potential.

As is clear from the explanation below, the semiconductor device according to the present invention has problems in forming the substrate potential supply electrode, such as complication of the process, urchin last trouble, and increased cost, as seen in conventional cutting. can be easily resolved.

[Brief explanation of the drawing]

FIG. 1 is a basic mask layout diagram of the present invention. FIG. 2 is a sectional view of a semiconductor device of the present invention. FIG. 3 is a mask layout diagram when the present invention is applied to a chip layout. 11...0 Polysilicon gate, 12.13...
...N-type diffusion region, 14... Aluminum electrode part, 1s, 1e, 11ro...-aluminum.
Silicon alloy region, 17...P-type substrate, 18.
...Gate oxide film, 19...Field oxide film, 20...Surface oxide layer. 292-

Claims (1)

[Claims] A metal for taking out external electrodes formed on the surface of the semiconductor substrate,
an electrode having a diffusion region formed on the surface of the semiconductor substrate and a contact portion for making contact between the diffusion region and the metal, and having the same temple shape as the semiconductor substrate and made of an alloy of the metal and the semiconducting substrate; A semiconductor device characterized in that a region is provided and the electrode region is used as a substrate potential control electrode.