JPH0462874A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH0462874A JPH0462874A JP16622890A JP16622890A JPH0462874A JP H0462874 A JPH0462874 A JP H0462874A JP 16622890 A JP16622890 A JP 16622890A JP 16622890 A JP16622890 A JP 16622890A JP H0462874 A JPH0462874 A JP H0462874A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- isolation oxide
- gate
- gate electrode
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000002955 isolation Methods 0.000 claims abstract description 37
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 abstract description 4
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- 229920005591 polysilicon Polymers 0.000 abstract description 4
- 238000005530 etching Methods 0.000 abstract description 3
- 239000004642 Polyimide Substances 0.000 abstract description 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＭＯ３型半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to an MO3 type semiconductor device.
本発明はＭＯ３型高耐圧半導体装置のゲート電極の表面
と、素子分離用酸化膜の表面とを平坦化して形成したた
め、従来ゲート電極形成時に生じたマスクずれによる特
性の変動を抑制することを可能としたものである。In the present invention, since the surface of the gate electrode of the MO3 type high voltage semiconductor device and the surface of the oxide film for element isolation are flattened, it is possible to suppress the variation in characteristics due to mask misalignment that conventionally occurs when forming the gate electrode. That is.
従来、第２図に示したように、半導体基板１表面付近に
素子分離用酸化膜２を選択的に設け、素子分離用酸化膜
２に囲まれた領域にゲート酸化膜３を設け、ゲート酸化
膜３を介して素子分離用酸化膜２上の一部にまで延在す
るゲート電極４を設け、ゲート酸化膜３に隣接する素子
分離用酸化膜３のチャネル長方向の外側に隣接するソー
ス５、ドレイン６を設け、ゲート酸化膜３とソース５に
挟まれた素子分離用酸化膜２の下側とゲート酸化膜３と
ドレイン６に挟まれた素子分離用酸化膜２の下側にソー
ス５、ドレイン６と同しＲ電型の不純物拡散領域７を設
けることにより半導体装置を形成していた。Conventionally, as shown in FIG. 2, an element isolation oxide film 2 is selectively provided near the surface of a semiconductor substrate 1, a gate oxide film 3 is provided in a region surrounded by the element isolation oxide film 2, and gate oxide film 3 is provided in a region surrounded by the element isolation oxide film 2. A gate electrode 4 extending to a part of the element isolation oxide film 2 via the film 3 is provided, and a source 5 adjacent to the outside in the channel length direction of the element isolation oxide film 3 adjacent to the gate oxide film 3 is provided. , a drain 6 is provided below the element isolation oxide film 2 sandwiched between the gate oxide film 3 and the source 5, and on the lower side of the element isolation oxide film 2 sandwiched between the gate oxide film 3 and the drain 6. , a semiconductor device was formed by providing an impurity diffusion region 7 of the same R type as the drain 6.
しかし、従来の技術ではゲート電極と素子分離用酸化膜
とのアライメントずれによる特性の変動という問題点を
有していた。However, the conventional technology has had the problem of variations in characteristics due to misalignment between the gate electrode and the element isolation oxide film.
以上に述べた問題点を解決するために、本発明では、ゲ
ート電極の表面と素子分離用酸化膜の表面とを平坦化し
て形成した。In order to solve the above-mentioned problems, in the present invention, the surface of the gate electrode and the surface of the element isolation oxide film are formed by planarizing them.
」１記のごとく形成された半導体装置は、ゲート電極と
選択的に形成する素子分離用酸化膜とがセルフアライメ
ント的に形成できる。In the semiconductor device formed as described in 1 above, the gate electrode and the selectively formed element isolation oxide film can be formed in a self-aligned manner.
したがって、高面１圧トランジスタのオン抵抗および面
］圧を安定させることを可能とした。Therefore, it is possible to stabilize the on-resistance and surface pressure of the high-surface single-voltage transistor.
本発明の実施例を図面に基づいて詳細に説明する。第１
図は本発明の高１１ｉｉ（圧ＭＯ３型半導体装置の一実
施例をＮヂャネル型を例にとってチャネル長方向の断面
図を示したものである。Ｐ型半導体基板１表面付近に素
子分離用酸化膜２を選択的に形成し、素子分離用酸化膜
２に囲まれた領域にゲート酸化膜３を形成し、素子分離
用酸化膜２に囲まれた領域にゲート酸化膜３を介して表
面が素子分離用酸化膜２と平坦にゲート電極４を形成す
る。Embodiments of the present invention will be described in detail based on the drawings. 1st
The figure shows a cross-sectional view in the channel length direction of an embodiment of the high 11ii (pressure MO3) type semiconductor device of the present invention, taking an N channel type as an example. 2 is selectively formed, a gate oxide film 3 is formed in a region surrounded by the oxide film 2 for element isolation, and a gate oxide film 3 is formed in the region surrounded by the oxide film 2 for element isolation so that the surface of the element A gate electrode 4 is formed flat with the isolation oxide film 2.
こごで、ゲート電極４は素子分離用酸化膜２とゲート酸
化膜３との段差より厚く例えばｎ型ポリシリコンを堆積
し、ｎ型ポリシリコン上に例えばフォトレジスト、ポリ
イミド等を平坦に堆積し、エツチング選択比を１対１で
素子分離用酸化膜２表面までエッチハックすることによ
り形成される。Here, the gate electrode 4 is made by depositing, for example, n-type polysilicon thicker than the step difference between the element isolation oxide film 2 and the gate oxide film 3, and depositing, for example, photoresist, polyimide, etc., flatly on the n-type polysilicon. , is formed by etching down to the surface of the element isolation oxide film 2 at an etching selectivity of 1:1.
次に、ゲート酸化膜３に隣接する素子分離用酸化膜２の
チャネル長方向の外側に隣接するｎ型のソース５、ドレ
イン６を形成し、ゲート酸化膜３とソース５に挟まれた
素子分離用酸化膜２の下側とゲート酸化膜２とドレイン
６に挟まれた素子分離用酸化膜２の下側にｎ型不純物拡
散領域７を形成する。このあとは図示しないが５ｖ系ト
ランジスタ領域にゲート電極、ソース、ドレインを形成
し、全面に中間層を堆積し、選択的にコンタクトホール
を形成し、必要な配線層を形成し、保護を形成して完成
する。Next, an n-type source 5 and drain 6 are formed adjacent to the outside in the channel length direction of the device isolation oxide film 2 adjacent to the gate oxide film 3, and the device isolation sandwiched between the gate oxide film 3 and the source 5 is formed. An n-type impurity diffusion region 7 is formed under the element isolation oxide film 2 and between the gate oxide film 2 and the drain 6. After this, although not shown, a gate electrode, source, and drain are formed in the 5V transistor region, an intermediate layer is deposited on the entire surface, contact holes are selectively formed, necessary wiring layers are formed, and protection is formed. and complete it.
「発明の効果〕
以」二詳細に説明した本発明の半導体装置は、ゲート電
極と素子分離用酸化膜をセルフアライメントに形成した
ため、”７スクずれによるオン抵抗および耐圧の特性を
安定させることができる。``Effects of the Invention'' In the semiconductor device of the present invention described in detail below, since the gate electrode and the element isolation oxide film are formed in self-alignment, it is possible to stabilize the on-resistance and withstand voltage characteristics caused by ``7'' misalignment. can.
第１図は本発明のＭＯ３型半導体装置のチャネル長方向
断面図の一例、第２図は従来のＭＯ３型半導体装置のチ
ャネル長方向断面図である。
１・・・Ｐ型半導体基板
２・・・素子分離用酸化膜
３・ 、ゲート酸化膜
４・・・ゲート電極
５・・・ソース
６・・・ドレイン
７・・・ｎ型不純物拡散領域
以上FIG. 1 is an example of a sectional view in the channel length direction of an MO3 type semiconductor device of the present invention, and FIG. 2 is a sectional view in the channel length direction of a conventional MO3 type semiconductor device. 1... P-type semiconductor substrate 2... Element isolation oxide film 3, Gate oxide film 4... Gate electrode 5... Source 6... Drain 7... N-type impurity diffusion region or above
Claims (1)
酸化膜を設け、前記素子分離用酸化膜に囲まれた領域に
ゲート酸化膜を設け、前記素子分離用酸化膜に囲まれた
領域に前記ゲート酸化膜を介して表面が前記素子分離用
酸化膜と平坦にゲート電極を設け、前記ゲート酸化膜に
隣接する前記素子分離用酸化膜のチャネル長方向の外側
に隣接するソース・ドレインを設け、前記ゲート酸化膜
と前記ソースに挟まれた前記素子分離用酸化膜の下側と
前記ゲート酸化膜と前記ドレインに挟まれた前記素子分
離用酸化膜の下側に第２導電型の不純物拡散領域を設け
たことを特徴とする半導体装置。A device isolation oxide film is selectively provided near the surface of a first conductivity type semiconductor substrate, a gate oxide film is provided in a region surrounded by the device isolation oxide film, and a gate oxide film is provided in a region surrounded by the device isolation oxide film. A gate electrode is provided whose surface is flat with the element isolation oxide film through the gate oxide film, and a source/drain is provided adjacent to the outer side in the channel length direction of the element isolation oxide film adjacent to the gate oxide film. , a second conductivity type impurity is diffused into the lower side of the element isolation oxide film sandwiched between the gate oxide film and the source, and the lower side of the element isolation oxide film sandwiched between the gate oxide film and the drain. A semiconductor device characterized by providing a region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16622890A JPH0462874A (en) | 1990-06-25 | 1990-06-25 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16622890A JPH0462874A (en) | 1990-06-25 | 1990-06-25 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0462874A true JPH0462874A (en) | 1992-02-27 |
Family
ID=15827489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16622890A Pending JPH0462874A (en) | 1990-06-25 | 1990-06-25 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0462874A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07142708A (en) * | 1993-06-21 | 1995-06-02 | Nec Corp | Semiconductor device and its manufacture |
| US6103574A (en) * | 1998-07-21 | 2000-08-15 | Nec Corporation | Method of manufacturing non-volatile semiconductor memory device having reduced electrical resistance of a source diffusion layer |
| US6917076B2 (en) | 1996-05-28 | 2005-07-12 | United Microelectronics Corporation | Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device |
-
1990
- 1990-06-25 JP JP16622890A patent/JPH0462874A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07142708A (en) * | 1993-06-21 | 1995-06-02 | Nec Corp | Semiconductor device and its manufacture |
| US6917076B2 (en) | 1996-05-28 | 2005-07-12 | United Microelectronics Corporation | Semiconductor device, a method of manufacturing the semiconductor device and a method of deleting information from the semiconductor device |
| US6103574A (en) * | 1998-07-21 | 2000-08-15 | Nec Corporation | Method of manufacturing non-volatile semiconductor memory device having reduced electrical resistance of a source diffusion layer |
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