JPH0669512A - Semiconductor device - Google Patents

Abstract

PURPOSE:To increase the bonding width of a diode element for gate protection without increasing the external size of a semiconductor substrate (a semiconductor chip) and to enhance a protective effect in a semiconductor device wherein a vertical-type MISFET (a power transistor) and the diode element, for gate protection, connected to a gate electrode for the vertical-type MISFET are provided. CONSTITUTION:A semiconductor device is provided with a vertical-type MISFET and with a diode element, for gate protection, connected to a gate electrode for the vertical MISFET. In the semiconductor device, the diode element for gate protection is formed on the gate electrode 4 for the vertical-type MISFET by interposing an interlayer insulating film 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a single structure having a vertical MISFET and a gate protection diode element connected to the gate electrode of the vertical MISFET. It relates to effective technology.

[0002]

2. Description of the Related Art A vertical MOSFET, this vertical MOSFE
A semiconductor device having a single structure (power MOS device) having gate protection diode elements connected to the gate electrode of T
In the FET, the gate protection diode element is designed in consideration of the following three items.

(1) It is formed in a thin film such as a polycrystalline silicon film.

(2) The withstand voltage is secured by the number of gate protection die-auto elements connected in series. For example, in the present situation, one series in which gate protection diode elements are connected in series is 7.
Connect 2 rows set to 5 [V] in series to 22.5 rows.
The withstand voltage of [V] is secured.

(3) A diode element for gate protection is formed on the gate pad to suppress an increase in chip size.

Regarding the semiconductor device having the single structure, for example, I. Yoshida et. al; "Novel Gate-pro
tection Devices for MOSFETs "Proc of the 1
4th Cconf. (1982 Alternative) on Solid Sta
te Devices, Tokyo, 1982. PP. 81-84.

[0007]

The present inventor has found the following problems as a result of examining the above-mentioned semiconductor device having a single structure.

That is, since the gate protection diode element connected to the gate electrode of the vertical MOSFET is formed on the gate pad, the junction width W is small and the resistance at breakdown is large. Therefore, the clamp effect is small and the protection effect is limited.

If the diode element for gate protection is formed in the peripheral region of the semiconductor chip, the junction width W can be increased, but the outer size of the semiconductor chip is also increased.

An object of the present invention is to provide a technique capable of increasing the junction width W of the gate protection diode element and improving the protection effect without increasing the outer size of the semiconductor chip.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the vertical MISFET, the vertical M
In the semiconductor device having each of the gate protection diode elements connected to the gate electrode of the ISFET, the gate protection diode element is provided on the gate electrode of the vertical MISFET with an interlayer insulating film interposed.

[0014]

According to the above-mentioned means, the area occupied by the gate protection diode element becomes substantially equal to the area of the gate electrode of the vertical MISFET, so that the gate protection diode element does not increase in external size of the semiconductor chip. The joint width W can be increased, and the protective effect can be improved.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings.

In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) FIG. 1 is a main part of a semiconductor device having a single structure having a vertical MISFET according to a first embodiment of the present invention and a gate protection diode element connected to a gate electrode of the vertical MISFET. FIG. 2 is a plan view showing the layout, and FIG. 2 is a sectional view taken along the line AA shown in FIG.

As shown in FIGS. 1 and 2, the semiconductor device having a simple structure is mainly composed of an n-type semiconductor substrate (semiconductor chip) 1 having a rectangular planar shape. This n
A plurality of vertical MISFs are provided in the central region of the semiconductor substrate 1.
An ET (power transistor) is arranged. Semiconductor substrate 1
The central region of is surrounded by the peripheral region. That is, the vertical MISFETs are regularly arranged in a matrix in the central region of the n-type semiconductor substrate 1 and electrically connected in parallel.

The vertical MISFET is an n-type semiconductor substrate 1
The main surface of the central area of the. That is, vertical MISF
ET is composed of a channel forming region, a source region, a drain region, a gate insulating film 3, a gate electrode 4, and the like.
The channel formation region is composed of the p-type semiconductor region 5 formed on the main surface of the n-type semiconductor substrate 1. The p-type semiconductor region 2 is integrally formed in the p-type semiconductor region 5 for the purpose of ohmic connection with the source electrode 12. The source region is composed of the n + type semiconductor region 6 formed on the main surface of the p type semiconductor region 5. The drain region is composed of the n-type semiconductor substrate 1. The gate insulating film 3 is formed of, for example, a silicon oxide film formed by a thermal oxidation method. The gate electrode 4 is formed of, for example, a polycrystalline silicon film.

The p-type semiconductor region 5 (and 2) which is the channel forming region of the vertical MISFET and n + which is the source region.
A source line 12 is connected to each of the type semiconductor regions 6. The source wiring 12 extends on the interlayer insulating film 9,
P-type semiconductor region 5 and n + -type semiconductor region 6 through the opening 10
Connected to each of. The source wiring 12 is formed of, for example, an aluminum (Al) film.

An interlayer insulating film 7 is formed on the upper surface and the side surface of the gate electrode 4 of the vertical MISFET. A gate protection diode element connected to the gate electrode 6 is formed on the interlayer insulating film 7. The gate protection diode element is mainly composed of a diode material 8 formed on the interlayer insulating film 7, and the diode material 8 has an n + type semiconductor region 8B and a p type semiconductor region 8A, respectively. This gate protection diode element is formed on each gate electrode 4 of a plurality of vertical MISFETs with an interlayer insulating film 7 interposed. That is, the area of the gate protection diode element is formed to be substantially equal to the area of the gate electrode 4.

A diode wiring 11 is connected to the n + type semiconductor region 8B of the gate protection die-auto element. The diode wiring 11 extends over the interlayer insulating film 9 and is connected to the n + type semiconductor region 8B of the diode material 8 through the opening 9a formed in the interlayer insulating film 9. The diode wiring 11 is formed in the same layer as the source wiring 12 described above. That is, the semiconductor device of this embodiment has a single-layer wiring structure (single-layer aluminum wiring structure).

A final protective film (not shown) is formed on the entire surface of the substrate including the source wiring 12 and the die-auto wiring 11. The final protective film is formed of, for example, a polyimide resin film.

Next, a method of manufacturing the semiconductor device having the single structure will be briefly described with reference to FIGS. 3 to 5 (cross-sectional views of a main part shown in each manufacturing step).

First, the n-type semiconductor substrate 1 is prepared.

Next, a p-type impurity is selectively introduced into the main surface of the central region (active region) of the n-type semiconductor substrate 1 by, for example, an ion implantation method to form a p-type semiconductor region 2.

Next, a well-known selective thermal oxidation method is used to form a field insulating film (not shown) on the main surface of the peripheral region (inactive region) of the n-type semiconductor substrate 1.

Next, the gate insulating film 3 is formed on the main surface of the central region of the n-type semiconductor substrate 1. The gate insulating film 3 is formed of, for example, a silicon oxide film formed by a thermal oxidation method.

Next, a gate electrode 4 is formed on the surface of the gate insulating film 3. This gate electrode 4 is, for example, CV
It is formed by depositing a polycrystalline silicon film by the D method and patterning this polycrystalline silicon film. Impurities that reduce the resistance value are introduced into the polycrystalline silicon film during or after its deposition.

Next, on the main surface of the p-type semiconductor region 2, a p-type semiconductor region 5 serving as a channel forming region and an n + type semiconductor region 6 serving as a source region are formed.

Next, as shown in FIG. 3, an interlayer insulating film 7 is formed on the upper surface and the side surface of the gate electrode 4. The interlayer insulating film 7 is formed of, for example, a silicon oxide film formed by a thermal oxidation method.

Next, a polycrystalline silicon film is deposited on the entire surface of the substrate including the interlayer insulating film 7 by the CVD method, for example. After that, p-type impurities are introduced into the polycrystalline silicon film by, for example, an ion implantation method.

Next, the polycrystalline silicon film is subjected to predetermined patterning to form a diode material 8 on the interlayer insulating film 7. Then, by selectively introducing n-type impurities into the diode material 8 by an ion implantation method, as shown in FIG. 4, n + type semiconductor regions 8B and p-type semiconductor regions 8A are formed in the diode material 8. Thus, the gate protection diode element is formed on the gate electrode 4 with the interlayer insulating film 7 interposed.

Next, an interlayer insulating film 9 is formed on the diode material 8. The interlayer insulating film 9 is formed of, for example, a silicon oxide film deposited by the CVD method. After this, the interlayer insulating film 9
Then, the openings 9a and 10 are formed by predetermined patterning.

Next, after depositing an aluminum film on the entire surface of the substrate including the interlayer insulating film 9 by, for example, a sputtering method,
By applying a predetermined patterning to this aluminum film,
As shown in FIG. 5, the source wiring 12 and the diode wiring 1
Shape each one of 1. After that, a final protective film is formed on the entire surface of the substrate including the source wiring 12 and the diode wiring, whereby the semiconductor device of this embodiment is almost completed.

As described above, by forming the gate protection diode element on the gate electrodes 4 of the plurality of vertical MISFETs with the interlayer insulating film 7 interposed, the area of the gate protection diode element is smaller than that of the gate electrode 4. Since the area is almost the same as the area, the junction width W of the gate protection diode element can be increased without increasing the outer size of the semiconductor substrate (semiconductor chip) 1, and the protection effect can be improved.

(Embodiment 2) FIG. 6 is a main part of a semiconductor device having a single structure having a vertical MISFET according to a second embodiment of the present invention and a gate protection diode element connected to the gate electrode of the vertical MISFET. FIG. 7 is a plan view showing the layout, and FIG. 7 is a cross-sectional view taken along the line BB of FIG.

As shown in FIGS. 6 and 7, the semiconductor device having a single structure, which is the second embodiment of the present invention, has the same structure as that of the first embodiment, on the gate electrodes 4 of the plurality of vertical MISFETs. A gate protection diode element is formed with an interlayer insulating film 7 interposed therebetween. This semiconductor device has a two-layer wiring structure (two-layer aluminum wiring structure). That is,
A second layer wiring 14 is connected to the source wiring 12.
The second-layer wiring 14 extends on the interlayer insulating film 13 and is connected to the source wiring 12 through an opening (not shown) formed in the interlayer insulating film.

In the semiconductor device having a single structure constructed as described above, the junction width W of the gate protection diode element can be increased without increasing the outer size of the semiconductor chip as in the case of the first embodiment, and the protection effect can be obtained. In addition to the improvement, the current amount can be increased as compared with the single layer wiring structure.

The inventions made by the present inventors are as follows.
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0041]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

Vertical MISFET and this vertical MISFE
In the semiconductor device having the gate protection diode element connected to the gate electrode of T, the junction width W of the gate protection diode element can be increased and the protection effect can be improved without increasing the outer size of the semiconductor chip. .

[Brief description of drawings]

FIG. 1 is a vertical MISFET according to a first embodiment of the present invention.
A plan view showing a layout of a main part of a semiconductor device having a semi-single structure having a (power transistor) and a gate protection diode element connected to a gate electrode of the vertical MISFET;

FIG. 2 is a sectional view taken along the line AA shown in FIG.

FIG. 3 is a cross-sectional view of essential parts in a first manufacturing process of the semiconductor device,

FIG. 4 is a sectional view of an essential part in a second manufacturing step of the semiconductor device,

FIG. 5 is a cross-sectional view of essential parts in a third manufacturing process of the semiconductor device,

FIG. 6 is a plan view showing a main part layout of a semiconductor device having a semi-single unit structure having a vertical MISFET according to a second embodiment of the present invention and a gate protection diode element connected to a gate electrode of the vertical MISFET;

7 is a cross-sectional view taken along the line BB shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... n-type semiconductor substrate (semiconductor chip), 2 ... p-type semiconductor region, 3 ... gate insulating film, 4 ... gate electrode, 5 ... p-type semiconductor region, 6 ... n + -type semiconductor region, 7 ... interlayer insulating film, 8 ... diode material, 8A ... p-type semiconductor region, 8B ... n + -type semiconductor region, 9 ... interlayer insulating film, 9a, 10 ... opening, 11 ... diode wiring, 12 ... source wiring, 13 ... interlayer insulating film, 1
4 ... Wiring of the second layer.

Front page continuation (72) Inventor Katsuo Ishizaka 111 Nishiyokote-cho, Takasaki-shi, Gunma Hitachi Takasaki Plant Co., Ltd. (72) Nario Otaka 111 Nishiyote-cho, Takasaki-shi, Gunma Hitachi Takasaki Plant Co., Ltd. Within

Claims (1)

[Claims] 1. A vertical MISFET, and this vertical MISFE.
In the semiconductor device having each of the gate protection diode elements connected to the gate electrode of T, the vertical MIS
A semiconductor device comprising the gate protection diode element provided on an FET gate electrode with an interlayer insulating film interposed.