JPS58107662A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS58107662A JPS58107662A JP56206535A JP20653581A JPS58107662A JP S58107662 A JPS58107662 A JP S58107662A JP 56206535 A JP56206535 A JP 56206535A JP 20653581 A JP20653581 A JP 20653581A JP S58107662 A JPS58107662 A JP S58107662A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- electrode
- resistance element
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置に関し、特に負荷抵抗素子を内蔵す
る電界効果中導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and more particularly to a field-effect conductor device incorporating a load resistance element.
最近、ディジタル信号を扱う回路が発達し、ディジタル
回路が半導体集積回路で作られることが多くなってきた
。多くのディジタル回路はインノ（−タ回路を含んでい
る。Recently, circuits that handle digital signals have developed, and digital circuits are increasingly being made of semiconductor integrated circuits. Many digital circuits include inverter circuits.
第１図は従来のインバータ回路の一例を形成した半導体
＊ｒｌｔ（ＤＨ面図である。FIG. 1 is a DH side view of a semiconductor *rlt (DH) forming an example of a conventional inverter circuit.
Ｎｇシリコン基板１にＰＭウェル２を設け、その中にＮ
ｉｌのソース領域ａ、４．Ｎａ！！のドレイン領域５．
６．ゲート電極９．ｌＯを設けて、二つのＭ０８トラン
ジスタを形成する。ソース領域３゜ドレイン領域５．ゲ
ート電極９から成るエンノ・ンスメント臘ＭＯ８）ラン
ジスタを躯勧素子、ドレイン領域５とソース領域４とを
金域配４１１２で接続し、ソース領域４．ドレイ／領域
６．ゲート電極１０から成るデプレツシ四ンｆｊｌ１Ｍ
Ｏ８）うｙジスタを＊ｍ木子としてインバータ回路を構
成する。A PM well 2 is provided on an Ng silicon substrate 1, and N.
il source region a, 4. Na! ! Drain region5.
6. Gate electrode 9. Provide lO to form two M08 transistors. Source region 3° Drain region 5. An enhancement MO8) transistor consisting of a gate electrode 9 is connected to the drain region 5 and the source region 4 by a metal interconnection 4112, and the source region 4. Drey/Area 6. Depletion line fjl1M consisting of gate electrode 10
O8) Configure an inverter circuit by using the uy register as a *m tree.
第２図は従来のインバータ回路の他の例を形成した半導
体装置の断面図である。FIG. 2 is a sectional view of a semiconductor device forming another example of a conventional inverter circuit.
Ｎｉｌシリコン基板２１にＰ型ウェル２２を設けその中
にＮｕｔのソース領域２３．ドレイン領域２４、ゲート
電極２５を設けてＭＯＳ）ランジスタを形成する。ウェ
ル２２と間隔をおいてＰ型領＃２６を設け、その両端に
電極２９．３０を設けて抵抗素子とする。抵抗素子の電
極２９とドレイ／電極２８とを接続し、ＭＯＳ）ランジ
スタを駆勧累子、抵抗素子を負荷抵抗素子としてインバ
ータを構成する。A P-type well 22 is provided in a Nil silicon substrate 21, and a Nut source region 23. A drain region 24 and a gate electrode 25 are provided to form a MOS transistor. A P-type region #26 is provided at a distance from the well 22, and electrodes 29 and 30 are provided at both ends thereof to form a resistance element. The electrode 29 of the resistive element and the drain/electrode 28 are connected to form an inverter using the MOS transistor as a driving resistor and the resistive element as a load resistive element.
上記二つの例で示したように、従来のインバータを半導
体基板に形成する場合に負荷抵抗素子の占有面積が大き
く、そのために半導体チップの面積が大きくなってしま
うという欠点がちりた。As shown in the above two examples, when a conventional inverter is formed on a semiconductor substrate, the load resistance element occupies a large area, which leads to a disadvantage that the area of the semiconductor chip becomes large.
本発明は上記欠点を除き、負荷抵抗素子の占有面積を小
さくすることによシチツプ面積の縮小化を計り、以って
集積密度を向上させた半導体装置を提供するものである
。The present invention eliminates the above-mentioned drawbacks and provides a semiconductor device in which the chip area is reduced by reducing the area occupied by the load resistance element, thereby improving the integration density.
本発明の半導体装置は、ｓｉ導電型の半導体基板に設け
られた第２導電をの第１領域と％前記第１領域内に設け
られた第１導電型ＭＯ８）ランジスタと、＃記＠１領域
と間隔をおいて前記半導体基板に設けられた第２導電を
の第２領域と、前記第２１１域内に°設けられた第１導
電型の第３領域と。The semiconductor device of the present invention includes a first region of a second conductive layer provided on a semiconductor substrate of a Si conductive type, an MO8) transistor of a first conductive type provided in the first region, and a region marked with #@1. a second region of a second conductivity type provided in the semiconductor substrate with an interval therebetween; and a third region of a first conductivity type provided within the 211th region.
前記第２導電截の第２領域の牛導体基板謄面に終る端面
にそれぞれ設けられた二つの電極と、ｍ記二つの電極の
うちの一方の電極と前記ＭＯＳトランジスタのドレイン
電極とを接続する配線とを含み、前記ＭＯ８）ツンジス
タを駆動菓子とし前記第２領域とその両端電極とを負荷
抵抗素子として構成される。Connecting two electrodes respectively provided on the end face of the second region of the second conductive cutout, which end at the bottom surface of the conductor substrate, and one electrode of the two electrodes m to the drain electrode of the MOS transistor. The second region and the electrodes at both ends thereof are configured as a load resistance element with the MO8) Tungister as a driving confection.
本発明を実施例によシ説明する。The present invention will be explained by way of examples.
８３図は本発明の一実施例の＃面図である。FIG. 83 is a side view of one embodiment of the present invention.
Ｎ＠シリコン基板３１にＰＷウェル３２を設け。A PW well 32 is provided on an N@silicon substrate 31.
その中にＰ＠ソース領域３３．ドレイン領域３４を設け
る。我面にフィールド酸化膜３５．ゲート酸化膜３６を
設け、ソース電極３７．ドレイ／′ｆＩｔ極３８．ゲー
ト電極３９を設ける。Ｐ型ウェル３２と間隔をおいてＰ
ｇの第２績域４０を設け、その中にＮ鉦の第３饋域４１
を設ける。第２領域４０の半導体基板表面に終る端面に
電極４２．４３を形成し、第２領域４０を抵抗素子とす
る。ドレイ／電極３８と抵抗素子の電極４２とを配線４
４で接続する。Ｐ１１１ウェル３２に作られるＭＯＳ）
ランジスタを駆動素子、抵抗素子４２を負荷抵抗素子と
してインバータ回路が構成される。P@source area 33. A drain region 34 is provided. Field oxide film 35. A gate oxide film 36 is provided, and a source electrode 37 . Drei/'fIt pole 38. A gate electrode 39 is provided. P type well 32 and spaced apart from P type well 32
A second performance area 40 of g is provided, and a third performance area 41 of N key is provided within it.
will be established. Electrodes 42 and 43 are formed on the end face of the second region 40 that ends at the surface of the semiconductor substrate, and the second region 40 is used as a resistance element. The wire 4 connects the drain/electrode 38 and the electrode 42 of the resistance element.
Connect with 4. MOS made in P111 well 32)
An inverter circuit is configured using the transistor as a driving element and the resistance element 42 as a load resistance element.
この実施列は第２図に示した従来のインバータ回路と全
く同様の性能を有する。しかも、抵抗素子の抵抗領域４
０はＵ字形に曲けられた形をしているので半導体チップ
上での占有面積が小さくなるという効果を有する。This implementation has exactly the same performance as the conventional inverter circuit shown in FIG. Moreover, the resistance region 4 of the resistance element
0 has a U-shaped bent shape, which has the effect of reducing the area occupied on the semiconductor chip.
以上旺細に説明したように１本発明によれば、負荷抵抗
素子の占有面積を縮小し、以って集積密度を向上させる
半導体装置が得られるのでその効果は大きい。As described in detail above, according to the present invention, it is possible to obtain a semiconductor device in which the area occupied by the load resistance element is reduced and the integration density is improved, so the effect is significant.
第１図は従来のインバータ回路の一例を形成した半導体
装置の断面図、第２図は従来のインノ（−夕回路の他の
列を形成した半導体装置の断面図。
第３図は本発明の一実施例の断面図である。
１・・・・・・Ｎをシ＋’）コン基板、２・・・・・・
Ｐｆｊｌウェル、３．４・・・・・・Ｎｌソース領域、
５，６・・・・・・Ｎ型ドレイン領域、７・・・・・・
フィールド酸化膜、８・・・・・・ゲート酸化膜、９．
１０・・・・・・ゲート電極、１１・・・・・・ソース
電極、１２・・・・・・ドレイン電極％ ２１・・・・
・・Ｎｕシリコン基板、シ２・・・・・・Ｐ型りエル、
２３・・・・・・Ｎ型ソース領域、２４・・・・・・Ｎ
型ドレイン電極、２５・・・・・・ゲート電極、２６・
・・・・・Ｐ＠領領域２７・−・・・・ソース電極、２
８・・・・・・ドレイ／を極、２９．３０・・・・・・
抵抗の電極、３１・・・・・・Ｎ型シリコン基板、３２
・・・・・・Ｐ型ウェル、３３・・・・・・Ｐ＠ソース
領域、３４・・・・・・Ｐ型ドレイン領域、３５・・・
・・・フィールド酸化膜、３６・・・・・・ゲート酸化
膜、３７・・・・・・ソース電極、３８・・・・・・ド
レイン電極、３９・・・・・・ゲート電極、４０・・・
・・・Ｐ型第２領域、４１・・・・・・Ｎ型第３領域、
４２゜４３・・・・・・抵抗の電極、４４・・・・・・
配線。FIG. 1 is a cross-sectional view of a semiconductor device forming an example of a conventional inverter circuit, and FIG. 2 is a cross-sectional view of a semiconductor device forming another column of a conventional inverter circuit. It is a sectional view of one embodiment. 1...N is a +') contact board, 2...
Pfjl well, 3.4...Nl source region,
5, 6...N-type drain region, 7...
Field oxide film, 8... Gate oxide film, 9.
10...Gate electrode, 11...Source electrode, 12...Drain electrode% 21...
...Nu silicon substrate, Si2...P type Riel,
23...N type source region, 24...N
type drain electrode, 25...gate electrode, 26.
...P@region 27 ---source electrode, 2
8...Drey/wo pole, 29.30...
Resistance electrode, 31...N-type silicon substrate, 32
...P type well, 33...P@source region, 34...P type drain region, 35...
... Field oxide film, 36 ... Gate oxide film, 37 ... Source electrode, 38 ... Drain electrode, 39 ... Gate electrode, 40.・・・
...P-type second region, 41...N-type third region,
42゜43... Resistance electrode, 44...
wiring.
Claims (1)
１領域と、１ｉｔｌ記＠ｌ領域内に設けられた第１導電
ｉ！ｔ！ＭＯ８）？ンジスタと、前記＠１領域と間隔を
おいて前記半導体基板に設けられた第２導電型の＠２領
域と、ｓｔＩ記第２領域内に設けられた第１導ｖｉａの
第３領域と、前記第２導電匿の第２領域の半導体基板表
面に終る端面にそれぞれ設けられた二つの電極と％前記
二つの電極のうちの一方の電極と前記ＭＯ８）ランジス
タのドレイン電極とを接続する配線とを含み、前記ＭＯ
８）ランジスタを駆動素子として前記第２領域とその両
端電極とを負荷抵抗素子とすることを特徴とする半導体
装置。The first region of the 112 conductive view provided on the semiconductor substrate of the first conductive view, and the first conductive i! T! MO8)? a second conductivity type @2 region provided in the semiconductor substrate at a distance from the @1 region; a third region of the first conductive via provided in the second region stI; two electrodes each provided on the end face of the second conductive second region ending on the surface of the semiconductor substrate; and a wiring connecting one of the two electrodes and the drain electrode of the MO8 transistor. including the MO
8) A semiconductor device, wherein a transistor is used as a driving element, and the second region and electrodes at both ends thereof are used as a load resistance element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56206535A JPS58107662A (en) | 1981-12-21 | 1981-12-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56206535A JPS58107662A (en) | 1981-12-21 | 1981-12-21 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58107662A true JPS58107662A (en) | 1983-06-27 |
Family
ID=16524973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56206535A Pending JPS58107662A (en) | 1981-12-21 | 1981-12-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58107662A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5162877A (en) * | 1987-01-27 | 1992-11-10 | Fujitsu Limited | Semiconductor integrated circuit device and method of producing same |
-
1981
- 1981-12-21 JP JP56206535A patent/JPS58107662A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5162877A (en) * | 1987-01-27 | 1992-11-10 | Fujitsu Limited | Semiconductor integrated circuit device and method of producing same |
| US5294566A (en) * | 1987-01-27 | 1994-03-15 | Fujitsu Limited | Method of producing a semiconductor integrated circuit device composed of a negative differential resistance element and a FET transistor |
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