JP2005340528A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method Download PDF

Info

Publication number
JP2005340528A
JP2005340528A JP2004158223A JP2004158223A JP2005340528A JP 2005340528 A JP2005340528 A JP 2005340528A JP 2004158223 A JP2004158223 A JP 2004158223A JP 2004158223 A JP2004158223 A JP 2004158223A JP 2005340528 A JP2005340528 A JP 2005340528A
Authority
JP
Japan
Prior art keywords
region
semiconductor device
semiconductor layer
diffusion region
depth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004158223A
Other languages
Japanese (ja)
Inventor
Toshiyuki Matsui
俊之 松井
Yasuyuki Hoshi
保幸 星
Yasuyuki Kobayashi
靖幸 小林
Yasushi Miyasaka
靖 宮坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Device Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=35424243&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=JP2005340528(A) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Fuji Electric Device Technology Co Ltd filed Critical Fuji Electric Device Technology Co Ltd
Priority to JP2004158223A priority Critical patent/JP2005340528A/en
Priority to US11/080,367 priority patent/US7282781B2/en
Priority to DE200510014932 priority patent/DE102005014932B4/en
Priority to CNB2005100647421A priority patent/CN100487913C/en
Publication of JP2005340528A publication Critical patent/JP2005340528A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/868—PIN diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Thyristors (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To sufficently enhance resistance enough to withstand lightning surge against the damping factor di/dt of reverse recovery current in a converter diode or the like while forward voltage VF is being kept low. <P>SOLUTION: P<SP>+</SP>diffusion areas 23, 24 and 25 of 14-20 μm in depth (design value) are selectively formed on the surface layer of an n<SP>-</SP>semiconductor layer. He ions are directed onto the entire surface of a chip, and a life time killer is introduced from a shallower position d2 than the position d1 of a pn junction surface 31 formed of the n<SP>-</SP>semiconductor layer 22 and the p<SP>+</SP>diffusion area 23, to a deeper position d3, thus forming a low life time area 32 on the entire surface of the chip. The He ions are given so that the depth of the p<SP>+</SP>diffusion area 23 may be the irradiation half-value width of the He ion or more, the peak position of the He ion may be deeper than the irradiation half-value width of the He ion, and the peak position may range 80-120% of the depth of the p<SP>+</SP>diffusion area 23. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

この発明は、パワーモジュール等に搭載される半導体装置およびその製造方法に関し、特に半導体モジュールに印加された雷サージ等に対して高い耐量を有する半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device mounted on a power module or the like and a manufacturing method thereof, and more particularly, to a semiconductor device having a high resistance against a lightning surge applied to a semiconductor module and a manufacturing method thereof.

図６は、パワーモジュールの一例を示す図である。図６に示すように、このパワーモジュールは、コンバータ部１、ブレーキ部２、インバータ部３およびサーミスタ４を備えている。通常、コンバータ部１のコンバータダイオード５は、ＰＩＮダイオードにより構成される。例えば、モジュール定格が１２００Ｖまたは６００Ｖである場合、コンバータダイオード５として、それぞれ１６００Ｖ以上または８００Ｖ以上の耐圧を有するＰＩＮダイオードが用いられる。   FIG. 6 is a diagram illustrating an example of a power module. As shown in FIG. 6, this power module includes a converter unit 1, a brake unit 2, an inverter unit 3, and a thermistor 4. Usually, the converter diode 5 of the converter unit 1 is constituted by a PIN diode. For example, when the module rating is 1200 V or 600 V, a PIN diode having a withstand voltage of 1600 V or higher or 800 V or higher is used as the converter diode 5, respectively.

このように定格以上の耐圧が要求される理由は、モジュールに定格以上の耐圧がかかることがあり、そのような場合にＰＩＮダイオードの破壊が起こらないようにするためである。また、コンバータダイオード５として用いられるＰＩＮダイオードでは、順電圧ＶＦが低いことが要求される。例えば、モジュール定格が１２００Ｖであるコンバータダイオード５では、順電圧ＶＦの要求値は、１．２〜１．５Ｖ程度である。   The reason why the breakdown voltage exceeding the rating is required in this way is to prevent the breakdown of the PIN diode in such a case where the module may have a breakdown voltage exceeding the rating. Further, the PIN diode used as the converter diode 5 is required to have a low forward voltage VF. For example, in the converter diode 5 whose module rating is 1200V, the required value of the forward voltage VF is about 1.2 to 1.5V.

図７は、従来のプレーナ型ＰＩＮダイオードの構成を示す断面図である。図７に示すように、ｎ+半導体層１１の上に、カソード領域となるｎ-半導体層１２が設けられている。ｎ-半導体層１２の表面層には、アノード領域となるｐ+拡散領域１３と、ガードリング領域となるｐ+拡散領域１４，１５が設けられている。 FIG. 7 is a cross-sectional view showing a configuration of a conventional planar PIN diode. As shown in FIG. 7, an n − semiconductor layer 12 serving as a cathode region is provided on the n + semiconductor layer 11. In the surface layer of the n − semiconductor layer 12, p + diffusion regions 13 serving as anode regions and p + diffusion regions 14 and 15 serving as guard ring regions are provided.

ｐ+拡散領域１４，１５の表面は、ＳｉＯ2等の絶縁膜１６により覆われている。ｐ+拡散領域１３には、アノード電極１７が接触している。ｎ+半導体層１１は、カソード電極１８に電気的に接続されている。なお、本明細書および添付図面において、ｎまたはｐを冠記した層や領域は、それぞれ電子または正孔がキャリアであることを意味する。また、ｎやｐに付す+、または-もしくは--は、それぞれ比較的高不純物濃度または比較的低不純物濃度であることを表す。 The surfaces of the p + diffusion regions 14 and 15 are covered with an insulating film 16 such as SiO 2 . The anode electrode 17 is in contact with the p + diffusion region 13. The n + semiconductor layer 11 is electrically connected to the cathode electrode 18. Note that in this specification and the accompanying drawings, a layer or a region having n or p is a sign that electrons or holes are carriers. Further, + or − or −− attached to n or p represents a relatively high impurity concentration or a relatively low impurity concentration, respectively.

従来のコンバータダイオード５の各部の寸法等は、次のとおりである。モジュール定格が１２００Ｖであり、耐圧が１６００Ｖである場合、比抵抗約１２０ΩｃｍのＦＺウェハよりなるｎ-半導体層１２の厚さは、３００μｍである。そして、ｐ+拡散領域１３の深さは、６〜８μｍであり、そのドーズ量は、１×１０15ｃｍ-2である。 The dimensions and the like of each part of the conventional converter diode 5 are as follows. When the module rating is 1200 V and the withstand voltage is 1600 V, the thickness of the n − semiconductor layer 12 made of an FZ wafer having a specific resistance of about 120 Ωcm is 300 μm. The depth of the p + diffusion region 13 is 6 to 8 μm, and the dose is 1 × 10 15 cm −2 .

また、モジュール定格が６００Ｖであり、耐圧が８００Ｖである場合には、比抵抗約４０Ωｃｍの拡散ウェハよりなるｎ-半導体層１２の厚さは、８０μｍ程度である。そして、ｐ+拡散領域１３については、モジュール定格１２００Ｖの場合と同じである。 When the module rating is 600V and the breakdown voltage is 800V, the thickness of the n − semiconductor layer 12 made of a diffusion wafer having a specific resistance of about 40 Ωcm is about 80 μm. The p + diffusion region 13 is the same as the module rating of 1200V.

上述したパワーモジュールにおいて、コンバータ動作時に雷サージ等が入ると、コンバータ部１に逆回復電流の減衰率（以下、ｄｉ／ｄｔと表す）の高いサージが印加される。そのため、コンバータダイオード５は、激しい逆回復動作モードとなり、高いｄｉ／ｄｔに耐えられずに、図８に示すように、破壊してしまうことがある。図８は、従来のコンバータ部１に高いｄｉ／ｄｔのサージが入り、コンバータダイオード５が破壊したときの波形図である。図８では、電流については１目盛りが１００Ａであり、電圧については１目盛りが２００Ｖであり、時間については１目盛りが１μ秒である。   In the power module described above, when a lightning surge or the like occurs during converter operation, a surge with a high reverse recovery current attenuation factor (hereinafter referred to as di / dt) is applied to the converter unit 1. For this reason, the converter diode 5 enters a severe reverse recovery operation mode, cannot withstand high di / dt, and may be destroyed as shown in FIG. FIG. 8 is a waveform diagram when a high di / dt surge enters the conventional converter unit 1 and the converter diode 5 is destroyed. In FIG. 8, one scale for current is 100 A, one scale for voltage is 200 V, and one scale is 1 μsec for time.

このような不具合が起こるのを防ぐため、近年、パワーモジュールに搭載されるコンバータ部１に対して、雷サージ等の高いｄｉ／ｄｔのサージに耐えられることが要求されている。以下、本明細書では、このｄｉ／ｄｔに対する耐量をｄｉ／ｄｔ耐量と表記する。   In order to prevent such a problem from occurring, in recent years, it is required that the converter unit 1 mounted on the power module can withstand a high di / dt surge such as a lightning surge. Hereinafter, in this specification, the tolerance against di / dt is expressed as di / dt tolerance.

ところで、ダイオードの逆回復動作モード時に、チップの外周部に電流が過度に集中して発熱すると、ダイオードが破壊してしまう。これを避けるため、Ｈｅイオンの照射によりダイオードの電極端部にのみライフタイムの短い領域を形成して、逆回復耐量を向上させることが提案されている（例えば、特許文献１参照。）。Ｈｅイオンの照射によりライフタイムの短い領域を形成することは、別の文献にも記載されている（例えば、特許文献２参照。）。   By the way, when the current is excessively concentrated on the outer peripheral portion of the chip during the reverse recovery operation mode of the diode and the heat is generated, the diode is destroyed. In order to avoid this, it has been proposed to improve the reverse recovery resistance by forming a region having a short lifetime only at the electrode end of the diode by irradiation with He ions (see, for example, Patent Document 1). The formation of a region having a short lifetime by irradiation with He ions is also described in another document (for example, see Patent Document 2).

また、接合深さが４〜８μｍのＰＮ接合付近にライフタイムキラーを導入して、ＰＮ接合付近のライフタイムを短くした高速ダイオードが公知である（例えば、特許文献３参照。）。また、接合深さが３μｍ程度のＰＮ接合を有するダイオードに対して、深さが１０〜３０μｍの範囲内にＨｅイオンを照射して、ｐ層の下のｎ-層中にライフタイムの短い領域を導入した半導体装置が公知である（例えば、特許文献４参照。）。さらに、ライフタイムキラーとして重金属を熱拡散させて導入する半導体素子の製造方法が公知である（例えば、特許文献５参照。）。 In addition, a high-speed diode in which a lifetime killer is introduced near a PN junction having a junction depth of 4 to 8 μm to shorten the lifetime near the PN junction is known (for example, see Patent Document 3). Further, a diode having a PN junction with a junction depth of about 3 μm is irradiated with He ions within a depth of 10 to 30 μm, and a region having a short lifetime in the n − layer under the p layer. A semiconductor device in which is introduced is known (for example, see Patent Document 4). Further, a method for manufacturing a semiconductor element in which heavy metal is introduced by thermal diffusion as a lifetime killer is known (see, for example, Patent Document 5).

なお、インバータ部３のフリーホイーリングダイオード６（図６参照）の各部の寸法等は、次のとおりである。耐圧が１２００Ｖである場合、ｎ--半導体層およびｎ-半導体層よりなるエピタキシャルウェハにおいて、比抵抗約６５Ωｃｍのｎ--半導体層の厚さは、約７０μｍである。比抵抗約４０Ωｃｍのｎ-半導体層の厚さは、約５０μｍである。 In addition, the dimension of each part of the freewheeling diode 6 (refer FIG. 6) of the inverter part 3 is as follows. If the breakdown voltage is 1200 V, n - in the epitaxial wafer made of a semiconductor layer, n of the specific resistance of about 65Ωcm - - semiconductor layer and the n-thickness of the semiconductor layer is about 70 [mu] m. The thickness of the n − semiconductor layer having a specific resistance of about 40 Ωcm is about 50 μm.

耐圧が６００Ｖである場合には、同様のエピタキシャルウェハにおいて、比抵抗約２５Ωｃｍのｎ--半導体層の厚さは、約４５μｍである。比抵抗約１５Ωｃｍのｎ-半導体層の厚さは、約２５μｍである。そして、いずれの耐圧でも、ｐ+拡散領域の深さは、３〜４μｍであり、そのドーズ量は、１０13ｃｍ-2程度である。 When the breakdown voltage is 600 V, the thickness of the n − -semiconductor layer having a specific resistance of about 25 Ωcm is about 45 μm in the same epitaxial wafer. The thickness of the n − semiconductor layer having a specific resistance of about 15 Ωcm is about 25 μm. At any breakdown voltage, the depth of the p + diffusion region is 3 to 4 μm, and the dose is about 10 13 cm −2 .

特開２００１−１３５８３１号公報JP 2001-135831 A 特開平１０−１１６９９８号公報JP-A-10-116998 特開平１０−２００１３２号公報JP-A-10-200132 特開２００３−２４９６６２号公報Japanese Patent Laid-Open No. 2003-249662 特開２００４−６６６４号公報JP 2004-6664 A

上記各特許文献に記載されている技術は、半導体装置として動作しているときの逆回復時のソフトリカバリー特性と、ソフトリカバリー化による逆回復時の破壊防止に関するものである。通常のリカバリー特性におけるｄｉ／ｄｔは、５００〜１０００Ａ／μ秒程度である。   The technologies described in the above patent documents relate to soft recovery characteristics during reverse recovery when operating as a semiconductor device, and prevention of breakdown during reverse recovery due to soft recovery. In normal recovery characteristics, di / dt is about 500 to 1000 A / μsec.

それに対して、コンバータ部に入ることが予想される雷サージのｄｉ／ｄｔは、約３５００Ａ／μ秒である。そのため、上記各特許文献に記載されている技術によって得られるｄｉ／ｄｔ耐量は、雷サージ等の高いｄｉ／ｄｔに対しては、不十分である。実際に本発明者らが実験したところ、上記各特許文献に記載されている技術では、雷サージ等に対して有効な高いｄｉ／ｄｔ耐量を得ることができないことが判明した。   In contrast, the lightning surge di / dt expected to enter the converter section is about 3500 A / μsec. Therefore, the di / dt tolerance obtained by the techniques described in the above patent documents is insufficient for high di / dt such as lightning surge. As a result of experiments conducted by the present inventors, it has been found that the techniques described in the above-mentioned patent documents cannot obtain a high di / dt resistance effective against lightning surges.

例えば、ダイオードの全面にライフタイムキラーを導入し、チップの全面にわたってライフタイムを低下させることによって、ｄｉ／ｄｔ耐量がある程度、改善されることがわかっているが、そのためには順電圧ＶＦを大幅に増大させる必要がある。しかし、上述したように、コンバータダイオードでは、順電圧ＶＦを低くしなければならないので、順電圧ＶＦを増大させることは好ましくない。   For example, by introducing a lifetime killer over the entire surface of the diode and reducing the lifetime over the entire surface of the chip, it has been found that the di / dt resistance is improved to some extent. For this purpose, the forward voltage VF is greatly increased. Need to be increased. However, as described above, since the forward voltage VF must be lowered in the converter diode, it is not preferable to increase the forward voltage VF.

また、チップの外周部や端部において局所的にライフタイムを低下させることによっても、ｄｉ／ｄｔ耐量がある程度、改善されるが、雷サージに耐え得る程度に十分に高いｄｉ／ｄｔ耐量を得ることはできない。また、この場合、局所的にライフタイムキラーを導入するための導入しない部分への厚い遮蔽膜を形成したり、その遮蔽膜を除去する必要があるため、製造工程が複雑になり、チップコストが上昇してしまうという不都合がある。   In addition, the di / dt resistance can be improved to some extent by locally reducing the lifetime at the outer periphery and end of the chip, but a sufficiently high di / dt resistance to withstand lightning surge is obtained. It is not possible. Further, in this case, since it is necessary to form a thick shielding film on the part not to be introduced for locally introducing a lifetime killer or to remove the shielding film, the manufacturing process becomes complicated and the chip cost is reduced. There is an inconvenience of rising.

また、チップ表面またはその近傍に、Ｈｅイオンやプロトン等を用いて深さ方向に局所的にライフタイムの短い領域を形成しても、十分なｄｉ／ｄｔ耐量を得ることはできない。また、ライフタイムキラーとして重金属を拡散させる場合には、その拡散深さを制御するのは難しい。   Further, even if a region having a short lifetime is locally formed in the depth direction using He ions, protons, or the like on the chip surface or in the vicinity thereof, sufficient di / dt resistance cannot be obtained. Moreover, when diffusing heavy metals as a lifetime killer, it is difficult to control the diffusion depth.

この発明は、上述した従来技術による問題点を解消するため、雷サージに耐え得る程度に十分に高いｄｉ／ｄｔ耐量と、低い順電圧ＶＦを有する半導体装置を提供することを目的とする。また、この発明は、雷サージに耐え得る程度に十分に高いｄｉ／ｄｔ耐量と、低い順電圧ＶＦを有する半導体装置を容易に作製することができる半導体装置の製造方法を提供することを目的とする。   An object of the present invention is to provide a semiconductor device having a sufficiently high di / dt resistance and a low forward voltage VF to withstand a lightning surge in order to eliminate the above-described problems caused by the prior art. Another object of the present invention is to provide a semiconductor device manufacturing method capable of easily manufacturing a semiconductor device having a sufficiently high di / dt resistance to withstand lightning surge and a low forward voltage VF. To do.

上述した課題を解決し、目的を達成するため、本発明者らは、鋭意研究を重ねた結果、チップ全面にわたってＰＮ接合面よりも浅い位置から深い位置までの領域にライフタイムの短い領域を存在させることによって、雷サージ等に対して十分に高いｄｉ／ｄｔ耐量が得られることを見出した。また、本発明者らは、ＰＮ接合面がある程度深くなると、雷サージ等に対して十分に高いｄｉ／ｄｔ耐量が得られることも見出した。本発明は、このような知見に基づいてなされたものである。   In order to solve the above-described problems and achieve the object, the present inventors have conducted extensive research, and as a result, a region having a short lifetime exists in a region from a shallower position to a deeper position than the PN junction surface over the entire surface of the chip. It has been found that a sufficiently high di / dt resistance against lightning surge and the like can be obtained. The inventors have also found that a sufficiently high di / dt resistance against a lightning surge or the like can be obtained when the PN junction surface is deepened to some extent. The present invention has been made based on such knowledge.

請求項１の発明にかかる半導体装置は、第１導電型半導体層と、前記第１導電型半導体層の表面層に選択的に設けられた第２導電型半導体領域よりなる１２．６μｍ以上の深さの拡散領域と、前記第１導電型半導体層および前記拡散領域の全体にわたって、前記拡散領域と前記第１導電型半導体層との接合界面であるＰＮ接合面の最も深い位置よりも浅い位置から該ＰＮ接合面の最も深い位置よりも深い位置まで、Ｈｅイオンの照射により形成されたライフタイムキラーを含むことによって、他の領域よりもキャリアのライフタイムが短い低ライフタイム領域と、を備えることを特徴とする。   According to a first aspect of the present invention, there is provided a semiconductor device having a depth of 12.6 μm or more comprising a first conductive type semiconductor layer and a second conductive type semiconductor region selectively provided on a surface layer of the first conductive type semiconductor layer. From a position shallower than the deepest position of the PN junction surface, which is the junction interface between the diffusion region and the first conductivity type semiconductor layer, over the entire diffusion region, the first conductivity type semiconductor layer, and the diffusion region. Including a lifetime killer formed by irradiation of He ions up to a deeper position than the deepest position of the PN junction surface, thereby providing a low lifetime region in which the lifetime of carriers is shorter than other regions It is characterized by.

請求項２の発明にかかる半導体装置は、請求項１に記載の発明において、前記拡散領域の深さは、２２μｍ以下であることを特徴とする。   A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the depth of the diffusion region is 22 μm or less.

請求項３の発明にかかる半導体装置は、請求項１または２に記載の発明において、前記拡散領域は、半導体装置として電流が流れる活性領域の周囲に設けられたガードリング領域を含むことを特徴とする。   A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein the diffusion region includes a guard ring region provided around an active region through which a current flows as a semiconductor device. To do.

請求項４の発明にかかる半導体装置は、請求項１〜３のいずれか一つに記載の発明において、ＰＩＮダイオードであることを特徴とする。   A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to any one of the first to third aspects, wherein the semiconductor device is a PIN diode.

請求項１〜４の発明によれば、低ライフタイム領域が、チップの全面にわたって、１２．６μｍ以上の深さのＰＮ接合面よりも浅い位置から深い位置までの領域に設けられているので、順電圧ＶＦを大幅に増大させなくても、雷サージ等に対して十分に高いｄｉ／ｄｔ耐量が得られる。   According to the first to fourth aspects of the present invention, the low lifetime region is provided in a region from a shallower position to a deeper position than the PN junction surface having a depth of 12.6 μm or more over the entire surface of the chip. Even if the forward voltage VF is not significantly increased, a sufficiently high di / dt resistance against a lightning surge or the like can be obtained.

また、上述した課題を解決し、目的を達成するため、請求項５の発明にかかる半導体装置の製造方法は、第１導電型半導体層の表面層に選択的に第２導電型半導体領域よりなる１２．６μｍ以上の深さの拡散領域を有し、かつ前記第１導電型半導体層および前記拡散領域の全体にわたって、前記拡散領域と前記第１導電型半導体層との接合界面であるＰＮ接合面の最も深い位置よりも浅い位置から該ＰＮ接合面の最も深い位置よりも深い位置まで、他の領域よりもキャリアのライフタイムが短い低ライフタイム領域を有する半導体装置を製造するにあたって、前記第１導電型半導体層の表面層に前記拡散領域を１４μｍ以上の深さになるように選択的に形成する工程と、Ｈｅイオンのピーク位置がＨｅイオンの照射半値幅よりも深くなるように、前記第１導電型半導体層および前記拡散領域の全面にわたってＨｅイオンを照射して、ライフタイムキラーを有する前記低ライフタイム領域を形成する工程と、を含むことを特徴とする。   According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device comprising a second conductive semiconductor region selectively formed on a surface layer of the first conductive semiconductor layer. A PN junction surface which has a diffusion region with a depth of 12.6 μm or more and is a junction interface between the diffusion region and the first conductivity type semiconductor layer over the first conductivity type semiconductor layer and the diffusion region. In manufacturing a semiconductor device having a low lifetime region in which the carrier lifetime is shorter than other regions from a position shallower than the deepest position to a position deeper than the deepest position of the PN junction surface. A step of selectively forming the diffusion region in the surface layer of the conductive semiconductor layer so as to have a depth of 14 μm or more, and a peak position of He ions so as to be deeper than an irradiation half-value width of He ions. And irradiating He ions over the entire surface of the first conductive type semiconductor layer and the diffusion region to form the low lifetime region having a lifetime killer.

請求項６の発明にかかる半導体装置の製造方法は、請求項５に記載の発明において、前記低ライフタイム領域を形成する際に、Ｈｅイオンのピーク位置が前記拡散領域の深さの８０％以上１２０％以下の範囲になるように、Ｈｅイオンを照射することを特徴とする。   According to a sixth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the fifth aspect, wherein the peak position of He ions is 80% or more of the depth of the diffusion region when the low lifetime region is formed. Irradiation with He ions is performed so as to be in a range of 120% or less.

請求項７の発明にかかる半導体装置の製造方法は、請求項５または６に記載の発明において、Ｈｅイオン種として３Ｈｅ2+を用いることを特徴とする。 A method of manufacturing a semiconductor device according to a seventh aspect of the invention is characterized in that, in the invention according to the fifth or sixth aspect, 3He 2+ is used as a He ion species.

請求項５〜７の発明によれば、チップの全面にＨｅイオンを照射するので、チップの全面にわたって、１２．６μｍ以上の深さのＰＮ接合面よりも浅い位置から深い位置までの領域にライフタイムの短い領域を容易に形成することができる。   According to the fifth to seventh aspects of the present invention, since He ions are irradiated to the entire surface of the chip, the entire surface of the chip is exposed to a region from a shallower position to a deeper position than a PN junction surface having a depth of 12.6 μm or more. A region with a short time can be easily formed.

本発明にかかる半導体装置によれば、順電圧ＶＦを大幅に増大させなくても、雷サージ等に対して十分に高いｄｉ／ｄｔ耐量が得られるので、雷サージに耐え得る程度に十分に高いｄｉ／ｄｔ耐量と、低い順電圧ＶＦを有する半導体装置が得られるという効果を奏する。また、本発明にかかる半導体装置の製造方法によれば、チップの全面にわたって、１２．６μｍ以上の深さのＰＮ接合面よりも浅い位置から深い位置までの領域にライフタイムの短い領域を容易に形成することができるので、雷サージに耐え得る程度に十分に高いｄｉ／ｄｔ耐量と、低い順電圧ＶＦを有する半導体装置を容易に作製することができるという効果を奏する。   According to the semiconductor device of the present invention, a sufficiently high di / dt resistance against lightning surge or the like can be obtained without significantly increasing the forward voltage VF, so that it is sufficiently high to withstand lightning surge. There is an effect that a semiconductor device having a di / dt tolerance and a low forward voltage VF can be obtained. Further, according to the method of manufacturing a semiconductor device according to the present invention, a region having a short lifetime can be easily formed in a region from a shallower position to a deeper position than a PN junction surface having a depth of 12.6 μm or more over the entire surface of the chip. Since the semiconductor device can be formed, a semiconductor device having a sufficiently high di / dt resistance enough to withstand a lightning surge and a low forward voltage VF can be easily produced.

以下に添付図面を参照して、この発明にかかる半導体装置およびその製造方法の好適な実施の形態を詳細に説明する。   Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings.

図１は、本発明の実施の形態にかかるプレーナ型ＰＩＮダイオードの構成を示す断面図である。図１に示すように、ｎ+半導体層２１の上に、カソード領域となるｎ-半導体層２２が設けられている。ダイオードとして電流が流れる活性領域において、ｎ-半導体層２２の表面層には、アノード領域となるｐ+拡散領域２３が選択的に設けられている。 FIG. 1 is a cross-sectional view showing a configuration of a planar PIN diode according to an embodiment of the present invention. As shown in FIG. 1, an n − semiconductor layer 22 serving as a cathode region is provided on an n + semiconductor layer 21. In an active region where current flows as a diode, a p + diffusion region 23 serving as an anode region is selectively provided in the surface layer of the n − semiconductor layer 22.

また、活性領域の外側の耐圧構造部において、ｎ-半導体層２２の表面層には、ガードリング領域となるｐ+拡散領域２４，２５が設けられている。耐圧構造部の表面は、ＳｉＯ2等の絶縁膜２６により覆われている。アノード電極２７は、ｐ+拡散領域２３に接触している。カソード電極２８は、ｎ+半導体層２１に電気的に接続されている。 In the breakdown voltage structure outside the active region, p + diffusion regions 24 and 25 serving as guard ring regions are provided in the surface layer of the n − semiconductor layer 22. The surface of the withstand voltage structure is covered with an insulating film 26 such as SiO 2 . The anode electrode 27 is in contact with the p + diffusion region 23. The cathode electrode 28 is electrically connected to the n + semiconductor layer 21.

また、低ライフタイム領域３２が、ｎ-半導体層２２とｐ+拡散領域２３との接合界面であるＰＮ接合面３１の最も深い位置ｄ１よりも浅い位置ｄ２から、このＰＮ接合面３１の最も深い位置ｄ１よりも深い位置ｄ３まで、チップ全体にわたって設けられている。低ライフタイム領域３２は、Ｈｅイオンやプロトン等の軽イオン（以下、Ｈｅイオン等とする）の照射により形成されたライフタイムキラーを含んでおり、他の領域よりもキャリアのライフタイムが短い領域である。 In addition, the low lifetime region 32 starts from the deepest position d2 of the PN junction surface 31 which is the junction interface between the n − semiconductor layer 22 and the p + diffusion region 23, and is deepest in the PN junction surface 31. The entire chip is provided up to a position d3 deeper than the position d1. The low lifetime region 32 includes a lifetime killer formed by irradiation with light ions such as He ions and protons (hereinafter referred to as He ions), and has a shorter carrier lifetime than other regions. It is.

低ライフタイム領域３２は、ガードリング領域となるｐ+拡散領域２４，２５とｎ-半導体層２２との接合界面であるＰＮ接合面３３，３４の最も深い部分も含んでいる。このように低ライフタイム領域３２が設けられていることによって、ダイオードの逆回復時に、端部への電流集中が抑えられるので、高いｄｉ／ｄｔ耐量が得られる。 Low lifetime region 32 also includes deepest portions of PN junction surfaces 33 and 34 that are junction interfaces between p + diffusion regions 24 and 25 that serve as guard ring regions and n − semiconductor layer 22. Since the low lifetime region 32 is provided in this way, current concentration at the end can be suppressed during reverse recovery of the diode, so that a high di / dt resistance can be obtained.

ここで、ｐ+拡散領域２３の深さ、すなわちｎ-半導体層２２とｐ+拡散領域２３とからなるＰＮ接合面３１の最も深い位置ｄ１は、ｐ+拡散領域２３の表面から１２．６μｍ以上２２μｍ以下の範囲にあるのが好ましい。ｄ１の設計上の値は、１４μｍ以上２０μｍであるが、±１０％の結晶公差を見込むと、実際にできあがったダイオードでは、ｄ１はこのような値となる。 Here, the depth of the p + diffusion region 23, that is, the deepest position d 1 of the PN junction surface 31 composed of the n − semiconductor layer 22 and the p + diffusion region 23 is 12.6 μm or more from the surface of the p + diffusion region 23. It is preferably in the range of 22 μm or less. The design value of d1 is not less than 14 μm and not more than 20 μm. However, when a crystal tolerance of ± 10% is anticipated, d1 becomes such a value in an actually completed diode.

図１に示す構成のダイオードを作製するにあたっては、まず、ｎ-半導体層２２の表面層にｐ+拡散領域２３，２４，２５を選択的に形成する。その際、ガードリング領域となるｐ+拡散領域２４，２５や、アノード領域となるｐ+拡散領域２３の終端部分のみを局所的に深くする必要はない。つまり、１回の拡散で同時にｐ+拡散領域２３，２４，２５を形成することができる。従って、チップコストが増大することはない。 In fabricating the diode having the configuration shown in FIG. 1, first, p + diffusion regions 23, 24, and 25 are selectively formed in the surface layer of the n − semiconductor layer 22. At that time, it is not necessary to locally deepen only the end portions of the p + diffusion regions 24 and 25 serving as the guard ring regions and the p + diffusion region 23 serving as the anode region. That is, the p + diffusion regions 23, 24, and 25 can be simultaneously formed by one diffusion. Therefore, the chip cost does not increase.

そして、ｐ+拡散領域２３，２４，２５およびｎ-半導体層２２の全面にＨｅイオン等を照射して、結晶中にＨｅイオン等を導入する。その後、３５０℃程度の温度でアニールを行う。このようにして、ライフタイムキラーを導入し、低ライフタイム領域３２を形成する。 Then, He ions and the like are introduced into the crystal by irradiating the entire surfaces of the p + diffusion regions 23, 24 and 25 and the n − semiconductor layer 22 with He ions and the like. Thereafter, annealing is performed at a temperature of about 350 ° C. In this way, the lifetime killer is introduced and the low lifetime region 32 is formed.

上記プロセスにおいてＨｅイオン等を照射する際には、ｐ+拡散領域２３の深さ、すなわち前記ｄ１の深さがＨｅイオン等の照射半値幅以上になるようにする。また、Ｈｅイオン等のピーク位置がＨｅイオン等の照射半値幅よりも深くなるようにする。さらに、Ｈｅイオン等のピーク位置が前記ｄ１の深さの８０％以上１２０％以下の範囲になるようにする。 When irradiating He ions or the like in the above process, the depth of the p + diffusion region 23, that is, the depth of the d1 is set to be equal to or greater than the half width of irradiation of He ions or the like. Further, the peak position of He ions or the like is set to be deeper than the half width of irradiation of He ions or the like. Further, the peak position of He ions or the like is set in a range of 80% to 120% of the depth of d1.

照射する軽イオンとしては、Ｈｅイオンが効果的である。具体的にＨｅイオンの照射条件の一例を挙げれば、例えば、２３ＭｅＶの加速電圧で３Ｈｅ2+を照射する。この場合には、前記ｄ１の位置を挟んで上下にそれぞれ５μｍ程度の幅を有する低ライフタイム領域３２が形成される。このようにすることによって、効果的に逆回復時のキャリアを消滅させることができる。 As light ions to be irradiated, He ions are effective. If an example of irradiation conditions of He ion is specifically mentioned, 3He < 2+ > will be irradiated with the acceleration voltage of 23 MeV, for example. In this case, low lifetime regions 32 each having a width of about 5 μm are formed on both sides of the position of d1. By doing so, carriers at the time of reverse recovery can be effectively eliminated.

一例として、実施の形態にかかるＰＩＮダイオードの各部の寸法等は、次のとおりである。モジュール定格が１２００Ｖであり、耐圧が１６００Ｖである場合、比抵抗１２０ΩｃｍのＦＺウェハよりなるｎ-半導体層２２の厚さは、３００μｍである。そして、ｐ+拡散領域２３の深さは、結晶公差を含めると２０±２μｍであり、そのドーズ量は、１×１０15ｃｍ-2である。 As an example, dimensions and the like of each part of the PIN diode according to the embodiment are as follows. When the module rating is 1200 V and the withstand voltage is 1600 V, the thickness of the n − semiconductor layer 22 made of an FZ wafer having a specific resistance of 120 Ωcm is 300 μm. The depth of the p + diffusion region 23 is 20 ± 2 μm including the crystal tolerance, and the dose is 1 × 10 15 cm −2 .

次に、本発明者らが、実施の形態にかかるＰＩＮダイオードの特性を調べた結果について説明する。図２は、サージ波形を調べた結果を示す波形図である。図２より、ｄｉ／ｄｔが４０００Ａ／μ秒であるが、ダイオードは破壊していないことがわかる。   Next, a description will be given of the results of investigations by the present inventors on the characteristics of the PIN diode according to the embodiment. FIG. 2 is a waveform diagram showing the result of examining the surge waveform. FIG. 2 shows that di / dt is 4000 A / μsec, but the diode is not destroyed.

図３は、ｄｉ／ｄｔ耐量と順電圧ＶＦとの関係を示す特性図である。図３に示すように、順電圧ＶＦの増加を最小限に抑えつつ、４０００Ａ／μ秒を超えるｄｉ／ｄｔ耐量が確保されていることがわかる。図３に示す例では、Ｈｅイオンを照射した後、３５０℃程度の温度でアニールを実施することにより、順電圧ＶＦとサージに対する高いｄｉ／ｄｔ耐量の両方が達成されている。   FIG. 3 is a characteristic diagram showing the relationship between the di / dt tolerance and the forward voltage VF. As shown in FIG. 3, it can be seen that a di / dt resistance exceeding 4000 A / μsec is ensured while minimizing the increase in the forward voltage VF. In the example shown in FIG. 3, both the forward voltage VF and the high di / dt resistance against surge are achieved by performing annealing at a temperature of about 350 ° C. after irradiation with He ions.

図４は、ｄｉ／ｄｔ耐量とＰＮ接合深さ（前記ｄ１）、すなわちｐ+拡散領域２３の深さとの関係を示す特性図である。図４に示すように、ＰＮ接合深さを１４μｍ以上にすることによって、低ライフタイム領域３２が半導体結晶の内部に形成されるので、４０００Ａ／μ秒以上の高いｄｉ／ｄｔ耐量が得られることがわかる。なお、図４において、白抜きの丸印で示すプロットは、ＰＮ接合深さが８μｍである従来のＰＩＮダイオードのものである。 FIG. 4 is a characteristic diagram showing the relationship between the di / dt resistance and the PN junction depth (d1), that is, the depth of the p + diffusion region 23. As shown in FIG. 4, by setting the PN junction depth to 14 μm or more, the low lifetime region 32 is formed inside the semiconductor crystal, so that a high di / dt resistance of 4000 A / μsec or more can be obtained. I understand. In FIG. 4, the plots indicated by white circles are those of a conventional PIN diode having a PN junction depth of 8 μm.

図５は、ＰＮ接合深さ（前記ｄ１）を１６μｍまたは２０μｍとしたときのｄｉ／ｄｔ耐量とＨｅイオンのピーク位置、すなわち低ライフタイム領域３２の深さとの関係を示す特性図である。図５に示すように、低ライフタイム領域３２がＰＮ接合面３１を含み、かつＨｅイオンのピーク位置がＰＮ接合深さの±２０％以内であれば、その実力値が同等であることがわかる。また、このときに、順電圧ＶＦを最小限に抑えることができる。   FIG. 5 is a characteristic diagram showing the relationship between the di / dt resistance and the peak position of He ions, that is, the depth of the low lifetime region 32 when the PN junction depth (d1) is 16 μm or 20 μm. As shown in FIG. 5, if the low lifetime region 32 includes the PN junction surface 31 and the peak position of He ions is within ± 20% of the PN junction depth, it can be seen that the ability values are equivalent. . At this time, the forward voltage VF can be minimized.

以上説明したように、実施の形態によれば、低ライフタイム領域３２が、チップの全面にわたって、１４〜２０μｍ（設計値）の深さにあるＰＮ接合面３１よりも浅い位置（ｄ２）から深い位置（ｄ１）までの領域に設けられているので、端部において消滅しきれずに残ったキャリアを効果的に消滅させることができる。従って、順電圧ＶＦを大幅に増大させなくても、雷サージ等に対して十分に高いｄｉ／ｄｔ耐量を有するダイオードが得られる。   As described above, according to the embodiment, the low lifetime region 32 is deeper from a position (d2) shallower than the PN junction surface 31 at a depth of 14 to 20 μm (design value) over the entire surface of the chip. Since it is provided in the region up to the position (d1), it is possible to effectively annihilate carriers that have not completely disappeared at the end portion. Therefore, a diode having a sufficiently high di / dt resistance against a lightning surge or the like can be obtained without significantly increasing the forward voltage VF.

以上において、本発明は、上述した実施の形態に限らず、種々変更可能である。例えば、上述した寸法やドーズ量などは一例であり、これに限定されるものではない。また、上述した実施の形態では、第１導電型をｎ型とし、第２導電型をｐ型としたが、本発明は、第１導電型をｐ型とし、第２導電型をｎ型としても同様に成り立つ。   As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the dimensions and doses described above are examples, and the present invention is not limited to these. In the above-described embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. The same holds true.

以上のように、本発明にかかる半導体装置およびその製造方法は、パワーモジュール等に搭載される半導体装置に有用であり、特に、コンバータに用いられるＰＩＮダイオードや、インバータに用いられるフリーホイーリングダイオードに適している。   As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for a semiconductor device mounted on a power module or the like, and particularly for a PIN diode used for a converter or a free wheeling diode used for an inverter. Are suitable.

実施の形態にかかるプレーナ型ＰＩＮダイオードの構成を示す断面図である。It is sectional drawing which shows the structure of the planar type PIN diode concerning embodiment. 実施の形態にかかるＰＩＮダイオードのサージ波形を示す波形図である。It is a wave form diagram which shows the surge waveform of the PIN diode concerning embodiment. 実施の形態にかかるＰＩＮダイオードのｄｉ／ｄｔ耐量と順電圧ＶＦとの関係を示す特性図である。It is a characteristic view which shows the relationship between the di / dt tolerance of the PIN diode concerning embodiment, and the forward voltage VF. 実施の形態にかかるＰＩＮダイオードのｄｉ／ｄｔ耐量とＰＮ接合深さとの関係を示す特性図である。It is a characteristic view which shows the relationship between the di / dt tolerance of the PIN diode concerning embodiment, and PN junction depth. 実施の形態にかかるＰＩＮダイオードのｄｉ／ｄｔ耐量とＨｅイオンのピーク位置との関係を示す特性図である。It is a characteristic view which shows the relationship between the di / dt tolerance of the PIN diode concerning embodiment, and the peak position of He ion. 自動車用パワーモジュールの一例を示す回路図である。It is a circuit diagram which shows an example of the power module for motor vehicles. 従来のプレーナ型ＰＩＮダイオードの構成を示す断面図である。It is sectional drawing which shows the structure of the conventional planar type PIN diode. 従来のコンバータ部にサージが入ったときの波形を示す波形図である。It is a wave form diagram which shows a waveform when a surge enters into the conventional converter part.

符号の説明Explanation of symbols

２２ 第１導電型半導体層（ｎ-半導体層）
２３，２４，２５ 第２導電型拡散領域（ｐ+拡散領域）
３１ ＰＮ接合面
３２ 低ライフタイム領域



22 First conductivity type semiconductor layer (n − semiconductor layer)
23, 24, 25 Second conductivity type diffusion region (p + diffusion region)
31 PN interface 32 Low lifetime region



Claims (7)

第１導電型半導体層と、
前記第１導電型半導体層の表面層に選択的に設けられた第２導電型半導体領域よりなる１２．６μｍ以上の深さの拡散領域と、
前記第１導電型半導体層および前記拡散領域の全体にわたって、前記拡散領域と前記第１導電型半導体層との接合界面であるＰＮ接合面の最も深い位置よりも浅い位置から該ＰＮ接合面の最も深い位置よりも深い位置まで、Ｈｅイオンの照射により形成されたライフタイムキラーを含むことによって、他の領域よりもキャリアのライフタイムが短い低ライフタイム領域と、
を備えることを特徴とする半導体装置。 A first conductivity type semiconductor layer;
A diffusion region having a depth of 12.6 μm or more, comprising a second conductivity type semiconductor region selectively provided on a surface layer of the first conductivity type semiconductor layer;
The entire surface of the first conductive type semiconductor layer and the diffusion region are arranged from the shallowest position to the deepest position of the PN junction surface, which is the junction interface between the diffusion region and the first conductive type semiconductor layer. By including a lifetime killer formed by irradiation of He ions to a deeper position than a deep position, a low lifetime region in which the carrier lifetime is shorter than other regions,
A semiconductor device comprising: 前記拡散領域の深さは、２２μｍ以下であることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a depth of the diffusion region is 22 μm or less. 前記拡散領域は、半導体装置として電流が流れる活性領域の周囲に設けられたガードリング領域を含むことを特徴とする請求項１または２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the diffusion region includes a guard ring region provided around an active region through which a current flows as a semiconductor device. ＰＩＮダイオードであることを特徴とする請求項１〜３のいずれか一つに記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor device is a PIN diode. 第１導電型半導体層の表面層に選択的に第２導電型半導体領域よりなる１２．６μｍ以上の深さの拡散領域を有し、かつ前記第１導電型半導体層および前記拡散領域の全体にわたって、前記拡散領域と前記第１導電型半導体層との接合界面であるＰＮ接合面の最も深い位置よりも浅い位置から該ＰＮ接合面の最も深い位置よりも深い位置まで、他の領域よりもキャリアのライフタイムが短い低ライフタイム領域を有する半導体装置を製造するにあたって、
前記第１導電型半導体層の表面層に前記拡散領域を１４μｍ以上の深さになるように選択的に形成する工程と、
Ｈｅイオンのピーク位置がＨｅイオンの照射半値幅よりも深くなるように、前記第１導電型半導体層および前記拡散領域の全面にわたってＨｅイオンを照射して、ライフタイムキラーを有する前記低ライフタイム領域を形成する工程と、
を含むことを特徴とする半導体装置の製造方法。 The surface layer of the first conductivity type semiconductor layer has a diffusion region having a depth of 12.6 μm or more selectively made of the second conductivity type semiconductor region, and over the entire first conductivity type semiconductor layer and the diffusion region. , Carriers from a position shallower than the deepest position of the PN junction surface, which is a junction interface between the diffusion region and the first conductive semiconductor layer, to a position deeper than the deepest position of the PN junction surface, compared to other regions. In manufacturing a semiconductor device having a low lifetime region with a short lifetime
Selectively forming the diffusion region in the surface layer of the first conductivity type semiconductor layer to a depth of 14 μm or more;
The low lifetime region having a lifetime killer by irradiating He ions over the entire surface of the first conductive semiconductor layer and the diffusion region such that the peak position of He ions is deeper than the half width of He ion irradiation. Forming a step;
A method for manufacturing a semiconductor device, comprising: 前記低ライフタイム領域を形成する際に、Ｈｅイオンのピーク位置が前記拡散領域の深さの８０％以上１２０％以下の範囲になるように、Ｈｅイオンを照射することを特徴とする請求項５に記載の半導体装置の製造方法。   6. When forming the low lifetime region, He ions are irradiated so that a peak position of He ions is in a range of 80% to 120% of the depth of the diffusion region. The manufacturing method of the semiconductor device as described in 2. above. Ｈｅイオン種として３Ｈｅ2+を用いることを特徴とする請求項５または６に記載の半導体装置の製造方法。



7. The method of manufacturing a semiconductor device according to claim 5, wherein 3He 2+ is used as the He ion species.



JP2004158223A 2004-05-27 2004-05-27 Semiconductor device and its manufacturing method Pending JP2005340528A (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2004158223A JP2005340528A (en) 2004-05-27 2004-05-27 Semiconductor device and its manufacturing method
US11/080,367 US7282781B2 (en) 2004-05-27 2005-03-15 Semiconductor device with a short-lifetime region and manufacturing method thereof
DE200510014932 DE102005014932B4 (en) 2004-05-27 2005-04-01 Semiconductor component and method for its production
CNB2005100647421A CN100487913C (en) 2004-05-27 2005-04-18 Semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004158223A JP2005340528A (en) 2004-05-27 2004-05-27 Semiconductor device and its manufacturing method

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2012101066A Division JP5549704B2 (en) 2012-04-26 2012-04-26 Semiconductor device and manufacturing method thereof

Publications (1)

Publication Number Publication Date
JP2005340528A true JP2005340528A (en) 2005-12-08

Family

ID=35424243

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004158223A Pending JP2005340528A (en) 2004-05-27 2004-05-27 Semiconductor device and its manufacturing method

Country Status (4)

Country Link
US (1) US7282781B2 (en)
JP (1) JP2005340528A (en)
CN (1) CN100487913C (en)
DE (1) DE102005014932B4 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8178941B2 (en) 2008-07-22 2012-05-15 Fuji Electric Co., Ltd. Semiconductor device
JP2014135476A (en) * 2012-12-12 2014-07-24 Fuji Electric Co Ltd Semiconductor device
US9450110B2 (en) 2013-03-21 2016-09-20 Fuji Electric Co., Ltd. Semiconductor device

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10316222B3 (en) * 2003-04-09 2005-01-20 eupec Europäische Gesellschaft für Leistungshalbleiter mbH Method for producing a robust semiconductor component and semiconductor component produced thereby
DE102007062305B3 (en) * 2007-12-21 2009-05-28 Semikron Elektronik Gmbh & Co. Kg Power semiconductor component with trench-shaped field ring structure and manufacturing method for this purpose
JP5450490B2 (en) * 2011-03-24 2014-03-26 株式会社東芝 Power semiconductor device
CN103715083B (en) * 2012-09-28 2018-07-06 中国科学院微电子研究所 The preparation method of FRD
JP6496992B2 (en) * 2014-07-22 2019-04-10 富士電機株式会社 Semiconductor device
JP2016029685A (en) * 2014-07-25 2016-03-03 株式会社東芝 Semiconductor device
JP6319453B2 (en) * 2014-10-03 2018-05-09 富士電機株式会社 Semiconductor device and manufacturing method of semiconductor device
DE112016000062T5 (en) * 2015-01-14 2017-03-02 Fuji Electric Co., Ltd. Semiconductor device
JP6766889B2 (en) * 2017-01-17 2020-10-14 富士電機株式会社 Semiconductor devices and methods for manufacturing semiconductor devices
JP7052322B2 (en) * 2017-11-28 2022-04-12 富士電機株式会社 Silicon Carbide Semiconductor Device and Method for Manufacturing Silicon Carbide Semiconductor Device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04314367A (en) * 1991-04-12 1992-11-05 Fuji Electric Co Ltd Planar diode and its manufacture
JPH06314801A (en) * 1993-03-05 1994-11-08 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
WO2000016408A1 (en) * 1998-09-10 2000-03-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and its manufacturing method
JP2000106368A (en) * 1998-08-21 2000-04-11 Asea Brown Boveri Ag Semiconductor element and fabrication thereof
JP2001127066A (en) * 1999-10-28 2001-05-11 Fuji Electric Co Ltd Shielding mask for ion implantation and ion implanter for manufacturing semiconductor

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4291329A (en) * 1979-08-31 1981-09-22 Westinghouse Electric Corp. Thyristor with continuous recombination center shunt across planar emitter-base junction
CH668860A5 (en) * 1986-02-05 1989-01-31 Bbc Brown Boveri & Cie SEMICONDUCTOR COMPONENT AND METHOD FOR THE PRODUCTION THEREOF.
JPH10116998A (en) 1996-10-14 1998-05-06 Toyota Motor Corp Semiconductor device and its manufacture
JPH10200132A (en) 1997-01-10 1998-07-31 Fuji Electric Co Ltd High speed diode
JP3435166B2 (en) * 1997-08-14 2003-08-11 三菱電機株式会社 Semiconductor device
JP4653273B2 (en) 1999-11-05 2011-03-16 富士電機システムズ株式会社 Semiconductor device and manufacturing method thereof
JP5061407B2 (en) * 2001-01-31 2012-10-31 富士電機株式会社 Semiconductor device and manufacturing method thereof
JP2004006664A (en) 2002-04-10 2004-01-08 Sanken Electric Co Ltd Manufacturing method of semiconductor device
JP3910922B2 (en) 2003-02-12 2007-04-25 三菱電機株式会社 Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04314367A (en) * 1991-04-12 1992-11-05 Fuji Electric Co Ltd Planar diode and its manufacture
JPH06314801A (en) * 1993-03-05 1994-11-08 Mitsubishi Electric Corp Semiconductor device and manufacture thereof
JP2000106368A (en) * 1998-08-21 2000-04-11 Asea Brown Boveri Ag Semiconductor element and fabrication thereof
WO2000016408A1 (en) * 1998-09-10 2000-03-23 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and its manufacturing method
JP2001127066A (en) * 1999-10-28 2001-05-11 Fuji Electric Co Ltd Shielding mask for ion implantation and ion implanter for manufacturing semiconductor

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8178941B2 (en) 2008-07-22 2012-05-15 Fuji Electric Co., Ltd. Semiconductor device
JP2013179342A (en) * 2008-07-22 2013-09-09 Fuji Electric Co Ltd Semiconductor device
US8716826B2 (en) 2008-07-22 2014-05-06 Fuji Electric Co., Ltd. Semiconductor device
JP2014135476A (en) * 2012-12-12 2014-07-24 Fuji Electric Co Ltd Semiconductor device
US9985090B2 (en) 2012-12-12 2018-05-29 Fuji Electric Co., Ltd. Semiconductor device with low lifetime region
US10535729B2 (en) 2012-12-12 2020-01-14 Fuji Electric Co., Ltd. Semiconductor device with low lifetime region
US9450110B2 (en) 2013-03-21 2016-09-20 Fuji Electric Co., Ltd. Semiconductor device

Also Published As

Publication number Publication date
DE102005014932A1 (en) 2005-12-22
US20050263842A1 (en) 2005-12-01
CN100487913C (en) 2009-05-13
US7282781B2 (en) 2007-10-16
CN1702876A (en) 2005-11-30
DE102005014932B4 (en) 2010-12-02

Similar Documents

Publication Publication Date Title
US7282781B2 (en) Semiconductor device with a short-lifetime region and manufacturing method thereof
JP5052091B2 (en) Semiconductor device
JP6078961B2 (en) Manufacturing method of semiconductor device
JP6237915B2 (en) Semiconductor device and manufacturing method of semiconductor device
JP5641055B2 (en) Semiconductor device and manufacturing method thereof
JP2008091705A (en) Semiconductor device and manufacturing method thereof
US20150014742A1 (en) Semiconductor device and production method for semiconductor device
JP5695343B2 (en) Semiconductor device
JP4746927B2 (en) Manufacturing method of semiconductor device
US20130221403A1 (en) Semiconductor device and method of manufacturing semiconductor device
JP2009272550A (en) Semiconductor device
JP2006332127A (en) Semiconductor device for power
JP5267036B2 (en) Manufacturing method of semiconductor device
JP2013542597A (en) Bipolar non-punch-through power semiconductor device
US9543405B2 (en) Method of manufacturing a reduced free-charge carrier lifetime semiconductor structure
JP6018163B2 (en) Semiconductor device
JP5277882B2 (en) Semiconductor device and manufacturing method thereof
JP6467882B2 (en) Semiconductor device and method for manufacturing semiconductor device
JP5825329B2 (en) Semiconductor device and manufacturing method thereof
JP2004247593A (en) Semiconductor device, and manufacturing method thereof
JP6678549B2 (en) Semiconductor device, method of manufacturing the same, and power conversion system
JP6237731B2 (en) Semiconductor device
JP2009194330A (en) Semiconductor device and its manufacturing method
JP5549704B2 (en) Semiconductor device and manufacturing method thereof
JP2006196502A (en) Power semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20070215

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090116

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20091112

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20091112

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20091112

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110308

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20110422

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110509

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120207

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120426

A911 Transfer of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20120507

A912 Removal of reconsideration by examiner before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A912

Effective date: 20120615