JP5061407B2 - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP5061407B2
JP5061407B2 JP2001023985A JP2001023985A JP5061407B2 JP 5061407 B2 JP5061407 B2 JP 5061407B2 JP 2001023985 A JP2001023985 A JP 2001023985A JP 2001023985 A JP2001023985 A JP 2001023985A JP 5061407 B2 JP5061407 B2 JP 5061407B2
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semiconductor
platinum
oxide film
semiconductor device
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JP2002231968A (en
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祥司 北村
俊之 松井
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Fuji Electric Co Ltd
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Fuji Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609—Diodes
    • H01L29/66136—PN junction diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体装置およびその製造方法に関し、特にｐｎ接合を利用した整流素子用の半導体装置およびその製造方法に関する。
【０００２】
【従来の技術】
一般に、高周波スイッチングに用いられる半導体装置として、高速リカバリーダイオードが公知である。このダイオードは、Ｐ型の半導体領域とＮ型の半導体領域とのｐｎ接合を有し、ライフタイムキラーとして白金等の重金属を拡散させることによってキャリアのライフタイムを短くしたものである。
【０００３】
図２１は、従来の高速リカバリーダイオードの構成を示す縦断面図である。このダイオードは、Ｎ型の半導体基板１１、半導体基板１１よりもキャリア濃度が低いＮ型の半導体層１２、Ｐ型の活性領域１３、Ｐ型のガードリング領域１４、酸化膜１５、表面電極１６および裏面電極１７を有する。
【０００４】
半導体層１２は半導体基板１１上にエピタキシャル成長により形成される。活性領域１３およびガードリング領域１４は、半導体層１２上に積層された酸化膜をパターニングし、それをマスクとしてＰ型の不純物をイオン注入することにより形成される。そのイオン注入後の熱処理によって半導体層１２の表面は再び酸化膜１５で被覆されるが、その酸化膜１５の一部を除去して活性領域１３を露出させ、白金の熱拡散後に活性領域１３上に表面電極１６が形成される。裏面電極１７は半導体基板１１の裏面に形成される。
【０００５】
ところで、近時、上述した構成のダイオードは力率改善回路（ＰＦＣ回路）に用いられることがある。一般に、この用途で使用されるダイオードには、逆回復電流が小さく、かつ逆回復時の逆方向電流のピーク値を過ぎてからの電流減衰率が小さいというソフトリカバリー特性が要求される。その理由は、逆回復電流が大きいと力率改善回路にスイッチング素子として設けられるＭＯＳトランジスタ等のターンオン損失の増大や素子温度の上昇を招き、その減衰率が大きいと大きな電圧ノイズが発生し、それが電源電圧に重畳されてダイオード、およびＭＯＳトランジスタ等に印加されることによって、素子の破壊や、回路の誤動作を招くからである。
【０００６】
そこで、図２１に示す従来のｐｎ接合ダイオードでは、白金拡散条件の制御によりキャリアのライフタイムを短くすることによって逆回復電流の低減を図っている。しかし、ダイオードの順方向電圧と逆回復電流とはトレードオフの関係にあり、順方向電圧の上昇を招く。さらに白金拡散条件制御だけでは逆回復時の逆方向電流の減衰率は小さくならないため、十分にソフトリカバリー化が達成されているとはいえない。そこで、白金濃度に加え、半導体層１２の厚さをとアノードキャリア濃度を最適化することがおこなわれているが、半導体層１２の厚さを増すと順方向電圧増加を招き、トレードオフは悪化する。
【０００７】
【発明が解決しようとする課題】
ライフタイムキラーとして白金を拡散させたｐｎ接合ダイオードでは、白金がダイオードの表面近傍の深さ数μｍの領域にパイルアップして存在するため、それよりも深いｐｎ接合近傍においては白金による効果が十分に発揮されない。そのため、上述したトレードオフの改善は不十分であり、ソフトリカバリー特性が余り改善されないという問題点がある。ｐｎ接合近傍において白金による効果を十分に発揮させるため、白金の注入量を増やすことが考えられる。しかし、その場合には、Ｎ型の半導体層が高抵抗化するだけでなく、Ｐ型の活性領域で白金濃度が高くなりすぎて欠陥が増加し、リーク電流が増えるという不具合を引き起こす。
【０００８】
本発明は、上記問題点に鑑みてなされたものであり、高速でかつ十分なソフトリカバリー特性を具えたダイオードを構成する半導体装置およびその製造方法を提供することを目的とする。
【０００９】
【課題を解決するための手段】
上記目的を達成するため、本発明は、第１導電型の半導体領域に白金をドープすることにより、その半導体領域の酸化膜で被われていない表面近傍部分を第２導電型に反転させ、その第２導電型の反転領域と第１導電型の半導体領域とでｐｎ接合を形成するようにしたものである。ｐｎ接合の深さは、白金を熱拡散させる際の温度および時間を制御することにより調節する。
【００１０】
この発明によれば、白金のドープによってできた第２導電型の反転領域と第１導電型の半導体領域とによりｐｎ接合部が形成されるため、従来よりもｐｎ接合部が浅くなり、ｐｎ接合部の位置と白金が有効に作用する位置とが一致する。
【００１１】
【発明の実施の形態】
以下に、本発明の実施の形態について図面を参照しつつ詳細に説明する。なお、以下の説明では、第１導電型をＮ型、第２導電型をＰ型とし、たとえばシリコンでできた半導体とする。
【００１２】
実施の形態１．
図１は、本発明の実施の形態１にかかる半導体装置の構造を示す縦断面図である。この半導体装置は、Ａｓ（ヒ素）ドープのＮ型の半導体基板２１、Ｐ（リン）ドープのＮ型の半導体層２２、Ｐ型の反転領域２３、Ｐ型のガードリング領域２４、酸化膜２５、表面電極２６、裏面電極２７および活性領域エッジ部２８を有する。たとえば半導体基板２１の厚さは３００μｍであり、その不純物濃度は２×１０19ｃｍ-3である。また、たとえば半導体層２２の厚さは６０μｍであり、その不純物濃度は２×１０14ｃｍ-3である。
【００１３】
半導体層２２の表面の一部は酸化膜２５により被覆されている。反転領域２３は、半導体層２２の表面の、酸化膜２５により被われていない領域の下に浅く形成されている。反転領域２３の接合深さｘｊ、すなわちｐｎ接合の深さはたとえば数μｍである。この反転領域２３は、半導体層２２の表面近傍領域にパイルアップした高濃度の白金によってＮ型の半導体層２２がＰ型に反転してできたものである。
【００１４】
なお、図１では、白金の拡散によって導電型が反転した領域の界面を破線で示す（他の図も同じ）。この破線で示す界面は、反転領域２３と半導体層２２とのｐｎ接合部２９に相当する。ｐｎ接合部２９の深さは、白金の熱拡散条件およびその後の熱処理条件によって変化する。つまり、白金の熱拡散条件およびその後の熱処理条件を制御することによって、ｐｎ接合部２９の深さを調節することができる。
【００１５】
活性領域エッジ部２８は、半導体層２２の表面側の領域に、反転領域２３を囲むように形成されている。活性領域エッジ部２８は、反転領域２３に接続しており、反転領域２３とともに活性領域を構成する。活性領域エッジ部２８の接合深さｘｊは約１０μｍであり、反転領域２３（ｘｊ：数μｍ）よりも深い。ここで、ソフトリカバリー化を達成するためには、活性領域の接合深さは浅い方が望ましい。しかし、一般に活性領域が薄くなると、そのエッジ部分での電界増大による耐圧不良が起こり易くなってしまう。本実施の形態では、活性領域のエッジ部に活性領域エッジ部２８を設けたことによって、活性領域の接合深さを従来よりも浅くしながらも、十分な耐圧を確保している。
【００１６】
ガードリング領域２４は、半導体層２２の表面側の領域に、反転領域２３および活性領域エッジ部２８を囲むように、特に限定しないが、たとえば一重のリング状に形成されている。ガードリング領域２４の接合深さｘｊは約１０μｍである。ガードリング領域２４は二重、あるいはそれ以上設けられていてもよい。表面電極２６は、反転領域２３および活性領域エッジ部２８の表面に接するように形成されている。裏面電極２７は、半導体基板２１の裏面に接するように形成されている。
【００１７】
ここで、白金のパイルアップによって半導体層２２の表面近傍領域に反転領域２３ができることについて、図２を参照しながら簡単に説明する。図２は、半導体に熱拡散させた白金の深さ方向のプロファイルを説明するための模式図である。
【００１８】
たとえば、ＡｓドープのＮ型の半導体基板２１（不純物濃度：２×１０19ｃｍ-3、厚さ：３００μｍ）上にＰドープのＮ型の半導体層２２（不純物濃度：２×１０14ｃｍ-3、厚さ：６０μｍ）をエピタキシャル成長させる。そして、半導体基板２１の裏面または半導体層２２の表面に白金を１重量％含有したペーストを塗布し、９２０℃で３時間の熱処理をおこなう。そうすると、白金はパイルアップして半導体基板２１の裏面および半導体層２２の表面に偏在する。その際、白金はアクセプタとして作用し、不純物濃度が低い半導体層２２の表面から数μｍメートルの領域がＰ型に反転する。
【００１９】
Ｎ型の半導体層２２の表面近傍領域において、白金のパイルアップによってＰ型に反転するのは、図３に示すように、半導体層２２の表面が酸化膜２５で被われていない領域である。つまり、Ｎ型の半導体層２２の表面にたとえば厚さ９００ｎｍの酸化膜２５を形成し、その中央部をフォトリソグラフィ技術により除去して半導体層２２を露出させる。そして、半導体基板２１の裏面または半導体層２２の露出面に白金を１重量％含有したペーストを塗布し、９２０℃で３時間の熱処理をおこなうと、半導体層２２の、酸化膜２５で被われていない露出領域にのみ白金が高濃度で偏在し、Ｐ型に反転する。これは、半導体層２２の表面近傍に拡散した白金が酸化膜２５中に取り込まれるため、酸化膜２５で被われている領域ではＰ型の反転が起こらないからであると推測される。
【００２０】
つぎに、白金の熱拡散条件およびその後の熱処理条件を制御することによって、ｐｎ接合部２９の深さを調節することが可能であることについて説明する。図４は、白金の熱拡散温度と反転領域２３の略中央を通る縦断面（図３に一点鎖線で示す断面）における表面近傍領域のキャリア濃度分布との関係を示す特性図である。図４において、各プロファイルの谷となっているところがｐｎ接合の深さに相当する。
【００２１】
図４によれば、たとえばある熱拡散時間の場合、拡散温度が９３０℃では接合深さは約１μｍであり、９７０℃では約１０μｍであり、１０００℃では約２５μｍである。また、白金のプロファイルは、拡散時間が長くなると半導体の表面より内部に分布していくことが知られている（Ｊ．Ａｐｐｌ．Ｐｈｙｓ．，Ｖｏｌ．６１，Ｎｏ．３ １０５５）。したがって、接合深さは、同じ温度でも拡散時間が長くなるとより深くなる。
【００２２】
図１に示す構成の半導体装置では、表面電極２６および裏面電極２７を形成する際には、電極の接触抵抗を安定化させるため、たとえば５００℃で１時間の熱処理をおこなうが、この熱処理によってもｐｎ接合部２９の深さが変化する。図５は、９３０℃で白金を熱拡散させた半導体装置について、５００℃で１時間の熱処理をおこなう前とおこなった後でのキャリア濃度分布の変化を示す特性図である。熱処理前の接合深さが１μｍであるのに対して、熱処理後の接合深さは２μｍである。このように、白金の熱拡散条件とその後の熱処理条件によって、Ｎ型の半導体層２２とＰ型の反転領域２３との接合深さを制御することができる。
【００２３】
つぎに、図１に示す半導体装置の製造方法について図６〜図９を参照しながら説明する。まず、半導体基板２１上に半導体層２２をエピタキシャル成長させる。つづいて、半導体層２２の表面上にたとえば厚さ９００ｎｍの熱酸化膜２０を形成する。そして、フォトリソグラフィ技術およびエッチングにより、活性領域エッジ部２８およびガードリング領域２４の形成領域に対応する部分の酸化膜をたとえばリング状に除去する。ここまでの状態が図６に示されている。
【００２４】
つづいて、酸化膜２０の残部をマスクとして半導体層２２にＢ（ボロン）をイオン注入する。このときのドーズ量は１×１０14ｃｍ-2であり、加速電圧は５０ｋＶである。しかる後、１２００℃で７時間の熱処理をおこない、活性領域エッジ部２８およびガードリング領域２４を形成する。このとき、同時にたとえば厚さが４００ｎｍの酸化膜が形成され、ウエハ全面が酸化膜２５で被われる。ここまでの状態が図７に示されている。
【００２５】
つづいて、フォトリソグラフィ技術およびエッチングにより、活性領域を形成する部分の酸化膜２５を除去する。この状態で、半導体基板２１の裏面または活性領域を形成する領域の半導体表面に、白金を１重量％含有したペーストを塗布し、９２０℃で３時間の熱処理をおこなう。これによって、半導体層２２の活性領域の表面近傍がＰ型に反転し、反転領域２３が形成される。ここまでの状態が図８に示されている。
【００２６】
つづいて、たとえばウエハ表面に厚さ３μｍのＡｌＳｉをスパッタリングによって積層する。そして、フォトリソグラフィ技術およびエッチングにより、ＡｌＳｉ層を所望の形状にパターニングする。しかる後、Ｎ2雰囲気中で５００℃、１時間の熱処理をおこない、反転領域２３および活性領域エッジ部２８に接する低抵抗性の表面電極２６を形成する。ここまでの状態が図９に示されている。なお、表面電極２６は、純Ａｌを真空蒸着することにより形成されていてもよい。
【００２７】
最後に、半導体基板２１の裏面にＴｉ、ＮｉおよびＡｕを真空蒸着により積層して裏面電極２７を形成して、半導体装置が完成し、図１に示す状態となる。たとえば、Ｔｉの厚さは０．７μｍであり、Ｎｉの厚さは０．３μｍであり、Ａｕの厚さは０．１μｍである。
【００２８】
つぎに、図１に示す本実施の形態の半導体装置と図２１に示す従来構造の半導体装置とについて、逆回復特性を測定した結果について説明する。図１０は本実施の形態の半導体装置の逆回復電流を示す波形図であり、図１１は従来の半導体装置の逆回復電流を示す波形図である。
【００２９】
本実施の形態の半導体装置では、逆回復電流のピーク値は約２．３Ａである。それに対して従来の半導体装置の逆回復電流のピーク値は約４．６Ａである。したがって、本実施の形態の逆回復電流のピーク値は従来のおおよそ５０％であり、大幅に低減されているのがわかる。また、ピーク後の逆回復電流の減衰は、従来の波形（図１１）に比べて著しくソフト化されているのがわかる。
【００３０】
図１２に、順方向電圧ＶＦと、逆回復電流ピーク値ＩＲＰの結果を示す。図１２において、従来構造でのＰt拡散条件調整によるトレードオフはすべてハードリカバリーであり、ソフト化するにはＶＦを増加、すなわちトレードオフは右へシフトすることになる。したがって、従来構造でのＰt拡散条件調整によるトレードオフに比べ、本発明の実施の形態１の結果は、トレードオフの改善が図られていることがわかる。
【００３１】
上述した実施の形態１によれば、Ｎ型の半導体層２２に白金を熱拡散させることによりその半導体層２２の表面近傍領域がＰ型に反転し、そのＰ型の反転領域２３とＮ型の半導体層２２とにより浅いｐｎ接合部を形成するため、必要以上に白金の濃度を高くしなくても、白金の効果が発揮される位置にｐｎ接合部が形成される。したがって、高速でかつ十分なソフトリカバリー特性を具えたダイオードを構成する半導体装置が得られる。
【００３２】
また、活性領域を浅く形成することができるため、ダイオードの順方向電圧と逆回復電流とのトレードオフの関係を改善することができる。また、従来のようにＮ型の半導体層２２にＰ型の不純物を注入してＰ型の半導体領域を形成することによってｐｎ接合を形成する必要がないので、製造プロセスが簡略化される。
【００３３】
なお、上述した実施の形態１では白金の熱拡散につづいて電極２６，２７を形成するとしたが、これに限らない。たとえば、白金の熱拡散後、電極２６，２７の形成前に、半導体装置全体の厚さが３００μｍ程度になるように、半導体基板１の裏面を研磨してもよい。そうすれば、放熱特性が向上する。
【００３４】
また、上述した実施の形態１では反転領域２３と活性領域エッジ部２８とで活性領域を構成したが、これに限らない。それほど高い耐圧が要求されない場合には、たとえば図１３に示すように、活性領域エッジ部２８を設けずに活性領域を反転領域２３のみで構成してもよい。図１３に示す例では、ガードリング領域２４は二重に設けられている。
【００３５】
実施の形態２．
図１４は、本発明の実施の形態２にかかる半導体装置の構造を示す縦断面図である。この半導体装置は、Ａｓ（ヒ素）ドープのＮ型の半導体基板４１、Ｐ（リン）ドープのＮ型の半導体層４２、Ｐ型の反転領域４３、Ｐ型のガードリング領域４４、酸化膜４５、表面電極４６および裏面電極４７を有する。たとえば半導体基板４１の厚さは５００μｍであり、その不純物濃度は２×１０19ｃｍ-3である。また、たとえば半導体層４２の厚さは６０μｍであり、その不純物濃度は２×１０14ｃｍ-3である。
【００３６】
半導体層４２の表面の一部は酸化膜４５により被覆されている。反転領域４３は、半導体層４２の表面の、酸化膜４５により被われていない領域の下に浅く形成されている。反転領域４３の接合深さ（ｐｎ接合部４９の深さ）ｘｊはたとえば数μｍである。ガードリング領域４４は、半導体層４２の表面側の領域に、反転領域４３を囲むように、特に限定しないが、たとえば二重のリング状に形成されている。ガードリング領域４４の接合深さｘｊは反転領域４３と同じである。ガードリング領域４４は一重、あるいは三重以上設けられていてもよい。表面電極４６は、反転領域４３の表面に接するように形成されている。裏面電極４７は、半導体基板４１の裏面に接するように形成されている。
【００３７】
ここで、反転領域４３およびガードリング領域４４は、半導体層４２の表面近傍領域にパイルアップした高濃度の白金によってＮ型の半導体層４２がＰ型に反転してできたものである。したがって、実施の形態１と同様に白金の熱拡散条件およびその後の熱処理条件を制御することによって、反転領域４３およびガードリング領域４４の接合深さを制御することができる。
【００３８】
つぎに、図１４に示す半導体装置の製造方法について図１５〜図１７を参照しながら説明する。まず、実施の形態１と同様にして半導体基板４１上に半導体層４２およびたとえば厚さが９００ｎｍの熱酸化膜４５を順次形成する。そして、フォトリソグラフィ技術およびエッチングにより、酸化膜４５の一部を除去して反転領域４３およびガードリング領域４４の形成領域の半導体表面を露出させる。ここまでの状態が図１５に示されている。
【００３９】
つづいて、半導体基板４１の裏面または酸化膜４５の除去により露出させた半導体表面に、白金を１重量％含有したペーストを塗布し、９２０℃で３時間の熱処理をおこなう。これによって、半導体層４２の露出面近傍がＰ型に反転し、反転領域４３およびガードリング領域４４が形成される。ここまでの状態が図１６に示されている。
【００４０】
そして、実施の形態１と同様にして反転領域４３に接する低抵抗性の表面電極４６を形成する。ここまでの状態が図１７に示されている。最後に、半導体基板４１の裏面に裏面電極４７を形成して、半導体装置が完成し、図１４に示す状態となる。
【００４１】
上述した実施の形態２によれば、実施に形態１と同様に、高速でかつ十分なソフトリカバリー特性を具えたダイオードを構成する半導体装置が得られるという効果と、Ｐ型不純物の注入工程が不要であるため製造プロセスが簡略化されるという効果が得られる。それに加えて、実施の形態２によれば、ガードリング領域４４も白金の熱拡散によって反転領域４３と同時に形成されるので、実施の形態１に比べてさらに製造プロセスが簡略化されるという効果が得られる。
【００４２】
なお、上述した実施の形態２では活性領域を単一の反転領域４３で構成する単純な構成としたが、これに限らない。たとえば図１８に示すように、活性領域の一部にＰ型の反転領域４３が設けられており、活性領域の残りの部分がＮ型のままとなっている構成でもよい。つまり、活性領域をリング状、ストライプ状またはドット状などの任意の微細パターンの反転領域４３で構成してもよい。この場合には、白金の熱拡散時に、活性領域を形成する領域の半導体表面に前記微細パターンの相補的なパターンをなす酸化膜を残しておけばよい。この構造は実施の形態１の半導体装置にも適用できる。
【００４３】
また、上述した実施の形態２では半導体基板２１上に半導体層２２をエピタキシャル成長させたウエハに素子を形成したが、これに限らない。たとえば図１９に示すように、半導体基板１４１として、上述したエピタキシャル成長させたウエハよりも安価であるため、たとえば不純物濃度が２×１０14ｃｍ-3で厚さが５００μｍのＦＺウエハを用いてもよい。この場合には、ＦＺウエハの表面にたとえば厚さが８００ｎｍの酸化膜４５を形成し、その酸化膜４５の一部を開口した後、半導体基板１４１を裏面側からたとえば６０μｍの厚さとなるように機械研磨する。その後、半導体基板１４１の裏面から白金を熱拡散させて、反転領域４３およびガードリング領域４４を形成する。
【００４４】
そして、必要に応じて、半導体基板１４１の裏面と裏面電極４７とを低抵抗で接触させるため、半導体基板１４１の裏面からＡｓ等のＮ型のドーパントをたとえば表面濃度が１×１０18ｃｍ-3以上となるように注入する。そして、表面電極４６および裏面電極４７を形成する。この構造は実施の形態１の半導体装置にも適用できる。
【００４５】
実施の形態３．
図２０は、本発明にかかる半導体装置を適用した力率改善回路の一例を示す回路図である。この力率改善回路は、本発明にかかる半導体装置、たとえば上述した実施の形態１または実施の形態２の構成のダイオード６１、ダイオード・ブリッジ６２およびスイッチング素子であるＭＯＳトランジスタ６３を備えている。符号６４は交流入力、符号６５はインダクタンス、符号６６はキャパシタをそれぞれ表す。
【００４６】
この力率改善回路において、トランジスタ６３がオン状態からオフ状態に切り替わると、インダクタンス６５に蓄積されたエネルギーを放出するため、ダイオード６１は導通状態となる。この導通状態のダイオード６１は、トランジスタ６３がオフ状態からオン状態に切り替わるときには逆バイアス状態となる。その際、ダイオード６１は、ダイオード６１に蓄積されている電荷がなくなるまで導通するため、その逆回復期間中は、負荷に流れる電流に加えて逆回復電流がダイオード６１に流れる。そのため、トランジスタ６３のターンオン初期には大きな電流が流れることになるが、上述したようにダイオード６１の逆回復電流が従来よりも大幅に小さいので、トランジスタ６３のターンオン初期時に流れる電流は従来よりも小さくなる。
【００４７】
また、逆回復電流が減少するときの時間変化と回路の浮遊インダクタンスにより電圧ノイズが発生し、その電圧ノイズが電源電圧に重畳されてトランジスタ６３およびダイオード６１に印加されることになるが、上述したように逆回復電流のピーク後の減衰率が従来よりも著しく小さいため、発生する電圧ノイズも極めて小さい。したがって、実施の形態３によれば、力率改善回路を構成する半導体素子の破壊や、回路の誤動作を防ぐことができる。
【００４８】
以上において本発明は、種々変更可能である。たとえば、白金はＰ型のシリコン半導体中でドナーとして機能するため、第１導電型をＰ型とし、第２導電型をＮ型としてもよい。この場合には、Ｐ型の半導体層の表面近傍にＮ型の反転領域が形成されることになる。
【００４９】
また、上記実施の形態においては、半導体領域の表面近傍にその内部よりも高濃度に白金をドープする方法として、表面からの白金の熱拡散（手法）を用いて説明したが、本発明はこの手法に限定されるものではない。たとえば、白金のイオンを注入する方法やシリコン結晶作成時におけるドーブ処理などであってもよい。
【００５０】
【発明の効果】
本発明によれば、白金の熱拡散によってできた第２導電型の反転領域と第１導電型の半導体領域とによりｐｎ接合部が形成されるため、従来よりもｐｎ接合部が浅くなり、ｐｎ接合部の位置と白金が有効に作用する位置とが一致する。したがって、高速でかつ十分なソフトリカバリー特性を具えたダイオードを構成する半導体装置が得られるという効果を奏する。
【図面の簡単な説明】
【図１】本発明の実施の形態１にかかる半導体装置の構造を示す縦断面図である。
【図２】半導体に熱拡散させた白金の深さ方向のプロファイルを説明するための模式図である。
【図３】酸化膜によって特定領域にのみ反転領域を形成した様子を示す半導体装置の縦断面図である。
【図４】白金の熱拡散温度と表面近傍領域のキャリア濃度分布との関係を示す特性図である。
【図５】白金の熱拡散後に熱処理をおこなう前とおこなった後でのキャリア濃度分布の変化を示す特性図である。
【図６】図１に示す半導体装置の製造途中における要部を示す縦断面図である。
【図７】図１に示す半導体装置の製造途中における要部を示す縦断面図である。
【図８】図１に示す半導体装置の製造途中における要部を示す縦断面図である。
【図９】図１に示す半導体装置の製造途中における要部を示す縦断面図である。
【図１０】図１に示す半導体装置の逆回復電流を示す波形図である。
【図１１】従来の半導体装置の逆回復電流を示す波形図である。
【図１２】本発明の実施の形態１にかかる半導体装置のＶＦとＩＲＰトレードオフ改善（従来構造との比較）を示す説明図である。
【図１３】本発明の実施の形態１にかかる半導体装置の他の例を示す縦断面図である。
【図１４】本発明の実施の形態２にかかる半導体装置の構造を示す縦断面図である。
【図１５】図１４に示す半導体装置の製造途中における要部を示す縦断面図である。
【図１６】図１４に示す半導体装置の製造途中における要部を示す縦断面図である。
【図１７】図１４に示す半導体装置の製造途中における要部を示す縦断面図である。
【図１８】本発明の実施の形態２にかかる半導体装置の他の例を示す縦断面図である。
【図１９】本発明の実施の形態２にかかる半導体装置のさらに他の例を示す縦断面図である。
【図２０】本発明にかかる半導体装置を適用した力率改善回路の一例を示す回路図である。
【図２１】従来の高速リカバリーダイオードの構成を示す縦断面図である。
【符号の説明】
２０，２５，４５ 酸化膜
２１，４１，１４１ 半導体基板（半導体領域）
２２，４２ 半導体層（半導体領域）
２３，４３ 反転領域
２４ ガードリング領域（不純物拡散領域）
２６，４６ 表面電極（第１の電極）
２７，４７ 裏面電極（第２の電極）
２８ 活性領域エッジ部（不純物拡散領域）
２９，４９ ｐｎ接合部
４４ ガードリング領域（第２の反転領域）[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device for a rectifying element using a pn junction and a manufacturing method thereof.
[0002]
[Prior art]
In general, a fast recovery diode is known as a semiconductor device used for high-frequency switching. This diode has a pn junction of a P-type semiconductor region and an N-type semiconductor region, and shortens the lifetime of carriers by diffusing heavy metals such as platinum as a lifetime killer.
[0003]
FIG. 21 is a longitudinal sectional view showing a configuration of a conventional fast recovery diode. This diode includes an N-type semiconductor substrate 11, an N-type semiconductor layer 12 having a carrier concentration lower than that of the semiconductor substrate 11, a P-type active region 13, a P-type guard ring region 14, an oxide film 15, a surface electrode 16, and A back electrode 17 is provided.
[0004]
The semiconductor layer 12 is formed on the semiconductor substrate 11 by epitaxial growth. The active region 13 and the guard ring region 14 are formed by patterning an oxide film laminated on the semiconductor layer 12 and ion-implanting P-type impurities using the oxide film as a mask. The surface of the semiconductor layer 12 is again covered with the oxide film 15 by the heat treatment after the ion implantation. However, the active region 13 is exposed by removing a part of the oxide film 15, and after the thermal diffusion of platinum, A surface electrode 16 is formed on the surface. The back electrode 17 is formed on the back surface of the semiconductor substrate 11.
[0005]
By the way, recently, the diode configured as described above may be used in a power factor correction circuit (PFC circuit). In general, a diode used in this application is required to have a soft recovery characteristic in which a reverse recovery current is small and a current decay rate after a peak value of a reverse current at the time of reverse recovery is small. The reason is that if the reverse recovery current is large, the turn-on loss of the MOS transistor or the like provided as a switching element in the power factor correction circuit and the element temperature increase, and if the attenuation factor is large, a large voltage noise is generated. Is superimposed on the power supply voltage and applied to a diode, a MOS transistor or the like, thereby causing element destruction and circuit malfunction.
[0006]
  Therefore, in the conventional pn junction diode shown in FIG. 21, the reverse recovery current is reduced by shortening the carrier lifetime by controlling the platinum diffusion condition. However, the forward voltage of the diode and the reverse recovery current are in a trade-off relationship.RiseInvite. Furthermore, the control of the platinum diffusion condition alone does not reduce the reverse current decay rate during reverse recovery, so that it cannot be said that sufficient soft recovery has been achieved. Therefore, in addition to the platinum concentration, the thickness of the semiconductor layer 12 and the anode carrier concentration are optimized. However, increasing the thickness of the semiconductor layer 12 causes an increase in the forward voltage, which worsens the trade-off. Do.
[0007]
[Problems to be solved by the invention]
In a pn junction diode in which platinum is diffused as a lifetime killer, platinum is piled up in a region with a depth of several μm near the surface of the diode, so that the effect of platinum is sufficient in the vicinity of a deeper pn junction. Is not demonstrated. Therefore, the above-described trade-off improvement is insufficient and there is a problem that the soft recovery characteristic is not improved so much. In order to sufficiently exhibit the effect of platinum in the vicinity of the pn junction, it is conceivable to increase the injection amount of platinum. However, in that case, not only the resistance of the N-type semiconductor layer is increased, but also the platinum concentration becomes too high in the P-type active region, thereby increasing the number of defects and increasing the leakage current.
[0008]
The present invention has been made in view of the above problems, and an object thereof is to provide a semiconductor device that constitutes a diode having high speed and sufficient soft recovery characteristics, and a method for manufacturing the same.
[0009]
[Means for Solving the Problems]
In order to achieve the above-mentioned object, the present invention reverses the portion near the surface not covered with the oxide film of the semiconductor region to the second conductivity type by doping platinum into the semiconductor region of the first conductivity type, A pn junction is formed by the inversion region of the second conductivity type and the semiconductor region of the first conductivity type. The depth of the pn junction is adjusted by controlling the temperature and time when platinum is thermally diffused.
[0010]
According to the present invention, since the pn junction is formed by the inversion region of the second conductivity type and the first conductivity type semiconductor region formed by doping of platinum, the pn junction becomes shallower than the conventional case, and the pn junction is reduced. The position of the part coincides with the position where platinum acts effectively.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the first conductivity type is N-type and the second conductivity type is P-type, for example, a semiconductor made of silicon.
[0012]
Embodiment 1 FIG.
FIG. 1 is a longitudinal sectional view showing the structure of the semiconductor device according to the first embodiment of the present invention. This semiconductor device includes an As (arsenic) -doped N-type semiconductor substrate 21, a P (phosphorus) -doped N-type semiconductor layer 22, a P-type inversion region 23, a P-type guard ring region 24, an oxide film 25, It has a front electrode 26, a back electrode 27, and an active region edge portion 28. For example, the thickness of the semiconductor substrate 21 is 300 μm and the impurity concentration is 2 × 10.19cm-3It is. For example, the thickness of the semiconductor layer 22 is 60 μm, and the impurity concentration is 2 × 10.14cm-3It is.
[0013]
A part of the surface of the semiconductor layer 22 is covered with an oxide film 25. The inversion region 23 is shallowly formed under the region not covered with the oxide film 25 on the surface of the semiconductor layer 22. The junction depth xj of the inversion region 23, that is, the depth of the pn junction is, for example, several μm. The inversion region 23 is formed by inverting the N-type semiconductor layer 22 to P-type by high-concentration platinum piled up in the vicinity of the surface of the semiconductor layer 22.
[0014]
In FIG. 1, the interface of the region whose conductivity type is inverted by the diffusion of platinum is indicated by a broken line (the same applies to other drawings). The interface indicated by the broken line corresponds to the pn junction 29 between the inversion region 23 and the semiconductor layer 22. The depth of the pn junction 29 varies depending on the thermal diffusion conditions of platinum and the subsequent heat treatment conditions. That is, the depth of the pn junction 29 can be adjusted by controlling the thermal diffusion conditions of platinum and the subsequent heat treatment conditions.
[0015]
The active region edge portion 28 is formed in a region on the surface side of the semiconductor layer 22 so as to surround the inversion region 23. The active region edge portion 28 is connected to the inversion region 23 and constitutes an active region together with the inversion region 23. The junction depth xj of the active region edge portion 28 is about 10 μm, which is deeper than the inversion region 23 (xj: several μm). Here, in order to achieve soft recovery, it is desirable that the active region has a shallow junction depth. However, generally, when the active region becomes thin, a breakdown voltage failure due to an increase in electric field at the edge portion tends to occur. In the present embodiment, by providing the active region edge portion 28 at the edge portion of the active region, a sufficient breakdown voltage is ensured while the junction depth of the active region is shallower than the conventional one.
[0016]
The guard ring region 24 is not particularly limited in the region on the surface side of the semiconductor layer 22 so as to surround the inversion region 23 and the active region edge portion 28. For example, the guard ring region 24 is formed in a single ring shape. The junction depth xj of the guard ring region 24 is about 10 μm. The guard ring region 24 may be double or more. The surface electrode 26 is formed in contact with the surfaces of the inversion region 23 and the active region edge portion 28. The back electrode 27 is formed in contact with the back surface of the semiconductor substrate 21.
[0017]
Here, the fact that the inversion region 23 is formed in the region near the surface of the semiconductor layer 22 by pile-up of platinum will be briefly described with reference to FIG. FIG. 2 is a schematic diagram for explaining a profile in the depth direction of platinum thermally diffused in a semiconductor.
[0018]
For example, an As-doped N-type semiconductor substrate 21 (impurity concentration: 2 × 1019cm-3, Thickness: 300 μm) and P-doped N-type semiconductor layer 22 (impurity concentration: 2 × 1014cm-3, Thickness: 60 μm). Then, a paste containing 1% by weight of platinum is applied to the back surface of the semiconductor substrate 21 or the surface of the semiconductor layer 22, and heat treatment is performed at 920 ° C. for 3 hours. Then, platinum piles up and is unevenly distributed on the back surface of the semiconductor substrate 21 and the surface of the semiconductor layer 22. At that time, platinum acts as an acceptor, and a region of several μm from the surface of the semiconductor layer 22 having a low impurity concentration is inverted to P-type.
[0019]
In the vicinity of the surface of the N-type semiconductor layer 22, the surface of the semiconductor layer 22 is not covered with the oxide film 25 as shown in FIG. That is, an oxide film 25 having a thickness of, for example, 900 nm is formed on the surface of the N-type semiconductor layer 22, and the central portion thereof is removed by a photolithography technique to expose the semiconductor layer 22. When a paste containing 1% by weight of platinum is applied to the back surface of the semiconductor substrate 21 or the exposed surface of the semiconductor layer 22 and heat treatment is performed at 920 ° C. for 3 hours, the semiconductor layer 22 is covered with the oxide film 25. Platinum is unevenly distributed in a high concentration only in the unexposed area and is inverted to P-type. This is presumed to be because platinum diffused in the vicinity of the surface of the semiconductor layer 22 is taken into the oxide film 25, so that P-type inversion does not occur in the region covered with the oxide film 25.
[0020]
Next, it will be described that the depth of the pn junction 29 can be adjusted by controlling the thermal diffusion conditions of platinum and the subsequent heat treatment conditions. FIG. 4 is a characteristic diagram showing the relationship between the thermal diffusion temperature of platinum and the carrier concentration distribution in the vicinity of the surface in a vertical cross section (cross section indicated by a one-dot chain line in FIG. 3) passing through the approximate center of the inversion region 23. In FIG. 4, the valley of each profile corresponds to the depth of the pn junction.
[0021]
According to FIG. 4, for example, for a certain thermal diffusion time, the junction depth is about 1 μm at a diffusion temperature of 930 ° C., about 10 μm at 970 ° C., and about 25 μm at 1000 ° C. Further, it is known that the profile of platinum is distributed from the surface of the semiconductor to the inside as the diffusion time becomes longer (J. Appl. Phys., Vol. 61, No. 3 1055). Therefore, the junction depth becomes deeper as the diffusion time becomes longer even at the same temperature.
[0022]
In the semiconductor device having the configuration shown in FIG. 1, when the front electrode 26 and the back electrode 27 are formed, a heat treatment is performed at 500 ° C. for one hour in order to stabilize the contact resistance of the electrodes. The depth of the pn junction 29 changes. FIG. 5 is a characteristic diagram showing changes in carrier concentration distribution before and after heat treatment at 500 ° C. for 1 hour for a semiconductor device in which platinum is thermally diffused at 930 ° C. FIG. The junction depth before heat treatment is 1 μm, whereas the junction depth after heat treatment is 2 μm. As described above, the junction depth between the N-type semiconductor layer 22 and the P-type inversion region 23 can be controlled by the thermal diffusion condition of platinum and the subsequent heat treatment condition.
[0023]
Next, a method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. First, the semiconductor layer 22 is epitaxially grown on the semiconductor substrate 21. Subsequently, a thermal oxide film 20 having a thickness of, for example, 900 nm is formed on the surface of the semiconductor layer 22. Then, a portion of the oxide film corresponding to the formation region of the active region edge portion 28 and the guard ring region 24 is removed, for example, in a ring shape by photolithography and etching. The state up to this point is shown in FIG.
[0024]
Subsequently, B (boron) is ion-implanted into the semiconductor layer 22 using the remaining portion of the oxide film 20 as a mask. The dose at this time is 1 × 1014cm-2And the acceleration voltage is 50 kV. Thereafter, heat treatment is performed at 1200 ° C. for 7 hours to form the active region edge portion 28 and the guard ring region 24. At this time, an oxide film having a thickness of, for example, 400 nm is formed at the same time, and the entire wafer surface is covered with the oxide film 25. The state up to this point is shown in FIG.
[0025]
Subsequently, a portion of the oxide film 25 that forms the active region is removed by photolithography and etching. In this state, a paste containing 1% by weight of platinum is applied to the back surface of the semiconductor substrate 21 or the semiconductor surface of the region forming the active region, and heat treatment is performed at 920 ° C. for 3 hours. As a result, the vicinity of the surface of the active region of the semiconductor layer 22 is inverted to the P type, and the inverted region 23 is formed. The state up to this point is shown in FIG.
[0026]
Subsequently, for example, AlSi having a thickness of 3 μm is laminated on the wafer surface by sputtering. Then, the AlSi layer is patterned into a desired shape by photolithography and etching. After that, N2Heat treatment is performed in an atmosphere at 500 ° C. for 1 hour to form a low-resistance surface electrode 26 in contact with the inversion region 23 and the active region edge portion 28. The state up to this point is shown in FIG. The surface electrode 26 may be formed by vacuum deposition of pure Al.
[0027]
Finally, Ti, Ni, and Au are stacked on the back surface of the semiconductor substrate 21 by vacuum deposition to form the back electrode 27, whereby the semiconductor device is completed and the state shown in FIG. 1 is obtained. For example, the thickness of Ti is 0.7 μm, the thickness of Ni is 0.3 μm, and the thickness of Au is 0.1 μm.
[0028]
Next, the results of measuring reverse recovery characteristics of the semiconductor device of the present embodiment shown in FIG. 1 and the semiconductor device of the conventional structure shown in FIG. 21 will be described. FIG. 10 is a waveform diagram showing the reverse recovery current of the semiconductor device of the present embodiment, and FIG. 11 is a waveform diagram showing the reverse recovery current of the conventional semiconductor device.
[0029]
In the semiconductor device of the present embodiment, the peak value of the reverse recovery current is about 2.3A. On the other hand, the peak value of the reverse recovery current of the conventional semiconductor device is about 4.6A. Therefore, it can be seen that the peak value of the reverse recovery current of the present embodiment is about 50% of the conventional value, which is greatly reduced. It can also be seen that the reverse recovery current attenuation after the peak is significantly softened compared to the conventional waveform (FIG. 11).
[0030]
  Figure 12 shows the forward powerPressureThe results of VF and reverse recovery current peak value IRP are shown. In FIG. 12, the trade-off by adjusting the Pt diffusion condition in the conventional structure is all hard recovery, and VF is increased for softening, that is, the trade-off is shifted to the right. Therefore, it can be seen that the result of the first embodiment of the present invention improves the trade-off compared to the trade-off by adjusting the Pt diffusion condition in the conventional structure.
[0031]
According to the first embodiment, platinum is thermally diffused in the N-type semiconductor layer 22 so that the region near the surface of the semiconductor layer 22 is inverted to P-type, and the P-type inversion region 23 and the N-type inversion region 23 are inverted. Since a shallow pn junction is formed with the semiconductor layer 22, the pn junction is formed at a position where the effect of platinum is exhibited without increasing the platinum concentration more than necessary. Therefore, a semiconductor device that constitutes a diode having high speed and sufficient soft recovery characteristics can be obtained.
[0032]
In addition, since the active region can be formed shallow, the trade-off relationship between the forward voltage of the diode and the reverse recovery current can be improved. Further, since it is not necessary to form a pn junction by injecting a P-type impurity into the N-type semiconductor layer 22 to form a P-type semiconductor region as in the prior art, the manufacturing process is simplified.
[0033]
In the first embodiment described above, the electrodes 26 and 27 are formed following the thermal diffusion of platinum. However, the present invention is not limited to this. For example, the back surface of the semiconductor substrate 1 may be polished so that the thickness of the entire semiconductor device is about 300 μm after the thermal diffusion of platinum and before the formation of the electrodes 26 and 27. If it does so, a thermal radiation characteristic will improve.
[0034]
In the first embodiment described above, the inversion region 23 and the active region edge portion 28 constitute the active region, but the present invention is not limited to this. In the case where such a high breakdown voltage is not required, the active region may be composed of only the inversion region 23 without providing the active region edge portion 28 as shown in FIG. In the example shown in FIG. 13, the guard ring regions 24 are provided twice.
[0035]
Embodiment 2. FIG.
FIG. 14 is a longitudinal sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention. This semiconductor device includes an As (arsenic) -doped N-type semiconductor substrate 41, a P (phosphorus) -doped N-type semiconductor layer 42, a P-type inversion region 43, a P-type guard ring region 44, an oxide film 45, A front electrode 46 and a back electrode 47 are provided. For example, the thickness of the semiconductor substrate 41 is 500 μm, and the impurity concentration is 2 × 10.19cm-3It is. For example, the thickness of the semiconductor layer 42 is 60 μm, and the impurity concentration thereof is 2 × 10.14cm-3It is.
[0036]
A part of the surface of the semiconductor layer 42 is covered with an oxide film 45. The inversion region 43 is shallowly formed below the region not covered with the oxide film 45 on the surface of the semiconductor layer 42. The junction depth (depth of the pn junction 49) xj of the inversion region 43 is, for example, several μm. The guard ring region 44 is not particularly limited in the region on the surface side of the semiconductor layer 42 so as to surround the inversion region 43, but is formed in a double ring shape, for example. The junction depth xj of the guard ring region 44 is the same as that of the inversion region 43. The guard ring region 44 may be provided in a single layer or a triple layer or more. The surface electrode 46 is formed in contact with the surface of the inversion region 43. The back electrode 47 is formed in contact with the back surface of the semiconductor substrate 41.
[0037]
Here, the inversion region 43 and the guard ring region 44 are formed by inverting the N-type semiconductor layer 42 to P-type by high-concentration platinum piled up in the vicinity of the surface of the semiconductor layer 42. Therefore, the junction depth of the inversion region 43 and the guard ring region 44 can be controlled by controlling the thermal diffusion conditions of platinum and the subsequent heat treatment conditions as in the first embodiment.
[0038]
Next, a method for manufacturing the semiconductor device shown in FIG. 14 will be described with reference to FIGS. First, in the same manner as in the first embodiment, the semiconductor layer 42 and the thermal oxide film 45 having a thickness of, for example, 900 nm are sequentially formed on the semiconductor substrate 41. Then, a part of the oxide film 45 is removed by photolithography technique and etching to expose the semiconductor surface in the formation region of the inversion region 43 and the guard ring region 44. The state up to here is shown in FIG.
[0039]
Subsequently, a paste containing 1% by weight of platinum is applied to the back surface of the semiconductor substrate 41 or the semiconductor surface exposed by removing the oxide film 45, and heat treatment is performed at 920 ° C. for 3 hours. As a result, the vicinity of the exposed surface of the semiconductor layer 42 is inverted to the P-type, and the inversion region 43 and the guard ring region 44 are formed. The state up to this point is shown in FIG.
[0040]
Then, a low-resistance surface electrode 46 in contact with the inversion region 43 is formed in the same manner as in the first embodiment. The state up to this point is shown in FIG. Finally, the back electrode 47 is formed on the back surface of the semiconductor substrate 41 to complete the semiconductor device, and the state shown in FIG. 14 is obtained.
[0041]
According to the second embodiment described above, as in the first embodiment, the effect of obtaining a semiconductor device that constitutes a diode having a high speed and sufficient soft recovery characteristics and the step of implanting a P-type impurity are unnecessary. As a result, the manufacturing process can be simplified. In addition, according to the second embodiment, the guard ring region 44 is also formed simultaneously with the inversion region 43 by the thermal diffusion of platinum, so that the manufacturing process is further simplified compared to the first embodiment. can get.
[0042]
In the second embodiment described above, the active region is configured by a single inversion region 43. However, the present invention is not limited to this. For example, as shown in FIG. 18, a P-type inversion region 43 may be provided in a part of the active region, and the remaining part of the active region may remain N-type. In other words, the active region may be constituted by an inversion region 43 having an arbitrary fine pattern such as a ring shape, a stripe shape, or a dot shape. In this case, an oxide film having a complementary pattern to the fine pattern may be left on the semiconductor surface in the region where the active region is formed during the thermal diffusion of platinum. This structure can also be applied to the semiconductor device of the first embodiment.
[0043]
In the second embodiment described above, the element is formed on the wafer obtained by epitaxially growing the semiconductor layer 22 on the semiconductor substrate 21, but the present invention is not limited to this. For example, as shown in FIG. 19, since the semiconductor substrate 141 is cheaper than the above-mentioned epitaxially grown wafer, the impurity concentration is 2 × 10, for example.14cm-3Alternatively, an FZ wafer having a thickness of 500 μm may be used. In this case, an oxide film 45 having a thickness of, for example, 800 nm is formed on the surface of the FZ wafer, and after opening a part of the oxide film 45, the semiconductor substrate 141 is formed to have a thickness of, for example, 60 μm from the back surface side. Polish mechanically. Thereafter, platinum is thermally diffused from the back surface of the semiconductor substrate 141 to form the inversion region 43 and the guard ring region 44.
[0044]
Then, if necessary, in order to make the back surface of the semiconductor substrate 141 and the back surface electrode 47 come into contact with low resistance, an N-type dopant such as As is applied from the back surface of the semiconductor substrate 141 to a surface concentration of, for example, 1 × 10.18cm-3Inject so that it becomes the above. Then, the front electrode 46 and the back electrode 47 are formed. This structure can also be applied to the semiconductor device of the first embodiment.
[0045]
Embodiment 3 FIG.
FIG. 20 is a circuit diagram showing an example of a power factor correction circuit to which the semiconductor device according to the present invention is applied. The power factor correction circuit includes a semiconductor device according to the present invention, for example, the diode 61, the diode bridge 62, and the MOS transistor 63 as a switching element having the configuration of the first or second embodiment described above. Reference numeral 64 represents an AC input, reference numeral 65 represents an inductance, and reference numeral 66 represents a capacitor.
[0046]
In this power factor correction circuit, when the transistor 63 is switched from the on state to the off state, the energy stored in the inductance 65 is released, so that the diode 61 becomes conductive. The diode 61 in the conductive state is in a reverse bias state when the transistor 63 is switched from the off state to the on state. At this time, since the diode 61 is conducted until the electric charge accumulated in the diode 61 is exhausted, a reverse recovery current flows to the diode 61 in addition to the current flowing to the load during the reverse recovery period. Therefore, a large current flows in the early stage of turning on of the transistor 63. However, as described above, the reverse recovery current of the diode 61 is significantly smaller than that in the prior art. Become.
[0047]
In addition, voltage noise is generated due to the time change when the reverse recovery current decreases and the floating inductance of the circuit, and the voltage noise is superimposed on the power supply voltage and applied to the transistor 63 and the diode 61. Thus, since the decay rate after the peak of the reverse recovery current is significantly smaller than the conventional one, the generated voltage noise is extremely small. Therefore, according to the third embodiment, it is possible to prevent the destruction of the semiconductor element constituting the power factor correction circuit and the malfunction of the circuit.
[0048]
In the above, the present invention can be variously changed. For example, since platinum functions as a donor in a P-type silicon semiconductor, the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, an N-type inversion region is formed near the surface of the P-type semiconductor layer.
[0049]
In the above embodiment, the method of doping platinum in the vicinity of the surface of the semiconductor region at a higher concentration than the inside of the semiconductor region has been described using the thermal diffusion (method) of platinum from the surface. It is not limited to the method. For example, a method of implanting platinum ions or a dove process when forming a silicon crystal may be used.
[0050]
【The invention's effect】
According to the present invention, the pn junction is formed by the second conductivity type inversion region and the first conductivity type semiconductor region formed by the thermal diffusion of platinum. The position of the junction matches the position where platinum effectively acts. Therefore, it is possible to obtain a semiconductor device that constitutes a diode having high speed and sufficient soft recovery characteristics.
[Brief description of the drawings]
1 is a longitudinal sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram for explaining a profile in the depth direction of platinum thermally diffused in a semiconductor.
FIG. 3 is a vertical cross-sectional view of a semiconductor device showing a state where an inversion region is formed only in a specific region by an oxide film.
FIG. 4 is a characteristic diagram showing the relationship between the thermal diffusion temperature of platinum and the carrier concentration distribution in the region near the surface.
FIG. 5 is a characteristic diagram showing changes in carrier concentration distribution before and after heat treatment after thermal diffusion of platinum.
6 is a longitudinal sectional view showing a main part in the course of manufacturing the semiconductor device shown in FIG. 1. FIG.
7 is a longitudinal sectional view showing a main part in the course of manufacturing the semiconductor device shown in FIG. 1; FIG.
8 is a longitudinal sectional view showing a main part in the course of manufacturing the semiconductor device shown in FIG. 1;
9 is a longitudinal sectional view showing a main part in the course of manufacturing the semiconductor device shown in FIG. 1;
10 is a waveform chart showing a reverse recovery current of the semiconductor device shown in FIG.
FIG. 11 is a waveform diagram showing a reverse recovery current of a conventional semiconductor device.
FIG. 12 is an explanatory diagram showing VF and IRP trade-off improvement (comparison with a conventional structure) of the semiconductor device according to the first embodiment of the present invention;
FIG. 13 is a longitudinal sectional view showing another example of the semiconductor device according to the first embodiment of the present invention;
FIG. 14 is a longitudinal sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention;
15 is a longitudinal sectional view showing the main parts in the course of manufacturing the semiconductor device shown in FIG. 14;
16 is a longitudinal sectional view showing a main part in the course of manufacturing the semiconductor device shown in FIG. 14;
17 is a longitudinal sectional view showing a main part in the course of manufacturing the semiconductor device shown in FIG. 14;
FIG. 18 is a longitudinal sectional view showing another example of the semiconductor device according to the second embodiment of the present invention;
FIG. 19 is a longitudinal sectional view showing still another example of the semiconductor device according to the second embodiment of the present invention;
FIG. 20 is a circuit diagram showing an example of a power factor correction circuit to which the semiconductor device according to the invention is applied.
FIG. 21 is a longitudinal sectional view showing a configuration of a conventional fast recovery diode.
[Explanation of symbols]
20, 25, 45 Oxide film
21, 41, 141 Semiconductor substrate (semiconductor region)
22, 42 Semiconductor layer (semiconductor region)
23, 43 Inversion area
24 Guard ring region (impurity diffusion region)
26, 46 Surface electrode (first electrode)
27, 47 Back electrode (second electrode)
28 Active region edge (impurity diffusion region)
29,49 pn junction
44 Guard ring area (second inversion area)

Claims (12)

シリコン半導体からなる第１導電型の半導体領域と、
前記半導体領域の表面層に形成され主電流が流れる活性領域と、
前記活性領域の外周にて前記半導体領域の表面上に形成され、前記活性領域を露出する開口部を有する酸化膜と、
前記活性領域の、前記酸化膜の開口部に露出された表面近傍にその内部よりも高濃度に白金がドープされてなる第２導電型の反転領域と、
前記半導体領域と前記反転領域とからなるｐｎ接合部と、を具備し、
前記酸化膜の、前記半導体領域に接する側の部分には白金が取り込まれていることを特徴とする半導体装置。A first conductivity type semiconductor region made of a silicon semiconductor;
An active region formed in a surface layer of the semiconductor region and through which a main current flows;
An oxide film formed on the surface of the semiconductor region at an outer periphery of the active region and having an opening exposing the active region;
An inversion region of a second conductivity type formed by doping platinum in the active region near the surface exposed at the opening of the oxide film at a higher concentration than the inside thereof;
A pn junction portion comprising the semiconductor region and the inversion region,
A semiconductor device, wherein platinum is taken into a portion of the oxide film on the side in contact with the semiconductor region. 前記ｐｎ接合部に順方向バイアスの電圧が印加され順方向電流が流れることを特徴とする請求項１に記載の半導体装置。  2. The semiconductor device according to claim 1, wherein a forward bias voltage is applied to the pn junction and a forward current flows. 前記反転領域と接する第１の電極と、
前記半導体領域と接する第２の電極と、
前記反転領域を一重または二重以上に囲み、かつ前記ｐｎ接合部よりも深い位置で前記半導体領域と接合する第２導電型の不純物拡散領域と、
をさらに具備することを特徴とする請求項１または２に記載の半導体装置。A first electrode in contact with the inversion region;
A second electrode in contact with the semiconductor region;
A second conductivity type impurity diffusion region that surrounds the inversion region in a single layer or a double layer and is bonded to the semiconductor region at a position deeper than the pn junction;
The semiconductor device according to claim 1, further comprising: 前記反転領域を二重以上に囲む前記不純物拡散領域のうち最内周の不純物拡散領域は、前記反転領域に接続するとともに前記第１の電極と接していることを特徴とする請求項３に記載の半導体装置。  4. The innermost impurity diffusion region of the impurity diffusion regions surrounding the inversion region more than once is connected to the inversion region and is in contact with the first electrode. Semiconductor device. 前記反転領域と接する第１の電極と、
前記半導体領域と接する第２の電極と、
前記反転領域を一重または二重以上に囲み、かつ前記半導体領域の表面近傍にその内部よりも高濃度にドープされた白金により第２導電型に反転してなる第２の反転領域をさらに具備することを特徴とする請求項１または２に記載の半導体装置。A first electrode in contact with the inversion region;
A second electrode in contact with the semiconductor region;
The semiconductor device further includes a second inversion region that surrounds the inversion region in a single layer or a double layer or more and is inverted to the second conductivity type by platinum doped at a higher concentration than the inside in the vicinity of the surface of the semiconductor region. The semiconductor device according to claim 1, wherein: 前記第１の電極は前記半導体領域とも接していることを特徴とする請求項３〜５のいずれか一つに記載の半導体装置。  The semiconductor device according to claim 3, wherein the first electrode is in contact with the semiconductor region. シリコン半導体からなる第１導電型の半導体領域の第１の主面の一部を酸化膜で被覆する工程と、
前記半導体領域の表面近傍にその内部よりも高濃度に白金をドープし、当該白金を前記酸化膜に取り込ませることで前記第１の主面の露出部分の表面近傍領域に選択的に第２導電型の反転領域を形成する工程と、
前記反転領域と接する第１の電極、および前記半導体領域の第２の主面と接する第２の電極をそれぞれ形成する工程と、
を含むことを特徴とする半導体装置の製造方法。Covering a part of the first main surface of the first conductivity type semiconductor region made of a silicon semiconductor with an oxide film;
By doping platinum in the vicinity of the surface of the semiconductor region at a higher concentration than the inside thereof and incorporating the platinum into the oxide film, the second conductive is selectively applied to the surface vicinity region of the exposed portion of the first main surface. Forming a mold inversion region;
Forming a first electrode in contact with the inversion region and a second electrode in contact with the second main surface of the semiconductor region;
A method for manufacturing a semiconductor device, comprising: 前記半導体領域の第１の主面の露出部分、または前記半導体領域の第２の主面から白金を熱拡散させ、前記酸化膜の、前記半導体領域に接する部分に前記白金を取り込ませることによって、前記半導体領域の第１の主面の露出部分の表面近傍にその内部よりも高濃度に白金を選択的にドープすることを特徴とする請求項７に記載の半導体装置の製造方法。  By thermally diffusing platinum from the exposed portion of the first main surface of the semiconductor region or the second main surface of the semiconductor region, and by incorporating the platinum into the portion of the oxide film that contacts the semiconductor region, The method of manufacturing a semiconductor device according to claim 7, wherein platinum is selectively doped in the vicinity of the surface of the exposed portion of the first main surface of the semiconductor region at a higher concentration than the inside thereof. シリコン半導体からなる第１導電型の半導体領域の第１の主面の一部を酸化膜で被覆する工程と、
前記酸化膜をマスクとして前記半導体領域に第２導電型の不純物イオンを注入し、熱処理をおこなって第２導電型の不純物拡散領域を形成するとともに、前記第１の主面を酸化膜で被覆する工程と、
前記不純物拡散領域で囲まれた領域の前記酸化膜の一部を除去する工程と、
前記半導体領域の表面近傍にその内部よりも高濃度に白金をドープし、前記不純物拡散領域で囲まれた領域の前記第１の主面の露出部分の表面近傍領域に、前記白金を前記酸化膜に取り込ませることで前記不純物拡散領域よりも浅い接合の第２導電型の反転領域を選択的に形成する工程と、
前記反転領域と接する第１の電極、および前記半導体領域の第２の主面と接する第２の電極をそれぞれ形成する工程と、
を含むことを特徴とする半導体装置の製造方法。Covering a part of the first main surface of the first conductivity type semiconductor region made of a silicon semiconductor with an oxide film;
Impurity ions of the second conductivity type are implanted into the semiconductor region using the oxide film as a mask, heat treatment is performed to form a second conductivity type impurity diffusion region, and the first main surface is covered with the oxide film. Process,
Removing a portion of the oxide film in a region surrounded by the impurity diffusion region;
In the vicinity of the surface of the semiconductor region, platinum is doped at a higher concentration than the inside thereof, and in the region surrounded by the impurity diffusion region, the platinum is added to the oxide film in the region near the surface of the exposed portion of the first main surface. Selectively forming an inversion region of the second conductivity type having a junction shallower than the impurity diffusion region,
Forming a first electrode in contact with the inversion region and a second electrode in contact with the second main surface of the semiconductor region ;
A method for manufacturing a semiconductor device, comprising: 前記不純物拡散領域で囲まれた領域の前記第１の主面の露出部分、または前記半導体領域の第２の主面から白金を熱拡散させ、前記酸化膜の、前記半導体領域に接する部分に前記白金を取り込ませることによって、前記半導体領域の第１の主面の露出部分の表面近傍にその内部よりも高濃度の白金を選択的にドープすることを特徴とする請求項９に記載の半導体装置の製造方法。  Platinum is thermally diffused from the exposed portion of the first main surface of the region surrounded by the impurity diffusion region, or from the second main surface of the semiconductor region, and the portion of the oxide film in contact with the semiconductor region is 10. The semiconductor device according to claim 9, wherein platinum is selectively doped near the surface of the exposed portion of the first main surface of the semiconductor region with a higher concentration of platinum than the inside thereof by incorporating platinum. Manufacturing method. 白金の拡散前に、前記不純物拡散領域で囲まれた領域の前記酸化膜の一部を除去する際に、前記不純物拡散領域のうち最内周の不純物拡散領域が露出するように前記酸化膜を除去し、
また、前記第１の電極を最内周の前記不純物拡散領域と接するように形成することを特徴とする請求項１０に記載の半導体装置の製造方法。Before the diffusion of platinum, when removing a part of the oxide film in the region surrounded by the impurity diffusion region, the oxide film is formed so that the innermost impurity diffusion region of the impurity diffusion region is exposed. Remove,
The method of manufacturing a semiconductor device according to claim 10, wherein the first electrode is formed so as to be in contact with the innermost peripheral impurity diffusion region. 前記白金を熱拡散させる際の温度および時間を制御して前記反転領域の形成深さを調節することを特徴とする請求項７〜１１のいずれか一つに記載の半導体装置の製造方法。  The method for manufacturing a semiconductor device according to claim 7, wherein the formation depth of the inversion region is adjusted by controlling a temperature and a time when the platinum is thermally diffused.
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