JPH04314367A - Planar diode and its manufacture - Google Patents

Abstract

PURPOSE:To improve high frequency characteristics by decentralizingly forming a plurality of recessed parts having a specified second depth which is shallower than a first depth in a part apart from a peripheral edge part of a high impurity concentration region surface of a second conductivity type. CONSTITUTION:A silicon substrate consisting of an n<->-layer 1 and an n<+>-layer 2 is used and a 20 to 25mum-deep p<->-region 3 of a surface impurity concentration of 10<18> to 10<19>/cm<3> is formed by diffusion and introduction of impurities from an opening part of an oxide film 4 formed on a surface. Simultaneously, two p<+>-guard rings 5 are formed by diffusion and introduction of impurities from an opening part of an oxide film. Thereafter, an oxide film is formed all over again and etching is carried out from a surface of a p<+>-region 3; thereby, a recessed part 8 is formed making a depletion layer extending from a p-n junction with the n<->-layer 1 remain by about 6mum width when a reverse voltage of a rated voltage of 1000V or more is applied. Thereafter, Al is deposit- patterned on a surface of the region 3 to form an anode electrode 6 in contact with an inner side of the recessed part 8 and an Al cathode electrode 7 is formed.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] The present invention is directed to a P layer in which there are high impurity concentration layers of different conductivity types sandwiching a low impurity concentration layer.
The present invention relates to a planar diode having an IN structure and a method for manufacturing the same.

0002

[Prior Art] A diode having a large-capacity, high-voltage PIN structure is manufactured by diffusing different impurities from both sides of a first conductivity type, low impurity concentration semiconductor substrate. It is generally manufactured by forming layers. In the case of a planar type, a second conductivity type high impurity concentration diffusion layer is formed by impurity diffusion from an opening in the oxide film. FIG. 2 shows such a planar diode, showing an opening in an oxide film 4 formed on the surface of an n- layer 1 of a silicon substrate, which has an n- layer 1 with low impurity concentration and high resistance and an n+ layer 2 with high impurity concentration. A p+ region 3 with a high impurity concentration is formed by diffusion of acceptors from the substrate. Furthermore, in order to improve the breakdown voltage, an annular p+ guard ring 5 surrounding the p+ region is formed when the p+ region 3 is formed. Then, an anode electrode 6 is brought into contact with the p+ region 3, and a cathode electrode 7 is brought into contact with the n+ layer 2. In this case, increasing the depth of the p+ region 3 to about 20 to 25 μm means that when a reverse voltage is applied to this diode, the p+
This is effective in providing a margin for the depletion layer extending from the PN junction between region 3 and n- layer 1 into p+ region 3, and in preventing the influence of surface mobile ions from affecting the PN junction. .

On the other hand, the important things when operating a diode in a high frequency region are (1) reducing the on-state voltage to reduce steady-state loss, (2) shortening the reverse recovery time to reduce switching loss, (3) Reverse current during reverse recovery may be reduced. In order to simultaneously satisfy these requirements, in the case of the structure shown in FIG. 2, it is effective to make the diffusion depth of p+ region 3 shallow and to lower the impurity concentration. This reduces the total amount of impurities in the p+ region 3, which reduces the amount of holes injected from the p+ region 3 into the n- layer 1 when turned on, shortening the reverse recovery time and reducing the reverse recovery current. be able to.

0004

However, several problems arise when the p+ region 3 of the high breakdown voltage planar diode as shown in FIG. 2 is made shallower and its impurity concentration is lowered. That is, if p+ region 3 is made shallow,
The radius of curvature of the PN junction at the peripheral edge 31 at the bottom of the p+ diffusion region becomes smaller, and the concentration of the electric field becomes stronger, which is disadvantageous for increasing the breakdown voltage. Further, lowering the impurity concentration of the p+ region 3 is greatly affected by the surface, and the stability of the reverse breakdown voltage characteristics decreases. For this reason, in the past, emphasis was placed on high voltage characteristics,
The reverse recovery property had to be sacrificed.

An object of the present invention is to solve the above-mentioned problems and provide a planar diode that has high breakdown voltage characteristics and is suitable for operation in a high frequency region, and a method for manufacturing the same.

[0006]

[Means for Solving the Problems] In order to achieve the above object, the present invention provides a first conductivity type high impurity concentration layer on one side of the first conductivity type low impurity concentration layer, and a first conductivity type high impurity concentration layer on the other side. In a diode having a semiconductor body provided with a second conductivity type high impurity concentration diffusion region having a predetermined first depth from a predetermined portion of the surface, the periphery of the surface of the second conductivity type high impurity concentration region. It is assumed that a plurality of recesses having a predetermined second depth shallower than the first depth are formed in a distributed manner in a portion remote from the first depth. One or more annular second conductivity type high impurity concentration regions having a substantially first depth are formed outside the second conductivity type high impurity concentration regions at intervals, surrounding the regions. It is effective to Further, the method for manufacturing a planar diode of the present invention includes a step of forming a semiconductor body in which a first conductivity type low impurity concentration layer and a high impurity concentration layer are laminated, and a step of forming a semiconductor body in which a first conductivity type low impurity concentration layer and a high impurity concentration layer are stacked. introducing and diffusing impurities from a predetermined portion of the surface to form a second conductivity type high impurity concentration region having a predetermined first depth;
etching a plurality of parts of the surface of the high impurity concentration region to form a recess having a predetermined second depth shallower than the first depth, and contacting the surface of the high impurity concentration layer of the first conductivity type. The method includes a step of providing an electrode, and a step of providing an electrode in contact with the surface of the second conductivity type high impurity concentration region including the inner surface of the recess.

[0007]

[Effect] The diffusion region of the second conductivity type with a high impurity concentration is deepened to make it less susceptible to the influence of the surface on the PN junction between it and the resistance layer of the first conductivity type, and the radius of curvature of the periphery of the bottom of the region is reduced. Even if it is made larger and can stably exhibit high breakdown voltage characteristics, by forming a recess in the high-concentration surface area of the diffusion region and reducing the total amount of impurities by that amount, reverse recovery can be prevented during reverse recovery. The time is short and the reverse recovery current is small.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a planar type high voltage diode according to an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. Similar to the conventional planar diode shown in FIG. 2, this diode uses a silicon substrate consisting of an n- layer 1 and an n+ layer 2, and the surface impurities are diffused and introduced through the opening of the oxide film 4 formed on the surface. Concentration 1
018-19/cm3, p+ depth of 20-25 μm
Region 3 was formed, and at the same time, two p+ guard rings 5 were formed by diffusion and introduction of impurities from the opening of the oxide film. After that, an oxide film is again formed on the entire surface, and by making an opening and etching from the surface of the p+ region 3, when a reverse voltage of rated withstand voltage of 1000 V or more is applied, the oxide film is formed on the entire surface. The recess 8 was formed leaving a width of about 6 μm in the depletion layer extending from the PN junction. Thereafter, Al was deposited on the surface of the p+ region 3 and patterned to form the anode electrode 6 so as to contact the inner surface of the recess 8.
This was completed by forming an Al cathode electrode 7 in contact with the n+ layer 2.

FIGS. 3, 4, and 5 show examples of the shape of the recess 8 formed on the surface of the anode region 3. FIG. In the case of FIG. 3, the shape is a strip, in the case of FIG. 4, it is in the shape of a lattice, and in the case of FIG.

[0010] Such a PIN structure planar type high voltage diode satisfies the rated voltage characteristics and is superior to the conventional 80
% of the reverse recovery time, and can now operate in the high frequency range. Furthermore, similar effects were obtained using diodes with reversed conductivity types.

[0011]

According to the present invention, the high impurity concentration surface layer of the second conductivity type high impurity concentration region formed by diffusion from the surface of the first conductivity type low impurity concentration layer is partially removed. By forming the concave portion, the total amount of impurities could be reduced without reducing the diffusion depth of the high impurity concentration region or lowering the diffusion concentration. As a result, the on-voltage is low, and the radius of curvature at the bottom edge of the high impurity concentration region is large, so the concentration of electric field is weak, and the influence of mobile ions on the surface on the PN junction is small, ensuring high breakdown voltage characteristics. By reducing the amount of impurities, it has become possible to easily manufacture planar diodes with short reverse recovery time, small reverse recovery current, and excellent high-frequency operating characteristics. Of course, additionally providing a guard ring is effective in improving pressure resistance.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a planar high voltage diode according to an embodiment of the present invention.

[Figure 2] Cross-sectional view of a conventional planar high voltage diode

[
FIG. 3: A plan view of a planar diode silicon substrate according to an embodiment of the present invention

FIG. 4 is a plan view of a planar diode silicon substrate according to another embodiment of the present invention.

FIG. 5 is a plan view of a silicon substrate of a planar diode according to yet another embodiment of the present invention.

[Explanation of symbols]

1 n- layer 2 n+ layer 3 p+ area 5 p+ guard ring 6 Anode electrode 7 Cathode electrode 8 Recessed part

Claims (3)

[Claims] Claims: 1. A first conductivity type high impurity concentration layer on one side of the first conductivity type low impurity concentration layer; In a diode having a semiconductor body provided with a high impurity concentration diffusion region of the second conductivity type, a predetermined second depth shallower than the first depth is provided at a portion of the surface of the second conductivity type high impurity concentration region away from the peripheral edge. A planar diode characterized in that a plurality of concave portions having a high temperature are formed in a dispersed manner. 2. One or more annular high impurity concentration regions of a second conductivity type having a substantially first depth at a distance outside the high impurity concentration region of the second conductivity type surround the region. 2. A planar diode according to claim 1, formed of: 3. A step of forming a semiconductor element in which a first conductivity type low impurity concentration layer and a high impurity concentration layer are laminated, and introducing an impurity from a predetermined portion of the first conductivity type low impurity concentration layer. , forming a high impurity concentration region of a second conductivity type by diffusion to a predetermined first depth, and etching a plurality of parts of the surface of the high impurity concentration region to a predetermined depth shallower than the first depth. a step of forming a recess having a second depth; a step of providing an electrode in contact with the surface of the high impurity concentration layer of the first conductivity type; and a step of forming an inner surface of the recess on the surface of the high impurity concentration region of the second conductivity type. 1. A method for manufacturing a planar diode, the method comprising: providing an electrode that is in contact with the electrode.