JP2005136116A - Semiconductor element and its manufacturing method - Google Patents

Semiconductor element and its manufacturing method Download PDF

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JP2005136116A
JP2005136116A JP2003369845A JP2003369845A JP2005136116A JP 2005136116 A JP2005136116 A JP 2005136116A JP 2003369845 A JP2003369845 A JP 2003369845A JP 2003369845 A JP2003369845 A JP 2003369845A JP 2005136116 A JP2005136116 A JP 2005136116A
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JP4929559B2 (en
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Masayuki Hanaoka
正行 花岡
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Sanken Electric Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor element which has a channel stopper of relatively large width and good breakdown voltage characteristic or particularly the good breakdown voltage characteristic of an end, and to provide a method for manufacturing the same. <P>SOLUTION: In the semiconductor device, the channel stopper 18 is provided relatively widely adjacent to the outer peripheral p-type region 17 formed unavoidably in a manufacturing process at the outer peripheral edge of a semiconductor substrate 19. The polysilicon film on an n-type region comprising the channel stopper 18 for constituting the channel stopper 18 is first removed at an outer peripheral end in a width to be formed with the outer peripheral p-type region 17 of the minimum limit, and the outer peripheral p-type region 17 of the minimum width and the channel stopper 18 of the maximum width are formed by performing a p-type impurity diffusion in this state. Thereafter, when a second recess 26 is formed, the outer peripheral end of the polysilicon film is further removed, and an EQR 27 of a predetermined width is thereby formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、電力用スイッチング素子等に用いられる半導体素子およびその製造方法に関する。   The present invention relates to a semiconductor element used for a power switching element or the like and a method for manufacturing the same.

電力用のスイッチング素子として、ＭＯＳＦＥＴ（絶縁ゲート型電界効果トランジスタ）等の半導体素子が用いられている（特許文献１参照）。従来のＭＯＳＦＥＴを構成する半導体素子の構成を図５に示す。
図５に示す半導体素子１１０は、比較的不純物濃度の高いＮ+型半導体領域から構成されるドレイン領域１１１と、ドレイン領域１１１の上に形成された比較的不純物濃度の低いＮ-型半導体領域から構成されるドリフト領域１１２と、ドリフト領域１１２内に島状に分散配置されたＰ型半導体領域から構成されるベース領域１１３と、ベース領域１１３内に環状に形成されたソース領域１１４と、を有する半導体基板１１９と、半導体基板１１９の一面上に形成されたゲート電極１２２およびソース電極１２５と、半導体基板１１９の他面上に形成されたドレイン電極１２０と、を備える。ベース領域１１３（チャネル領域）は、ドリフト領域１１２とソース領域１１４との間に環状に設けられ、ゲート電極１２２は、ベース領域１１３の上にゲート絶縁膜を介してこれに対向して設けられている。
特開平１０−１８９９６９号公報 Semiconductor elements such as MOSFETs (insulated gate field effect transistors) are used as power switching elements (see Patent Document 1). FIG. 5 shows a configuration of a semiconductor element constituting a conventional MOSFET.
A semiconductor element 110 shown in FIG. 5 includes a drain region 111 composed of an N + type semiconductor region having a relatively high impurity concentration, and an N − type semiconductor region formed on the drain region 111 with a relatively low impurity concentration. A drift region 112 configured, a base region 113 formed of P-type semiconductor regions dispersed in an island shape in the drift region 112, and a source region 114 formed in an annular shape in the base region 113 The semiconductor substrate 119 includes a gate electrode 122 and a source electrode 125 formed on one surface of the semiconductor substrate 119, and a drain electrode 120 formed on the other surface of the semiconductor substrate 119. The base region 113 (channel region) is provided in an annular shape between the drift region 112 and the source region 114, and the gate electrode 122 is provided on the base region 113 so as to face the gate insulating film. Yes.
JP-A-10-189969

図５に示すように、この半導体素子１１０には、半導体基板１１９の外周縁に沿って、Ｐ型半導体領域（外周Ｐ型領域１１７）が環状に形成されている。環状の外周Ｐ型領域１１７の内側には、これと隣接してＮ型半導体領域から構成されるチャネルストッパ１１８が形成されている。チャネルストッパ１１８の機能については後述する。   As shown in FIG. 5, in this semiconductor element 110, a P-type semiconductor region (outer peripheral P-type region 117) is formed in an annular shape along the outer peripheral edge of the semiconductor substrate 119. A channel stopper 118 composed of an N-type semiconductor region is formed inside the annular outer peripheral P-type region 117 so as to be adjacent thereto. The function of the channel stopper 118 will be described later.

チャネルストッパ１１８の上にはポリシリコン膜から構成されるＥＱＲ１２７（等電位リング）が形成されている。また、図示しないが、ＥＱＲ１２７は、半導体基板１１９の角部で導体膜等によりチャネルストッパ１１８に電気的に接続されている。   On the channel stopper 118, an EQR 127 (equipotential ring) made of a polysilicon film is formed. Although not shown, the EQR 127 is electrically connected to the channel stopper 118 at the corner of the semiconductor substrate 119 by a conductor film or the like.

また、ベース領域１１３とソース領域１１４とから構成される単位セルのうち、素子の最外周に配置された単位セルの外側には、図示のように、これに隣接してＰ型補助領域１１６が形成されている。Ｐ型補助領域１１６は、最外周のセル領域の外側にＮ型半導体領域１１５が隣接して形成されることを防止する等の機能を有する。なお、隣り合うセル間に配置されたＮ型半導体領域１１５は、ドリフト領域１１２の抵抗を下げて、動作電圧を低減する機能を有する。   In addition, among the unit cells composed of the base region 113 and the source region 114, a P-type auxiliary region 116 is adjacent to the outside of the unit cell arranged on the outermost periphery of the element, as shown in the figure. Is formed. The P-type auxiliary region 116 has a function of preventing the N-type semiconductor region 115 from being formed adjacent to the outside of the outermost peripheral cell region. Note that the N-type semiconductor region 115 disposed between adjacent cells has a function of reducing the operating voltage by lowering the resistance of the drift region 112.

図５に示す半導体素子１１０では、ドレイン電極１２０とソース電極１２５との間にドレイン電極１２０側の電位を高くする電圧を印加し、さらにゲート電極１２２に所定のゲート電圧を印加すると、チャネル領域を通じてドレイン電極１２０とソース電極１２５との間にドレイン電流が流れる。   In the semiconductor element 110 illustrated in FIG. 5, when a voltage that increases the potential on the drain electrode 120 side is applied between the drain electrode 120 and the source electrode 125 and a predetermined gate voltage is further applied to the gate electrode 122, A drain current flows between the drain electrode 120 and the source electrode 125.

一方、ゲート電極１２２に印加するゲート電圧を所定のしきい値以下にすると、チャネルが閉じてドレイン電流が流れなくなる。このオフ状態のとき、ドリフト領域１１２とベース領域１１３との界面に形成されるＰＮ接合は逆方向にバイアスされ、その界面からドリフト領域１１２に空乏層が広がる。   On the other hand, when the gate voltage applied to the gate electrode 122 is set to a predetermined threshold value or less, the channel is closed and the drain current does not flow. In this off state, the PN junction formed at the interface between the drift region 112 and the base region 113 is biased in the reverse direction, and a depletion layer spreads from the interface to the drift region 112.

最外周に配置されたセル領域を構成するベース領域１１３からは、図５中破線で示すように、ＰＮ接合から広がる空乏層が素子外周側に向かって広がる。そして、この空乏層が外周Ｐ型領域１１７に到達すると、外周Ｐ型領域１１７を介して電流（リーク電流）が流れ、素子耐圧が低下する。   From the base region 113 constituting the cell region arranged on the outermost periphery, a depletion layer extending from the PN junction spreads toward the device outer peripheral side as shown by a broken line in FIG. When this depletion layer reaches the outer peripheral P-type region 117, a current (leakage current) flows through the outer peripheral P-type region 117, and the element breakdown voltage is reduced.

チャネルストッパ１１８は、このように空乏層が外周Ｐ型領域１１７に到達するのを抑制し、素子耐圧を向上させる機能を有する。外周Ｐ型領域１１７の内周側に隣接して設けられたチャネルストッパ１１８は、最外周のセル領域のＰＮ接合から延びる空乏層が自身を越えて外周Ｐ型領域１１７に到達するのを抑制する。   The channel stopper 118 has a function of suppressing the depletion layer from reaching the outer peripheral P-type region 117 and improving the element breakdown voltage. The channel stopper 118 provided adjacent to the inner peripheral side of the outer peripheral P-type region 117 suppresses the depletion layer extending from the PN junction in the outermost peripheral cell region from reaching the outer peripheral P-type region 117 beyond itself. .

以下、上記構成の従来の半導体素子１１０の製造方法について図面を参照して説明する。図６（ａ）〜（ｃ）にその製造プロセスを示す。まず、ドリフト領域１１２とドレイン領域１１１（図示せず）とを備え、ドリフト領域１１２にＰ型補助領域１１６が形成された半導体基板１１９を用意する。ここで、ドレイン領域１１１は、例えば、ドリフト領域１１２を構成する比較的不純物濃度の低いＮ-型半導体領域にＮ型不純物を拡散して形成される。また、Ｐ型補助領域１１６は、ドリフト領域１１２にＰ型不純物を選択的に拡散して形成され、半導体基板１１９の外周縁に沿って環状に形成されている。 Hereinafter, a method for manufacturing the conventional semiconductor element 110 having the above-described configuration will be described with reference to the drawings. FIGS. 6A to 6C show the manufacturing process. First, a semiconductor substrate 119 having a drift region 112 and a drain region 111 (not shown) and having a P-type auxiliary region 116 formed in the drift region 112 is prepared. Here, the drain region 111 is formed, for example, by diffusing an N-type impurity in an N − -type semiconductor region that constitutes the drift region 112 and has a relatively low impurity concentration. The P-type auxiliary region 116 is formed by selectively diffusing P-type impurities in the drift region 112, and is formed in an annular shape along the outer peripheral edge of the semiconductor substrate 119.

次に、用意した半導体基板１１９に熱処理を施して、半導体基板１１９のドリフト領域１１２形成面に、厚い酸化膜を形成する。さらに、酸化膜の、半導体基板１１９の外周側と内周側とをエッチング等により除去し、帯状の第１の絶縁膜１２１を環状に残存させる。   Next, heat treatment is performed on the prepared semiconductor substrate 119 to form a thick oxide film on the surface of the semiconductor substrate 119 where the drift region 112 is formed. Further, the outer peripheral side and the inner peripheral side of the semiconductor substrate 119 of the oxide film are removed by etching or the like, and the strip-shaped first insulating film 121 is left in an annular shape.

その後、ドリフト領域１１２を備えた半導体基板１１９の表面に、熱処理により薄い第２の絶縁膜１２３を形成する。第２の絶縁膜１２３はゲート絶縁膜を構成する。続いて、厚い第１の絶縁膜１２１をマスクとして、半導体基板１１９の表面領域にＮ型不純物を拡散させる。これにより、図６（ａ）に示すように、半導体基板１１９の内周側と外周側とにそれぞれＮ型拡散領域１３０が形成される。セル形成領域のＮ型拡散領域１３０は、上述したＮ型半導体領域１１５を構成する。また、半導体基板１１９の外周側端部のＮ型拡散領域１３０は、上述したチャネルストッパ１１８を構成する。   Thereafter, a thin second insulating film 123 is formed on the surface of the semiconductor substrate 119 provided with the drift region 112 by heat treatment. The second insulating film 123 forms a gate insulating film. Subsequently, N-type impurities are diffused in the surface region of the semiconductor substrate 119 using the thick first insulating film 121 as a mask. As a result, as shown in FIG. 6A, N-type diffusion regions 130 are formed on the inner and outer peripheral sides of the semiconductor substrate 119, respectively. The N-type diffusion region 130 in the cell formation region constitutes the N-type semiconductor region 115 described above. The N-type diffusion region 130 at the outer peripheral side end of the semiconductor substrate 119 constitutes the above-described channel stopper 118.

次に、半導体基板１１９の第１の絶縁膜１２１等が形成された面に、ＣＶＤ等によりポリシリコン膜を形成する。続いて、このポリシリコン膜にエッチングを施して、第１の絶縁膜１２１の内周側の第１のポリシリコン膜１３１と、外周側の第２のポリシリコン膜１３２と、を形成する。第１のポリシリコン膜１３１は上述したゲート電極１２２等を構成し、第２のポリシリコン膜１３２は上述したＥＱＲ１２７を構成する。   Next, a polysilicon film is formed on the surface of the semiconductor substrate 119 on which the first insulating film 121 and the like are formed by CVD or the like. Subsequently, the polysilicon film is etched to form a first polysilicon film 131 on the inner peripheral side of the first insulating film 121 and a second polysilicon film 132 on the outer peripheral side. The first polysilicon film 131 constitutes the above-described gate electrode 122 and the like, and the second polysilicon film 132 constitutes the above-described EQR 127.

ここで、半導体基板１１９の端部付近には、所定のアラインメントパターン（図示せず）が形成されているため、半導体基板１１９の外周縁を覆うポリシリコン膜を除去するようエッチングを行う。すなわち、第２のポリシリコン膜１３２の外周側の一端から半導体基板１１９の外周の間に、所定幅で第２の絶縁膜１２３が露出するようにエッチングを行う。   Here, since a predetermined alignment pattern (not shown) is formed in the vicinity of the end portion of the semiconductor substrate 119, etching is performed so as to remove the polysilicon film covering the outer peripheral edge of the semiconductor substrate 119. That is, etching is performed so that the second insulating film 123 is exposed with a predetermined width between one end on the outer peripheral side of the second polysilicon film 132 and the outer periphery of the semiconductor substrate 119.

次いで、第１および第２のポリシリコン膜１３１、１３２をマスクとして、半導体基板１１９の表面領域に、順次、Ｐ型不純物とＮ型不純物とをそれぞれ選択的に拡散させる。これにより、図６（ｂ）に示すように、半導体基板１１９、すなわち、ドリフト領域１１２の表面領域に、ベース領域１１３と、ソース領域１１４と、が形成される。   Next, using the first and second polysilicon films 131 and 132 as masks, P-type impurities and N-type impurities are selectively diffused sequentially in the surface region of the semiconductor substrate 119. As a result, as shown in FIG. 6B, the base region 113 and the source region 114 are formed in the semiconductor substrate 119, that is, the surface region of the drift region 112.

このとき、半導体基板１１９の外周縁端部の所定幅は、ポリシリコン膜（第２のポリシリコン膜１３２）で覆われていない。このため、端部には、不可避的にＰ型拡散領域、すなわち、上述した外周Ｐ型領域１１７が、除去幅に応じた幅で形成される。   At this time, the predetermined width of the outer peripheral edge of the semiconductor substrate 119 is not covered with the polysilicon film (second polysilicon film 132). For this reason, a P-type diffusion region, that is, the above-described outer peripheral P-type region 117 is inevitably formed at the end with a width corresponding to the removal width.

次に、半導体基板１１９のドリフト領域１１２を備える面上に、シリコン酸化膜等のシリコン系絶縁膜１３４をＣＶＤ等により形成する。続いて、図６（ｃ）に示すように、シリコン系絶縁膜１３４に選択的エッチング等を施し、次いで、シリコン系絶縁膜１３４をマスクとして半導体基板１１９をエッチングして、その周縁部等を除去する。
最後に、上記のようにして得られた半導体基板１１９の両面上にアルミニウム等から構成されるソース電極１２５とドレイン電極１２０とを形成することにより、図５に示す半導体素子１１０が完成する。 Next, a silicon-based insulating film 134 such as a silicon oxide film is formed on the surface of the semiconductor substrate 119 having the drift region 112 by CVD or the like. Subsequently, as shown in FIG. 6C, selective etching or the like is performed on the silicon-based insulating film 134, and then the semiconductor substrate 119 is etched using the silicon-based insulating film 134 as a mask to remove the peripheral portion and the like. To do.
Finally, the source electrode 125 and the drain electrode 120 made of aluminum or the like are formed on both surfaces of the semiconductor substrate 119 obtained as described above, thereby completing the semiconductor element 110 shown in FIG.

しかし、上記のように製造された半導体素子１１０は高い耐圧特性が得られにくく、本発明者が鋭意検討したところ、これは以下のような理由によることが判明した。すなわち、上記のように製造された半導体素子１１０では、チャネルストッパ１１８の形成幅が比較的狭く、チャネルストッパ１１８の効果が不十分なことが一因であることが判明した。   However, the semiconductor device 110 manufactured as described above is difficult to obtain a high withstand voltage characteristic, and the present inventors diligently studied and found that this is due to the following reasons. That is, in the semiconductor element 110 manufactured as described above, it has been found that the channel stopper 118 is formed with a relatively narrow width and the effect of the channel stopper 118 is insufficient.

詳細には、上記従来の半導体素子１１０は、図６（ｂ）および（ｃ）に示すように、ＥＱＲ１２７を構成するポリシリコン膜１３２を比較的狭い幅でエッチング形成した後、Ｐ型不純物を選択的に拡散させてセル形成領域にベース領域１１３を形成する。このとき、半導体基板１１９の端部には、図示しないアラインメントパターンのため外周Ｐ型領域１１７が不可避的に形成される。外周Ｐ型領域１１７の幅によりチャネルストッパ１１８の幅が決定されるが、第２のポリシリコン膜を比較的狭い幅で形成しており、端部の露出幅が比較的広い。このため、外周Ｐ型領域１１７の形成幅は比較的広く、一方で、チャネルストッパ１１８の形成幅は比較的狭いものとなる。   Specifically, in the conventional semiconductor device 110, as shown in FIGS. 6B and 6C, after the polysilicon film 132 constituting the EQR 127 is formed by etching with a relatively narrow width, the P-type impurity is selected. Thus, the base region 113 is formed in the cell formation region. At this time, an outer peripheral P-type region 117 is inevitably formed at the end of the semiconductor substrate 119 due to an alignment pattern (not shown). Although the width of the channel stopper 118 is determined by the width of the outer peripheral P-type region 117, the second polysilicon film is formed with a relatively narrow width, and the exposed width of the end portion is relatively wide. For this reason, the formation width of the outer peripheral P-type region 117 is relatively wide, while the formation width of the channel stopper 118 is relatively narrow.

このようにチャネルストッパ１１８の幅が比較的狭いと、高い逆方向電圧が印加された場合には、チャネルストッパ１１８の効果が十分に得られず、空乏層が外周Ｐ型領域１１７まで到達してしまう。空乏層が外周Ｐ型領域１１７に到達すると、外周Ｐ型領域１１７と、空乏層形成領域（ドリフト領域１１２）と、ベース領域１１３と、を介して、ドレイン電極１２０とソース電極１２５との間に図５中矢印で示すようにリーク電流が流れ、結果として素子耐圧が低下する。   If the width of the channel stopper 118 is relatively narrow as described above, when a high reverse voltage is applied, the effect of the channel stopper 118 cannot be obtained sufficiently, and the depletion layer reaches the outer peripheral P-type region 117. End up. When the depletion layer reaches the outer peripheral P-type region 117, the drain electrode 120 and the source electrode 125 are interposed between the outer peripheral P-type region 117, the depletion layer forming region (drift region 112), and the base region 113. As indicated by the arrows in FIG. 5, a leak current flows, and as a result, the device breakdown voltage decreases.

このように、従来のＭＯＳＦＥＴ等の半導体素子には、チャネルストッパの形成幅が比較的狭く、高い逆方向電圧が印加された場合に、外周縁に不可避的に形成される外周Ｐ型領域まで空乏層が到達しやすく、結果、高い耐圧が得られない場合があった。   As described above, a semiconductor device such as a conventional MOSFET has a relatively narrow channel stopper formation width and is depleted to an outer peripheral P-type region inevitably formed on the outer periphery when a high reverse voltage is applied. In some cases, the layer easily reached, and as a result, a high breakdown voltage could not be obtained.

上記事情を鑑みて、本発明は、オフ時のリーク電流の発生が抑制される等、高い耐圧を有する半導体素子およびその製造方法を提供することを目的とする。
また、本発明は、チャネルストッパを比較的広い幅で備える半導体素子およびその製造方法を提供することを目的とする。 In view of the above circumstances, an object of the present invention is to provide a semiconductor device having a high breakdown voltage such as generation of a leakage current at the time of off and a method for manufacturing the same.
It is another object of the present invention to provide a semiconductor device having a channel stopper with a relatively wide width and a method for manufacturing the same.

上記目的を達成するため、本発明の第１の観点にかかる半導体素子は、
半導体基板の一面を構成する第１導電型の第１半導体領域と、
前記第１半導体領域の端部の表面領域に形成された第２導電型の第２半導体領域と、
前記第１半導体領域の表面領域に前記第２半導体領域に隣接して形成され、前記第１半導体領域よりも不純物濃度の高い第１導電型の第３半導体領域と、
前記第１半導体領域の上方に設けられ、その端部側の一端が前記第３半導体領域の絶縁膜を介した上方にあるよう形成された導体膜と、
を備える。 In order to achieve the above object, a semiconductor element according to the first aspect of the present invention includes:
A first semiconductor region of a first conductivity type constituting one surface of the semiconductor substrate;
A second semiconductor region of a second conductivity type formed in a surface region at an end of the first semiconductor region;
A third semiconductor region of a first conductivity type formed in a surface region of the first semiconductor region adjacent to the second semiconductor region and having a higher impurity concentration than the first semiconductor region;
A conductor film provided above the first semiconductor region and having one end on the end side located above the insulating film of the third semiconductor region;
Is provided.

上記構成の半導体素子は前記第１半導体領域の表面領域の、前記第３半導体領域よりも内周側に形成された第２導電型の第４半導体領域をさらに備えてもよく、
前記第３半導体領域は、前記第１半導体領域と前記第４半導体領域との界面から形成される空乏層の外周側への広がりを抑制する等のために設けられている。 The semiconductor element having the above-described configuration may further include a second conductivity type fourth semiconductor region formed on an inner peripheral side of the surface region of the first semiconductor region with respect to the third semiconductor region,
The third semiconductor region is provided in order to suppress the spread of the depletion layer formed from the interface between the first semiconductor region and the fourth semiconductor region to the outer peripheral side.

上記構成の半導体素子において、例えば、前記導体膜は等電位リングを構成する。   In the semiconductor element having the above configuration, for example, the conductor film forms an equipotential ring.

上記構成の半導体素子において、前記第３半導体領域は、相対的に深い深さを有する第１の領域と、相対的に浅い深さを有する第２の領域と、を備え、その露出面には、前記第１の領域と前記第２の領域とを隔てる段差が形成されていてもよい。   In the semiconductor element configured as described above, the third semiconductor region includes a first region having a relatively deep depth and a second region having a relatively shallow depth, and an exposed surface thereof is provided on the exposed surface. A step that separates the first region from the second region may be formed.

上記構成の半導体素子において、前記第２の領域は、前記第２半導体領域と共通の平面を構成してもよい。   In the semiconductor element configured as described above, the second region may constitute a common plane with the second semiconductor region.

上記構成の半導体素子において、前記絶縁膜は、前記第１の領域を覆いかつ前記第２の領域を覆わないように形成されていてもよい。   In the semiconductor element having the above structure, the insulating film may be formed so as to cover the first region and not cover the second region.

上記構成の半導体素子において、前記導体膜の端部側の一端と、前記絶縁膜の端部側の一端と、前記第３半導体領域の段差と、は、共通の平面を構成してもよい。   In the semiconductor element configured as described above, one end on the end portion side of the conductor film, one end on the end portion side of the insulating film, and the step in the third semiconductor region may constitute a common plane.

上記構成の半導体素子は、前記第２の領域上に形成され、前記導体膜と前記第３半導体領域とを電気的に接続する接続用導体膜をさらに備えてもよい。   The semiconductor element having the above configuration may further include a connecting conductor film that is formed on the second region and electrically connects the conductor film and the third semiconductor region.

上記目的を達成するため、本発明の第２の観点にかかる半導体素子の製造方法は、
第１導電型の第１半導体領域を一面に備える半導体基板を用意する工程と、
前記半導体基板の一面上に、その端部が第１の幅で露出するように、相対的に厚い第１の絶縁膜を形成する工程と、
前記半導体基板の一面に、相対的に薄い第２の絶縁膜を形成する工程と、
前記半導体基板の一面に、前記第１の絶縁膜をマスクとして、選択的に第１導電型の不純物を拡散させ、前記第１半導体領域よりも不純物濃度の高い第１拡散領域を形成する工程と、
前記半導体基板の一面上に、少なくとも前記半導体基板の端部を前記第１の幅よりも小さい第２の幅で残して覆う導体膜を形成する工程と、
前記導体膜をマスクとして、前記半導体基板の一面の表面領域に第２導電型の不純物を選択的に拡散させ、前記第１拡散領域よりも深い拡散深さでこれと隣接する第２拡散領域を形成する工程と、
前記第１の幅よりも小さくかつ前記第２の幅よりも大きい幅で、前記半導体基板の一面の端部をその上に形成された前記第２の絶縁膜と前記導体膜とともに除去する除去工程と、
を備える。 In order to achieve the above object, a method of manufacturing a semiconductor device according to the second aspect of the present invention includes:
Providing a semiconductor substrate having a first semiconductor region of a first conductivity type on one side;
Forming a relatively thick first insulating film on one surface of the semiconductor substrate such that an end of the semiconductor substrate is exposed with a first width;
Forming a relatively thin second insulating film on one surface of the semiconductor substrate;
Forming a first diffusion region having a higher impurity concentration than the first semiconductor region by selectively diffusing impurities of the first conductivity type on one surface of the semiconductor substrate using the first insulating film as a mask; ,
Forming a conductor film on one surface of the semiconductor substrate, covering at least an end portion of the semiconductor substrate with a second width smaller than the first width; and
Using the conductor film as a mask, a second conductivity type impurity is selectively diffused in a surface region of one surface of the semiconductor substrate, and a second diffusion region adjacent to the second diffusion region is formed at a diffusion depth deeper than the first diffusion region. Forming, and
A removing step of removing an end portion of one surface of the semiconductor substrate together with the second insulating film and the conductor film formed thereon with a width smaller than the first width and larger than the second width. When,
Is provided.

上記方法は、前記端部に露出した前記第１拡散領域上に、前記端部に形成された前記導体膜と電気的に接続された接続用導体膜を形成する工程をさらに備えてもよい。   The method may further include a step of forming a connection conductor film electrically connected to the conductor film formed at the end portion on the first diffusion region exposed at the end portion.

本発明によれば、オフ時のリーク電流の発生が抑制される等、高い耐圧を有する半導体素子およびその製造方法が提供される。
また、本発明によれば、チャネルストッパを比較的広い幅で備える半導体素子およびその製造方法が提供される。 According to the present invention, there are provided a semiconductor device having a high breakdown voltage such as generation of a leakage current at the time of off, and a method for manufacturing the same.
In addition, according to the present invention, a semiconductor device having a channel stopper with a relatively wide width and a method for manufacturing the same are provided.

以下、本発明の実施の形態にかかる半導体素子について、図面を参照して詳細に説明する。なお、以下に示す実施の形態では、本発明を絶縁ゲート型電界効果トランジスタ（以下、ＭＯＳＦＥＴ：Metal Oxide Semiconductor Field Effect Transistor）に適用した場合を例として説明する。   Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings. In the embodiment described below, a case where the present invention is applied to an insulated gate field effect transistor (hereinafter referred to as a MOSFET: Metal Oxide Semiconductor Field Effect Transistor) will be described as an example.

図１に、本実施の形態にかかる半導体素子の断面構成を示す。図１に示すように、半導体素子１０は、ドレイン領域１１と、ドリフト領域１２と、ベース領域１３と、ソース領域１４と、Ｎ型半導体領域１５と、Ｐ型補助領域１６と、外周Ｐ型領域１７と、チャネルストッパ１８と、を備えた半導体基板１９を備える。   FIG. 1 shows a cross-sectional configuration of the semiconductor element according to the present embodiment. As shown in FIG. 1, the semiconductor element 10 includes a drain region 11, a drift region 12, a base region 13, a source region 14, an N-type semiconductor region 15, a P-type auxiliary region 16, and an outer peripheral P-type region. 17 and a semiconductor substrate 19 provided with a channel stopper 18.

ドレイン領域１１は、後述するＮ型半導体領域１５よりも不純物濃度の高いＮ+型半導体領域から構成される。ドレイン領域１１の一面上には、アルミニウム等から構成されるドレイン電極２０が形成されている。
ドリフト領域１２は、ドレイン領域１１の他面上に形成された、後述するＮ型半導体領域１５よりも不純物濃度の低いＮ-型半導体領域から構成される。ドレイン領域１１およびドリフト領域１２は、それぞれ、半導体基板１９の主面を構成する。 The drain region 11 is composed of an N + type semiconductor region having an impurity concentration higher than that of an N type semiconductor region 15 described later. A drain electrode 20 made of aluminum or the like is formed on one surface of the drain region 11.
The drift region 12 is composed of an N − type semiconductor region formed on the other surface of the drain region 11 and having an impurity concentration lower than that of an N type semiconductor region 15 described later. The drain region 11 and the drift region 12 each constitute a main surface of the semiconductor substrate 19.

ドリフト領域１２の上には、比較的厚膜のシリコン系膜から構成される第１の絶縁膜２１が設けられている。第１の絶縁膜２１は、ドリフト領域１２（半導体基板１９）の外周縁に沿って、その最外周から所定の幅Ｘ１離間して、環状、帯状に形成されている。幅Ｘ１は、例えば、４０μｍとされる。
第１の絶縁膜２１の内周側は、素子活性領域であるセル形成領域を構成し、その外周側は後述するＥＱＲ等が形成される端部を構成する。 On the drift region 12, a first insulating film 21 made of a relatively thick silicon-based film is provided. The first insulating film 21 is formed in an annular shape and a strip shape along the outer peripheral edge of the drift region 12 (semiconductor substrate 19) with a predetermined width X1 from the outermost periphery. The width X1 is, for example, 40 μm.
The inner peripheral side of the first insulating film 21 constitutes a cell formation region which is an element active region, and the outer peripheral side constitutes an end portion where an EQR or the like to be described later is formed.

ベース領域１３は、セル形成領域内の、ドリフト領域１２の表面領域に島状に分散配置されたＰ型半導体領域から構成される。
ソース領域１４は、ベース領域１３の表面領域の内側に環状に形成された、後述するＮ型半導体領域１５よりも不純物濃度の高いＮ+型半導体領域から構成される。
ドリフト領域１２とソース領域１４との間に露出する環状のベース領域１３（チャネル領域）の上方には、ポリシリコン膜から構成されるゲート電極２２が、ゲート絶縁膜を構成する第２の絶縁膜２３を介して対向するように設けられている。なお、第２の絶縁膜２３は、第１の絶縁膜２１よりも薄い厚さを有する。
ベース領域１３とソース領域１４とは単位セル領域を構成し、セル形成領域内に所定数設けられている。 Base region 13 is formed of P-type semiconductor regions dispersed in an island shape in the surface region of drift region 12 in the cell formation region.
The source region 14 is composed of an N + type semiconductor region formed in an annular shape inside the surface region of the base region 13 and having an impurity concentration higher than that of an N type semiconductor region 15 described later.
Above the annular base region 13 (channel region) exposed between the drift region 12 and the source region 14, a gate electrode 22 made of a polysilicon film is a second insulating film constituting the gate insulating film. 23 to face each other. The second insulating film 23 has a thickness smaller than that of the first insulating film 21.
The base region 13 and the source region 14 constitute a unit cell region, and a predetermined number is provided in the cell formation region.

ベース領域１３の略中央には、第１の凹部２４が形成されている。第１の凹部２４は、ソース領域１４を貫通し、その底部がソース領域１４の底部（底面）よりも深い位置にあるように形成されている。したがって、第１の凹部２４の内部側面にはソース領域１４が露出し、その底部にはベース領域１３が露出している。   A first recess 24 is formed substantially at the center of the base region 13. The first recess 24 penetrates the source region 14 and is formed so that its bottom is deeper than the bottom (bottom surface) of the source region 14. Therefore, the source region 14 is exposed on the inner side surface of the first recess 24, and the base region 13 is exposed on the bottom thereof.

第１の凹部２４の内部には、ソース電極２５がその内部に埋設されるように形成され、ソース領域１４およびベース領域１３の両方に電気的に接続されている。したがって、第１の凹部２４は、コンタクト用ホールと呼ぶこともできる。   A source electrode 25 is formed inside the first recess 24 so as to be embedded therein, and is electrically connected to both the source region 14 and the base region 13. Therefore, the first recess 24 can also be called a contact hole.

Ｎ型半導体領域１５は、隣り合うセル領域の間を埋めるように形成されたＮ型半導体領域から構成される。Ｎ型半導体領域１５は、ベース領域１３よりも浅い拡散深さで形成されている。Ｎ型半導体領域１５は、ドリフト領域１２の抵抗を下げ、素子の動作電圧を低減する機能を有する。   The N-type semiconductor region 15 is composed of an N-type semiconductor region formed so as to fill between adjacent cell regions. The N-type semiconductor region 15 is formed with a shallower diffusion depth than the base region 13. The N-type semiconductor region 15 has a function of lowering the resistance of the drift region 12 and reducing the operating voltage of the element.

Ｐ型補助領域１６は、セル形成領域の外周側に隣接して形成されたＰ型半導体領域から構成される。すなわち、Ｐ型補助領域１６は、第１の絶縁膜２１の内周側に沿って形成されている。Ｐ型補助領域１６は、後述する素子の形成工程において、セル形成領域の最外周の単位セル（ベース領域１３）の外周側に、Ｎ型半導体領域１５が形成されることを防止する等のために設けられている。   The P-type auxiliary region 16 is composed of a P-type semiconductor region formed adjacent to the outer peripheral side of the cell formation region. That is, the P-type auxiliary region 16 is formed along the inner peripheral side of the first insulating film 21. The P-type auxiliary region 16 is used to prevent the N-type semiconductor region 15 from being formed on the outer peripheral side of the outermost unit cell (base region 13) in the cell formation region in the element formation process described later. Is provided.

外周Ｐ型領域１７は、ドリフト領域１２の端部に、外周縁に沿って所定の幅Ｘ２で形成された環状のＰ型半導体領域から構成される。外周Ｐ型領域１７は、上述したベース領域１３と同一の工程で形成される。外周Ｐ型領域１７は、後述するように、アラインメントパターンのための余地を確保するために不可避的に形成される。外周Ｐ型領域１７の形成幅Ｘ２は、その確保のために必要最小限とされ、例えば、３０μｍとされる。   The outer peripheral P-type region 17 is composed of an annular P-type semiconductor region formed at the end of the drift region 12 with a predetermined width X2 along the outer peripheral edge. The outer peripheral P-type region 17 is formed in the same process as the base region 13 described above. The outer periphery P-type area | region 17 is inevitably formed in order to ensure the room for an alignment pattern so that it may mention later. The formation width X2 of the outer peripheral P-type region 17 is the minimum necessary for securing it, and is, for example, 30 μm.

チャネルストッパ１８は、環状の外周Ｐ型領域１７の内周側にこれと隣接して形成されたＮ型半導体領域から構成される。チャネルストッパ１８は、上述したＮ型半導体領域１５と同一の工程で、第１の絶縁膜２１をマスクとした不純物拡散により形成される。   The channel stopper 18 is composed of an N-type semiconductor region formed adjacent to the inner peripheral side of the annular outer peripheral P-type region 17. The channel stopper 18 is formed by impurity diffusion using the first insulating film 21 as a mask in the same process as the N-type semiconductor region 15 described above.

チャネルストッパ１８は、以下に説明するように、オフ時のリーク電流を抑制する機能を有する。図１に示す構成の半導体素子１０では、ドレイン電極２０とソース電極２５との間にドレイン電極２０側の電位を高くする電圧を印加し、さらにゲート電極２２に所定のゲート電圧を印加すると、チャネル領域を通じてドレイン電極２０とソース電極２５との間にドレイン電流が流れる。   As will be described below, the channel stopper 18 has a function of suppressing leakage current at the time of OFF. In the semiconductor element 10 having the configuration shown in FIG. 1, when a voltage for increasing the potential on the drain electrode 20 side is applied between the drain electrode 20 and the source electrode 25 and a predetermined gate voltage is applied to the gate electrode 22, A drain current flows between the drain electrode 20 and the source electrode 25 through the region.

一方、ゲート電極２２に印加するゲート電圧を所定のしきい値以下にすると、チャネルが閉じてドレイン電流が流れなくなる。このオフ状態のとき、ドリフト領域１２とベース領域１３との界面に形成されるＰＮ接合は逆方向にバイアスされ、その界面からドリフト領域１２に空乏層が広がる。   On the other hand, when the gate voltage applied to the gate electrode 22 is set to a predetermined threshold value or less, the channel is closed and the drain current does not flow. In this OFF state, the PN junction formed at the interface between the drift region 12 and the base region 13 is biased in the reverse direction, and a depletion layer spreads from the interface to the drift region 12.

このとき、最外周に配置されたセル領域を構成するベース領域１３からは、ＰＮ接合から広がる空乏層が外周側に向かって広がる。そして、この空乏層が外周Ｐ型領域１７に到達すると、外周Ｐ型領域１７を介して電流（リーク電流）が流れ、素子耐圧が低下することとなる。チャネルストッパ１８は、このように最外周のセル領域のＰＮ接合から空乏層が延びて外周Ｐ型領域１７に到達するのを抑制する。   At this time, a depletion layer extending from the PN junction spreads toward the outer peripheral side from the base region 13 constituting the cell region disposed on the outermost peripheral. When this depletion layer reaches the outer peripheral P-type region 17, a current (leakage current) flows through the outer peripheral P-type region 17, and the element breakdown voltage decreases. In this way, the channel stopper 18 prevents the depletion layer from extending from the PN junction in the outermost peripheral cell region and reaching the outer peripheral P-type region 17.

半導体基板１９の端部の外周縁には、その全体にわたって第２の凹部２６が環状に形成されている。第２の凹部２６は、外周Ｐ型領域１７の幅Ｘ２よりも大きい幅Ｘ３で形成されている。第２の凹部２６はチャネルストッパ１８よりも浅い深さで形成されている。外周Ｐ型領域１７は、第２の凹部２６の底面に露出し、同一の工程で形成されるベース領域１３よりも第２の凹部２６の深さの分浅い深さを有する。   On the outer peripheral edge of the end portion of the semiconductor substrate 19, a second recess 26 is formed in an annular shape over the entire periphery. The second recess 26 is formed with a width X3 that is larger than the width X2 of the outer peripheral P-type region 17. The second recess 26 is formed with a depth shallower than that of the channel stopper 18. The outer peripheral P-type region 17 is exposed on the bottom surface of the second concave portion 26 and has a depth that is shallower than the depth of the second concave portion 26 than the base region 13 formed in the same process.

第２の凹部２６は、好ましくは、第１の凹部２４と同一のエッチング工程で形成される。第２の凹部２６は、主としてダイシング時における素子のチッピングの発生を防止する機能を有する。すなわち、図１に示す半導体素子１０は、半導体ウェハをその外周縁端部においてダイシングすることによって作製され、ダイシング時には素子にチッピングが発生しやすい。第２の凹部２６はチッピングが素子の活性領域（セル形成領域）に到達することを良好に防止する。   The second recess 26 is preferably formed by the same etching process as the first recess 24. The second recess 26 mainly has a function of preventing the occurrence of chipping of the element during dicing. That is, the semiconductor element 10 shown in FIG. 1 is manufactured by dicing a semiconductor wafer at the outer peripheral edge thereof, and chipping is likely to occur in the element during dicing. The second recess 26 favorably prevents chipping from reaching the active region (cell formation region) of the element.

第２の凹部２６の幅Ｘ３は、第１の絶縁膜２１から端部が露出する幅Ｘ１よりも小さい。したがって、チャネルストッパ１８には、第２の凹部２６により、相対的に深い拡散深さを有する第１の領域１８ａと、相対的に浅い拡散深さを有する第２の領域１８ｂと、を隔てる段差が形成される。第１の領域１８ａはドリフト領域１２と共通の平面を構成し、また、第２の領域１８ｂは外周Ｐ型領域１７とともに、第２の凹部２６の底面を構成する。第２の凹部２６の幅Ｘ３は、例えば、３６μｍとされる。   The width X 3 of the second recess 26 is smaller than the width X 1 at which the end is exposed from the first insulating film 21. Therefore, the channel stopper 18 has a step which separates the first region 18a having a relatively deep diffusion depth and the second region 18b having a relatively shallow diffusion depth by the second recess 26. Is formed. The first region 18 a constitutes a common plane with the drift region 12, and the second region 18 b constitutes the bottom surface of the second recess 26 together with the outer peripheral P-type region 17. The width X3 of the second recess 26 is, for example, 36 μm.

ここで、後述するように、外周Ｐ型領域１７はチャネルストッパ１８を構成するＮ型拡散領域に選択的に拡散形成される。上記のように、外周Ｐ型領域１７は、必要最小限の幅Ｘ２で形成されるため、チャネルストッパ１８の幅Ｘ４は、比較的大きく形成されている。チャネルストッパ１８の幅Ｘ４は、例えば、４０μｍとされる。   Here, as will be described later, the outer peripheral P-type region 17 is selectively diffused and formed in the N-type diffusion region constituting the channel stopper 18. As described above, since the outer peripheral P-type region 17 is formed with the minimum necessary width X2, the width X4 of the channel stopper 18 is formed to be relatively large. The width X4 of the channel stopper 18 is, for example, 40 μm.

チャネルストッパ１８の上には、第２の絶縁膜２３を介してポリシリコン膜から構成されるＥＱＲ２７（等電位リング）が形成されている。ＥＱＲ２７は、ゲート電極２２と同一の工程で形成される。ＥＱＲ２７は、第１の絶縁膜２１の外周側を一部覆い、これに沿って環状に形成されている。   On the channel stopper 18, an EQR 27 (equipotential ring) made of a polysilicon film is formed via the second insulating film 23. The EQR 27 is formed in the same process as the gate electrode 22. The EQR 27 partially covers the outer peripheral side of the first insulating film 21 and is formed in an annular shape along this.

半導体基板１９の角部では、図２に示すように、ＥＱＲ２７がアルミニウム等の導体膜２８を介して、第２の凹部２６の底面に露出したチャネルストッパ１８の第２の領域１８ｂに電気的に接続されている。   At the corner of the semiconductor substrate 19, as shown in FIG. 2, the EQR 27 is electrically connected to the second region 18b of the channel stopper 18 exposed on the bottom surface of the second recess 26 via the conductor film 28 such as aluminum. It is connected.

図１に戻り、ＥＱＲ２７の外周側の一端は、第１の凹部２４の形成と同一の工程でパターン形成されており、チャネルストッパ１８の段差と第２の絶縁膜２３とともに同一の平面（エッチング面）を形成している。したがって、チャネルストッパ１８の段差がそのほぼ中央にあるように形成されている場合、すなわち、第１の領域１８ａと第２の領域１８ｂとがほぼ同じ幅で形成されている場合には、ＥＱＲ２７の外周端は、段差とともに、チャネルストッパ１８のほぼ中央に位置する。また、換言すれば、ＥＱＲ２７の外周端は、平面的に見て外周Ｐ型領域１７よりも半導体基板１９の内周側に形成されている。   Returning to FIG. 1, one end on the outer peripheral side of the EQR 27 is patterned in the same process as the formation of the first recess 24, and the same plane (etching surface) together with the step of the channel stopper 18 and the second insulating film 23. ) Is formed. Therefore, when the step of the channel stopper 18 is formed so as to be substantially at the center thereof, that is, when the first region 18a and the second region 18b are formed with substantially the same width, the EQR 27 The outer peripheral edge is located at the approximate center of the channel stopper 18 together with the step. In other words, the outer peripheral end of the EQR 27 is formed closer to the inner peripheral side of the semiconductor substrate 19 than the outer peripheral P-type region 17 in plan view.

上記のように構成された本実施の形態にかかる半導体素子１０は、以下のような利点を有する。すなわち、本実施の形態では、半導体基板１９の外周縁に不可避的に形成される外周Ｐ型領域１７の形成幅を可能な限り狭く形成しているため、外周Ｐ型領域１７と最外周の単位セル領域との間に、チャネルストッパ１８を比較的大きい幅Ｘ４で形成することができる。   The semiconductor element 10 according to the present embodiment configured as described above has the following advantages. That is, in the present embodiment, the formation width of the outer peripheral P-type region 17 inevitably formed on the outer peripheral edge of the semiconductor substrate 19 is formed as narrow as possible. The channel stopper 18 can be formed with a relatively large width X4 between the cell region.

半導体素子１０に高い逆方向電圧が印加された場合には、セル形成領域のドリフト領域１２とベース領域１３との界面から形成される空乏層が、図中破線に示すように外周側に広がる。チャネルストッパ１８の幅が比較的小さく、狭い場合には、この空乏層はチャネルストッパ１８を越えて外周Ｐ型領域１７まで到達しやすい。空乏層が外周Ｐ型領域１７に到達すると、外周Ｐ型領域１７と、空乏層形成領域（ドリフト領域１２）と、ベース領域１３と、を介して、ドレイン電極２０とソース電極２５との間にリーク電流が流れ、結果として素子耐圧が低下してしまう。   When a high reverse voltage is applied to the semiconductor element 10, a depletion layer formed from the interface between the drift region 12 and the base region 13 in the cell formation region spreads to the outer peripheral side as indicated by a broken line in the figure. When the width of the channel stopper 18 is relatively small and narrow, the depletion layer easily reaches the outer peripheral P-type region 17 beyond the channel stopper 18. When the depletion layer reaches the outer peripheral P-type region 17, the drain electrode 20 and the source electrode 25 are interposed between the outer peripheral P-type region 17, the depletion layer forming region (drift region 12), and the base region 13. Leakage current flows, resulting in a decrease in device breakdown voltage.

しかし、チャネルストッパ１８を比較的大きい幅で、広く形成する本実施の形態では、このような空乏層の外周Ｐ型領域１７への到達は抑制、防止される。したがって、半導体素子１０の外周縁端部における高い耐圧が安定して得られ、信頼性の高い半導体素子１０が得られる。この方法によれば、半導体素子１０の平面サイズを増大することなしに、工程数の増加等を伴うことなく、一般的な方法を用いて、簡便に実現可能である。   However, in the present embodiment in which the channel stopper 18 is formed with a relatively large width and a wide width, the arrival of such a depletion layer to the outer peripheral P-type region 17 is suppressed and prevented. Therefore, a high breakdown voltage at the outer peripheral edge of the semiconductor element 10 can be stably obtained, and the semiconductor element 10 with high reliability can be obtained. According to this method, without increasing the planar size of the semiconductor element 10 and without increasing the number of steps, it can be easily realized by using a general method.

また、本実施の形態では、図２に示すように、角部でチャネルストッパ１８と導体膜２８とを接続するが、チッピング防止用の第２の凹部２６の形成工程で同時にチャネルストッパ１８（の第２の領域１８ｂ）を表面に露出させるため、このような接続が容易となる。   Further, in the present embodiment, as shown in FIG. 2, the channel stopper 18 and the conductor film 28 are connected at the corners, but at the same time in the step of forming the second recess 26 for preventing chipping, Such a connection is facilitated because the second region 18b) is exposed on the surface.

以下、本発明の実施の形態にかかる半導体素子１０の製造方法について図面を参照して説明する。図３（ａ）〜（ｃ）および図４（ｄ）および（ｅ）に、その製造プロセスを示す。なお、以下に示すのは一例であり、同様の結果物が得られるのであれば、これに限られない。   Hereinafter, a method for manufacturing the semiconductor element 10 according to the embodiment of the present invention will be described with reference to the drawings. 3 (a) to 3 (c) and FIGS. 4 (d) and 4 (e) show the manufacturing process. The following is an example, and the present invention is not limited to this as long as a similar result can be obtained.

まず、ドリフト領域１２とドレイン領域１１とを備え、ドリフト領域１２にＰ型補助領域１６が形成された半導体基板１９を用意する。なお、理解を容易なものとするため、図３（ａ）〜（ｃ）および図４（ｄ）および（ｅ）では、ドレイン領域１１は図示を省略する。ここで、ドレイン領域１１は、ドリフト領域１２を構成する比較的不純物濃度の低いＮ-型半導体領域にＮ型不純物を拡散して形成される。ただし、ドレイン領域１１の上に一般的なエピタキシャル成長法を用いてドリフト領域１２を形成してもよい。また、Ｐ型補助領域１６は、ドリフト領域１２にＰ型不純物を選択的に拡散して形成され、半導体基板１９の外周縁に沿って環状に形成されている。 First, a semiconductor substrate 19 having a drift region 12 and a drain region 11 and having a P-type auxiliary region 16 formed in the drift region 12 is prepared. For easy understanding, the drain region 11 is not shown in FIGS. 3A to 3C and FIGS. 4D and 4E. Here, the drain region 11 is formed by diffusing an N-type impurity in an N − -type semiconductor region having a relatively low impurity concentration that constitutes the drift region 12. However, the drift region 12 may be formed on the drain region 11 using a general epitaxial growth method. The P-type auxiliary region 16 is formed by selectively diffusing P-type impurities in the drift region 12, and is formed in an annular shape along the outer peripheral edge of the semiconductor substrate 19.

次に、用意した半導体基板１９に熱処理を施して、半導体基板１９のドリフト領域１２形成面に、厚い酸化膜を形成する。さらに、図３（ａ）に示すように、酸化膜の、半導体基板１９の外周側と内周側とをエッチング等により除去し、帯状の第１の絶縁膜２１を環状に残存させる。第１の絶縁膜２１の内周側はセル形成領域を構成する。ここで、第１の絶縁膜２１は、その外周から端部までの幅Ｘ１が、例えば、４０μｍであるように形成される。   Next, the prepared semiconductor substrate 19 is subjected to a heat treatment to form a thick oxide film on the drift region 12 formation surface of the semiconductor substrate 19. Further, as shown in FIG. 3A, the outer peripheral side and the inner peripheral side of the semiconductor substrate 19 of the oxide film are removed by etching or the like, and the strip-shaped first insulating film 21 is left in an annular shape. The inner peripheral side of the first insulating film 21 constitutes a cell formation region. Here, the first insulating film 21 is formed such that the width X1 from the outer periphery to the end thereof is, for example, 40 μm.

次に、ドリフト領域１２を備えた半導体基板１９の表面に、熱処理により薄い第２の絶縁膜２３を形成する。第２の絶縁膜２３はゲート絶縁膜を構成する。続いて、薄い第２の絶縁膜２３をマスクとして、半導体基板１９の表面領域にＮ型不純物を拡散させる。これにより、図３（ｂ）に示すように、半導体基板１９の内周側と外周側とにそれぞれＮ型拡散領域３０が形成される。   Next, a thin second insulating film 23 is formed on the surface of the semiconductor substrate 19 provided with the drift region 12 by heat treatment. The second insulating film 23 constitutes a gate insulating film. Subsequently, N-type impurities are diffused into the surface region of the semiconductor substrate 19 using the thin second insulating film 23 as a mask. As a result, as shown in FIG. 3B, N-type diffusion regions 30 are formed on the inner and outer peripheral sides of the semiconductor substrate 19, respectively.

セル形成領域のＮ型拡散領域３０は、上述のＮ型半導体領域１５を構成する。また、半導体基板１９の外周側端部のＮ型拡散領域３０は、上述したチャネルストッパ１８を構成する。なお、第１の絶縁膜２１の下方およびＰ型補助領域１６が形成された領域には、Ｎ型拡散領域３０は形成されない。これにより、セル形成領域の最外周に形成される単位セルがＮ型拡散領域３０と隣接することは防止される。   The N-type diffusion region 30 in the cell formation region constitutes the N-type semiconductor region 15 described above. Further, the N-type diffusion region 30 at the outer peripheral side end portion of the semiconductor substrate 19 constitutes the channel stopper 18 described above. Note that the N-type diffusion region 30 is not formed below the first insulating film 21 and in the region where the P-type auxiliary region 16 is formed. This prevents unit cells formed on the outermost periphery of the cell formation region from being adjacent to the N-type diffusion region 30.

次に、半導体基板１９の第１の絶縁膜２１等が形成された面に、ＣＶＤ等によりポリシリコン膜を形成する。続いて、このポリシリコン膜にエッチングを施して、第１の絶縁膜２１の内周側の第１のポリシリコン膜３１と、外周側の第２のポリシリコン膜３２と、を形成する。第１のポリシリコン膜３１は上述したゲート電極２２等を構成し、第２のポリシリコン膜３２は上述したＥＱＲ２７を構成する。   Next, a polysilicon film is formed on the surface of the semiconductor substrate 19 on which the first insulating film 21 and the like are formed by CVD or the like. Subsequently, the polysilicon film is etched to form a first polysilicon film 31 on the inner peripheral side of the first insulating film 21 and a second polysilicon film 32 on the outer peripheral side. The first polysilicon film 31 constitutes the above-described gate electrode 22 and the like, and the second polysilicon film 32 constitutes the above-described EQR 27.

ここで、半導体基板１９の端部付近には、所定のアラインメントパターン（図示せず）が形成されているため、半導体基板１９の外周縁を覆うポリシリコン膜を除去するようエッチングを行う。すなわち、第２のポリシリコン膜３２の外周側の一端から半導体基板１９の外周の間に、所定の幅Ｘ５で第２の絶縁膜２３が露出するようにエッチングを行う。このとき、外周縁のポリシリコン膜の除去は、アラインメントパターンに必要な範囲で可能な限り少なく行われる。したがって、第２のポリシリコン膜３２は、極力長い幅で、半導体基板１９の端部に広がるよう設けられている。ここで、除去幅Ｘ５は、例えば、３０μｍ以下とされる。   Here, since a predetermined alignment pattern (not shown) is formed in the vicinity of the end portion of the semiconductor substrate 19, etching is performed so as to remove the polysilicon film covering the outer peripheral edge of the semiconductor substrate 19. That is, etching is performed so that the second insulating film 23 is exposed with a predetermined width X5 between one end on the outer peripheral side of the second polysilicon film 32 and the outer periphery of the semiconductor substrate 19. At this time, the removal of the outer peripheral polysilicon film is performed as little as possible within the range necessary for the alignment pattern. Therefore, the second polysilicon film 32 is provided so as to extend as far as possible to the end of the semiconductor substrate 19. Here, the removal width X5 is, for example, 30 μm or less.

次いで、第１および第２のポリシリコン膜３１、３２をマスクとして、半導体基板１９の表面領域に、順次、Ｐ型不純物とＮ型不純物とをそれぞれ選択的に拡散させる。これにより、図３（ｃ）に示すように、半導体基板１９、すなわち、ドリフト領域１２の表面領域に、ベース領域１３と、ソース領域１４と、が形成される。ここで、隣り合うベース領域１３の間にはＮ型拡散領域３０が残存して露出している。   Next, using the first and second polysilicon films 31 and 32 as masks, P-type impurities and N-type impurities are selectively diffused sequentially into the surface region of the semiconductor substrate 19. Thereby, as shown in FIG. 3C, the base region 13 and the source region 14 are formed in the semiconductor substrate 19, that is, the surface region of the drift region 12. Here, the N-type diffusion region 30 remains and is exposed between the adjacent base regions 13.

このとき、半導体基板１９の外周縁端部の所定幅Ｘ５は、ポリシリコン膜（第２のポリシリコン膜３２）で覆われていない。このため、端部には、不可避的に上述した外周Ｐ型領域１７が、除去幅Ｘ５に応じた幅Ｘ２で形成される。ここで、上述したように、第２のポリシリコン膜３２は半導体基板１９の内周側に極力長く、広い幅で形成しているため、外周Ｐ型領域１７の幅Ｘ２は可能な限り狭いものとなる。これにより、これに隣接するチャネルストッパ１８の幅Ｘ４を可能な限り広くとることができ、したがって上述したような耐圧向上効果が得られることとなる。   At this time, the predetermined width X5 at the outer peripheral edge of the semiconductor substrate 19 is not covered with the polysilicon film (second polysilicon film 32). For this reason, the outer periphery P-type area | region 17 inevitably mentioned above is formed in the edge part by the width | variety X2 according to the removal width | variety X5. Here, as described above, since the second polysilicon film 32 is formed as long and wide as possible on the inner peripheral side of the semiconductor substrate 19, the width X2 of the outer peripheral P-type region 17 is as narrow as possible. It becomes. As a result, the width X4 of the channel stopper 18 adjacent to the channel stopper 18 can be made as wide as possible, and thus the breakdown voltage improving effect as described above can be obtained.

次に、半導体基板１９のドリフト領域１２を備える面上に、シリコン酸化膜等のシリコン系絶縁膜３４をＣＶＤ等により形成する。さらに、図４（ｄ）に示すように、シリコン系絶縁膜３４の、上述した第１および第２の凹部２４、２６を形成すべき領域に対応する部分に、第１および第２の開口３４ａ、３４ｂをエッチングにより形成する。このとき、第２の開口３４ｂは、半導体基板１９がその外周から所定幅Ｘ３で露出するように形成される。第２の開口３４ｂの形成幅Ｘ３は、例えば、チャネルストッパ１８の幅の中程まで半導体基板１９の表面が露出する程度とされる。   Next, a silicon-based insulating film 34 such as a silicon oxide film is formed on the surface of the semiconductor substrate 19 having the drift region 12 by CVD or the like. Further, as shown in FIG. 4D, the first and second openings 34a are formed in portions of the silicon-based insulating film 34 corresponding to the regions where the first and second recesses 24 and 26 are to be formed. , 34b are formed by etching. At this time, the second opening 34b is formed so that the semiconductor substrate 19 is exposed from the outer periphery with a predetermined width X3. The formation width X3 of the second opening 34b is, for example, such that the surface of the semiconductor substrate 19 is exposed to the middle of the width of the channel stopper 18.

次に、図４（ｅ）に示すように、シリコン系絶縁膜３４の第１および第２の開口３４ａ、３４ｂを介して半導体基板１９の表面を選択的にエッチングして、対応部分の第２の絶縁膜２３、第２のポリシリコン膜３２および半導体領域を除去しつつ、第１および第２の凹部２４、２６を形成する。このとき、チャネルストッパ１８には、表面に露出する浅い第２の領域１８ｂが形成される。   Next, as shown in FIG. 4E, the surface of the semiconductor substrate 19 is selectively etched through the first and second openings 34a and 34b of the silicon-based insulating film 34, so that the second portion of the corresponding part is etched. The first and second recesses 24 and 26 are formed while removing the insulating film 23, the second polysilicon film 32, and the semiconductor region. At this time, the shallow second region 18b exposed on the surface is formed in the channel stopper 18.

最後に、上記のようにして得られた半導体基板１９の両面上にアルミニウム等から構成されるソース電極２５とドレイン電極２０とを形成することにより、図１に示す半導体素子１０が完成する。   Finally, the source electrode 25 and the drain electrode 20 made of aluminum or the like are formed on both surfaces of the semiconductor substrate 19 obtained as described above, thereby completing the semiconductor element 10 shown in FIG.

本発明は、上記実施の形態に限られず、種々の変更、変形等が可能である。
例えば、上記実施の形態に示した半導体素子１０において、反対導電型とした構成としてもよい。 The present invention is not limited to the above-described embodiment, and various changes and modifications can be made.
For example, the semiconductor element 10 described in the above embodiment may be configured to have an opposite conductivity type.

また、上記発明の実施の形態では、ＭＯＳＦＥＴを例に説明したが、これに限定されない。本発明は、当然に、金属絶縁体絶縁ゲート型電界効果トランジスタ（Metal Insulator Semiconductor Field Effect Transistor；ＭＩＳＦＥＴ）や絶縁ゲート型バイポーラトランジスタ（Insulated Gate Bipolar Transistor；ＩＧＢＴ）、その他の絶縁ゲート型半導体素子に適用可能である。   In the embodiment of the present invention, the MOSFET has been described as an example. However, the present invention is not limited to this. The present invention is naturally applied to a metal insulator insulated gate field effect transistor (MISFET), an insulated gate bipolar transistor (IGBT), and other insulated gate semiconductor elements. Is possible.

本発明の実施の形態に係る半導体素子の断面構成を示す図である。It is a figure which shows the cross-sectional structure of the semiconductor element which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体素子の角部の断面構成を示す図である。It is a figure which shows the cross-sectional structure of the corner | angular part of the semiconductor element which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体素子の製造プロセスを示す図である。It is a figure which shows the manufacturing process of the semiconductor element which concerns on embodiment of this invention. 本発明の実施の形態に係る半導体素子の製造プロセスを示す図である。It is a figure which shows the manufacturing process of the semiconductor element which concerns on embodiment of this invention. 従来の半導体素子の構成を示す図である。It is a figure which shows the structure of the conventional semiconductor element. 従来の半導体素子の製造プロセスを示す図である。It is a figure which shows the manufacturing process of the conventional semiconductor element.

符号の説明Explanation of symbols

１０ 半導体素子
１１ ドレイン領域
１２ ドリフト領域
１３ ベース領域
１４ ソース領域
１５ Ｎ型半導体領域
１６ Ｐ型補助領域
１７ 外周Ｐ型領域
１８ チャネルストッパ
１８ａ 第１の領域
１８ｂ 第２の領域
１９ 半導体基板
２１ 第１の絶縁膜
２２ ゲート電極
２３ 第２の絶縁膜
２７ ＥＱＲ
２８ 導体膜 DESCRIPTION OF SYMBOLS 10 Semiconductor element 11 Drain region 12 Drift region 13 Base region 14 Source region 15 N-type semiconductor region 16 P-type auxiliary region 17 Peripheral P-type region 18 Channel stopper 18a First region 18b Second region 19 Semiconductor substrate 21 First substrate Insulating film 22 Gate electrode 23 Second insulating film 27 EQR
28 Conductor film

Claims (10)

半導体基板の一面を構成する第１導電型の第１半導体領域と、
前記第１半導体領域の端部の表面領域に形成された第２導電型の第２半導体領域と、
前記第１半導体領域の表面領域に前記第２半導体領域に隣接して形成され、前記第１半導体領域よりも不純物濃度の高い第１導電型の第３半導体領域と、
前記第１半導体領域の上方に設けられ、その端部側の一端が前記第３半導体領域の絶縁膜を介した上方にあるよう形成された導体膜と、
を備える、ことを特徴とする半導体素子。 A first semiconductor region of a first conductivity type constituting one surface of the semiconductor substrate;
A second semiconductor region of a second conductivity type formed in a surface region at an end of the first semiconductor region;
A third semiconductor region of a first conductivity type formed in a surface region of the first semiconductor region adjacent to the second semiconductor region and having a higher impurity concentration than the first semiconductor region;
A conductor film provided above the first semiconductor region and having one end on the end side located above the insulating film of the third semiconductor region;
A semiconductor element comprising: 前記第１半導体領域の表面領域の、前記第３半導体領域よりも内周側に形成された第２導電型の第４半導体領域をさらに備え、
前記第３半導体領域は、前記第１半導体領域と前記第４半導体領域との界面から形成される空乏層の外周側への広がりを抑制するために設けられている、ことを特徴とする請求項１に記載の半導体素子。 A second conductivity type fourth semiconductor region formed on the inner peripheral side of the surface region of the first semiconductor region with respect to the third semiconductor region;
The said 3rd semiconductor region is provided in order to suppress the expansion to the outer peripheral side of the depletion layer formed from the interface of a said 1st semiconductor region and a said 4th semiconductor region, The said 3rd semiconductor region is provided. 2. The semiconductor element according to 1. 前記導体膜は等電位リングを構成する、ことを特徴とする請求項１または２に記載の半導体素子。   The semiconductor element according to claim 1, wherein the conductor film constitutes an equipotential ring. 前記第３半導体領域は、相対的に深い深さを有する第１の領域と、相対的に浅い深さを有する第２の領域と、を備え、その露出面には、前記第１の領域と前記第２の領域とを隔てる段差が形成されている、ことを特徴とする請求項１乃至３のいずれか１項に記載の半導体素子。   The third semiconductor region includes a first region having a relatively deep depth and a second region having a relatively shallow depth, and the exposed surface includes the first region and the second region. 4. The semiconductor device according to claim 1, wherein a step that separates the second region is formed. 5. 前記第２の領域は、前記第２半導体領域と共通の平面を構成する、ことを特徴とする請求項４に記載の半導体素子。   The semiconductor element according to claim 4, wherein the second region constitutes a common plane with the second semiconductor region. 前記絶縁膜は、前記第１の領域を覆いかつ前記第２の領域を覆わないように形成されている、ことを特徴とする請求項４または５に記載の半導体素子。   6. The semiconductor element according to claim 4, wherein the insulating film is formed so as to cover the first region and not cover the second region. 前記導体膜の端部側の一端と、前記絶縁膜の端部側の一端と、前記第３半導体領域の段差と、は、共通の平面を構成する、ことを特徴とする請求項４乃至６のいずれか１項に記載の半導体素子。   The one end on the end side of the conductor film, the one end on the end side of the insulating film, and the step in the third semiconductor region form a common plane. The semiconductor element according to any one of the above. 前記第２の領域上に形成され、前記導体膜と前記第３半導体領域とを電気的に接続する接続用導体膜をさらに備える、ことを特徴とする請求項４乃至７のいずれか１項に記載の半導体素子。   8. The connection conductor film according to claim 4, further comprising a connection conductor film formed on the second region and electrically connecting the conductor film and the third semiconductor region. The semiconductor element as described. 第１導電型の第１半導体領域を一面に備える半導体基板を用意する工程と、
前記半導体基板の一面上に、その端部が第１の幅で露出するように、相対的に厚い第１の絶縁膜を形成する工程と、
前記半導体基板の一面に、相対的に薄い第２の絶縁膜を形成する工程と、
前記半導体基板の一面に、前記第１の絶縁膜をマスクとして、選択的に第１導電型の不純物を拡散させ、前記第１半導体領域よりも不純物濃度の高い第１拡散領域を形成する工程と、
前記半導体基板の一面上に、少なくとも前記半導体基板の端部を前記第１の幅よりも小さい第２の幅で残して覆う導体膜を形成する工程と、
前記導体膜をマスクとして、前記半導体基板の一面の表面領域に第２導電型の不純物を選択的に拡散させ、前記第１拡散領域よりも深い拡散深さでこれと隣接する第２拡散領域を形成する工程と、
前記第１の幅よりも小さくかつ前記第２の幅よりも大きい幅で、前記半導体基板の一面の端部をその上に形成された前記第２の絶縁膜と前記導体膜とともに除去する除去工程と、
を備える、ことを特徴とする半導体素子の製造方法。 Providing a semiconductor substrate having a first semiconductor region of a first conductivity type on one side;
Forming a relatively thick first insulating film on one surface of the semiconductor substrate such that an end of the semiconductor substrate is exposed with a first width;
Forming a relatively thin second insulating film on one surface of the semiconductor substrate;
Forming a first diffusion region having a higher impurity concentration than the first semiconductor region by selectively diffusing impurities of the first conductivity type on one surface of the semiconductor substrate using the first insulating film as a mask; ,
Forming a conductor film on one surface of the semiconductor substrate, covering at least an end portion of the semiconductor substrate with a second width smaller than the first width; and
Using the conductor film as a mask, a second conductivity type impurity is selectively diffused in a surface region of one surface of the semiconductor substrate, and a second diffusion region adjacent to the second diffusion region is formed at a diffusion depth deeper than the first diffusion region. Forming, and
A removing step of removing an end portion of one surface of the semiconductor substrate together with the second insulating film and the conductor film formed thereon with a width smaller than the first width and larger than the second width. When,
A method for manufacturing a semiconductor device, comprising: 前記端部に露出した前記第１拡散領域上に、前記端部に形成された前記導体膜と電気的に接続された接続用導体膜を形成する工程をさらに備える、ことを特徴とする請求項９に記載の半導体素子の製造方法。   The method further comprises the step of forming a connecting conductor film electrically connected to the conductor film formed at the end on the first diffusion region exposed at the end. 10. A method for producing a semiconductor device according to 9.
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