JPH11204632A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a specified breakdown strength to a semiconductor device by improving a breakdown voltage value in a depletion layer, without increasing the film thickness of an electrically insulating film on a semiconductor substrate. SOLUTION: This device is provided with a conductive layer 18, which is extended to the side of a first impurity region 12 in an electrically insulating film 14 on a semiconductor substrate 11 as a field relaxing means and is placed at approximately the same potential as that of the semiconductor board 11, and a third impurity region 19 which is formed in a surface of the semiconductor substrate 11, shows conductivity equal to that of the semiconductor board 11, has an impurity concentration which is higher is than the impurity concentration of the semiconductor substrate and is lower than an impurity concentration of a second impurity region 13, and is extended towards the first impurity region 12 and is formed apart from the first impurity region. In addition, an extended end 18a of a layer 18 to the side of the first impurity region 12 is placed closer to the side of the second impurity region 13 than an extended end 19a of the third impurity region 19 placed to the side of the firs impurity region 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device using a semiconductor substrate, and more particularly, to a semiconductor device in which electric field relaxation means for increasing withstand voltage is incorporated.

[0002]

2. Description of the Related Art In an integrated circuit formed by incorporating various circuit elements such as transistors into a semiconductor substrate, a conductive type opposite to the conductive type of the semiconductor substrate is provided on the surface of the semiconductor substrate as a functional part of the element. The first impurity region shown is formed. When a reverse voltage is applied between the impurity region and the semiconductor substrate via an electric path extending from the impurity region to the oxide film covering the semiconductor substrate, a reverse voltage is applied to the semiconductor substrate under the electric path according to the voltage value. A depletion layer extends from the impurity region along the surface.

When this depletion layer reaches the peripheral circuit portion,
This has a strong adverse effect on the electrical characteristics of the circuit portion. As a technique for preventing the depletion layer from extending to the peripheral circuit, a second impurity region having the same conductivity type as the semiconductor substrate and having an impurity concentration higher than the impurity concentration of the substrate is provided on the semiconductor substrate as a channel stopper. There is a technology to provide.

When a reverse voltage is applied between the semiconductor substrate and the first impurity region, basically, a junction between the first impurity region to which the reverse voltage is applied and the semiconductor substrate is formed. The withstand voltage of the element including the first impurity region is determined depending on the withstand voltage in the surface. However, when a channel stopper including the second impurity region for preventing the extension of the depletion layer is provided, the depletion layer extending toward the channel stopper as the reverse voltage increases reaches the channel stopper. A strong electric field is likely to be concentrated on the depletion layer whose elongation is prevented by the stopper. Therefore, in a semiconductor device in which a channel stopper is incorporated, breakdown related to a depletion layer may occur at a breakdown voltage value lower than the above-described limit voltage value of the junction surface. The above-described breakdown in the depletion layer causes a decrease in breakdown voltage of the semiconductor device.

[0005] Therefore, as an electric field relaxation means for relaxing the concentration of the electric field in the depletion layer, "I Three Transactions on Electron Devices" published in August, 1987. ON
ELECTRON DEVICES) ", Volume ED-34, Issue 8, Issue 181
It has been proposed to form an electric field reduction region (FRR) as described on pages 6-1821.

The electric field reduction region is composed of a third impurity region having the same conductivity type as the channel stopper serving as the second impurity region, and is formed along the surface of the semiconductor substrate from the channel stopper along the surface of the semiconductor substrate. It is formed to extend toward the first impurity region to which a reverse voltage is applied.

The electric field reduction region suppresses the extension of the depletion layer and allows the extension of the depletion layer in response to an increase in the reverse voltage between the semiconductor substrate and the first impurity region, thereby reducing the electric field in the depletion layer. It acts to reduce concentration. This relaxation of the electric field reduction region prevents breakdown of the depletion layer in the electric field reduction region, and increases the reverse voltage value when the depletion layer reaches the channel stopper. The electric field relaxation effect of the electric field reduction region changes in association with the change in the impurity concentration of the third impurity region forming the electric field reduction region, and is higher than the impurity concentration of the semiconductor substrate and higher than the impurity concentration of the channel stopper. The depletion layer has the highest withstand voltage due to the predetermined depletion layer suppression effect obtained at a low predetermined value.

Therefore, in the case where the impurity concentration deviates from the predetermined value, the effect of suppressing the extension of the depletion layer by the electric field reduction region is too large or too small in accordance with the increase or decrease. , The pressure resistance in the depletion layer is
It is lower than the pressure resistance obtained at a predetermined value. For this reason, the impurity concentration of the electric field reduction region is set to a predetermined value so that the highest withstand voltage can be obtained by the electric field reduction region.

[0009]

However, in order to obtain a desired breakdown voltage with the electric field reduction region, the breakdown voltage in the depletion layer is reduced by the first impurity region to which the reverse voltage is applied and the semiconductor substrate. In order for the voltage to be equal to or higher than the threshold voltage at the bonding surface of
The electrical insulating film such as an oxide film disposed between the conductive region extending from the impurity region needs a large film thickness of about 2.5 μm or more. Therefore, in order to reduce the thickness of the semiconductor device, there has been a demand for a semiconductor device capable of obtaining a predetermined withstand voltage with an electric insulating film having a smaller thickness.

As means for suppressing the extension of the depletion layer to the channel stopper, a shield electrode having the same potential as that of the semiconductor substrate is provided in the insulating film on the semiconductor substrate in addition to the electric field reduction region. There is a technique for extending the depletion layer from the region toward the first impurity region. The shield electrode strongly restricts the extension of the depletion layer at the extension end position toward the first impurity region.

Therefore, as described above, optimum pressure resistance is exhibited only with a predetermined depletion layer suppression effect, and if the depletion layer extension suppression effect is too small or too large, the pressure resistance in the depletion layer is too large. Conversely, even if the conventional relaxation means comprising the electric field reduction region and the relaxation means comprising the shield electrode for more strongly restricting the elongation of the depletion layer are combined, depending on these combinations, each may be used alone. It was thought that only lower pressure resistance could be obtained than in the case of the above.

[0012]

However, the present inventors have found that when the two electric field relaxation means described above are combined in a specific relationship, a very excellent breakdown voltage characteristic can be obtained as compared with the case where each of them is used alone. I found something. In addition, the inventors of the present application have found that the effect of restricting the extension of the depletion layer by the shield electrode is reduced, thereby allowing the stepwise extension of the depletion layer, thereby alleviating the electric field concentration effect in the depletion layer. .

The present invention relates to a semiconductor substrate showing either p-type or n-type conductivity, and a semiconductor substrate showing the other p-type or n-type conductivity, on an electric insulating film provided on the surface of the semiconductor substrate. A first impurity region to which a reverse potential is applied between the first impurity region and the semiconductor substrate via an electric path extending to the first impurity region; and a depletion layer that is to extend along the electric path from the first impurity region under the electric circuit. A second impurity region formed on the surface of the semiconductor substrate at a distance from the first impurity region and having the same conductivity type as the semiconductor substrate and having an impurity concentration higher than the impurity concentration of the semiconductor substrate; The present invention is directed to a semiconductor device including an electric field relaxing means for preventing concentration of an electric field in a depletion layer.

According to the present invention, the electric field relaxation means extends from a region corresponding to the second impurity region in the electric insulating film to the first impurity region side beyond the region and has substantially the same potential as the semiconductor substrate. A conductive layer placed on the surface of the semiconductor substrate;
And a second impurity region formed between the second impurity region and having the same conductivity type as the semiconductor substrate, having an impurity concentration higher than the impurity concentration of the semiconductor substrate and lower than the impurity concentration of the second impurity region. A third impurity region extending from or near the impurity region toward the first impurity region and formed at a distance from the first impurity region;
The extension end of the conductive layer toward the first impurity region is closer to the second impurity region than the extension end of the third impurity region toward the first impurity region.
Is located on the side of the impurity region.

The third impurity region suppresses the extension of the depletion layer while suppressing the extension of the depletion layer in response to the increase in the reverse voltage between the semiconductor substrate and the first impurity region, as in the conventional electric field reduction region. Is allowed to reduce the concentration of the electric field in the depletion layer. The conductive layer extending from the region corresponding to the second impurity region in the electric insulating film to the first impurity region beyond the region and being substantially at the same potential as the semiconductor substrate is formed by a conventional shield layer. As in the case of the electrode, the extension of the depletion layer is strongly restricted at the extension end position toward the first impurity region.

The extended end of the conductive layer toward the first impurity region is located closer to the second impurity region than the extended end of the third impurity region toward the first impurity region. By satisfying this particular relationship,
The breakdown voltage value in the depletion layer, which cannot be obtained by individual relaxation means and is considered to cause a significant reduction by a combination of both relaxation means, can be significantly increased. It was confirmed that withstand voltage characteristics could be given.

Further, according to the present invention, the electric field relaxation means extends from a region corresponding to the second impurity region in the electric insulating film to the first impurity region side beyond the region and substantially extends from the semiconductor substrate. Including a conductive layer at the same potential, the conductive layer,
When viewed in a longitudinal section along the direction of extension of the circuit, which coincides with the direction of extension of the depletion layer, a plurality of lines are arranged at intervals in the direction of extension of the circuit along their respective widths. Characterized in that slits are defined between the narrow portions.

According to the conductive layer in which the slit is defined, when the depletion layer tries to extend toward the channel stopper, which is the second impurity region, as the reverse voltage increases, the second impurity region Elongation of the depletion layer is regulated stepwise by respective edges located on the first impurity region side of each narrow portion of the conductive layer defining the slit, which are arranged in alignment with the channel stopper. .

That is, the depletion layer whose extension is regulated by the edge of the narrow portion located on the side of the first impurity region is:
With the increase in the reverse voltage, before reaching the critical electric field value, the edge reaches the narrow portion adjacent to the narrow portion and located on the channel stopper side. After that, for each narrow portion, the depletion layer gradually expands toward the subsequent narrow portion before reaching the critical voltage value.
Elongation of the depletion layer can be appropriately controlled stepwise, and electric field concentration in the depletion layer can be effectively prevented.

As a result, the reverse voltage value at the time of reaching the channel stopper where the expansion of the depletion layer is finally constrained is increased, whereby the breakdown voltage value at the depletion layer is increased and the semiconductor device is reduced. The pressure resistance is improved. The predetermined electric field relaxation effect of the conductive layer having such a slit is as follows.
It is obtained only when the conductive layer is kept at substantially the same potential as the semiconductor substrate. Therefore, even if the conductive layer is used as a floating electrode, it is not possible to expect the floating electrode to function to gradually suppress the expansion of the depletion layer as in the present invention. Therefore, the reverse voltage when the depletion layer reaches the channel stopper is not expected. Cannot be set to a high value as in the conductive layer of the present invention. Therefore, the floating electrode cannot achieve the excellent electric field relaxation effect as in the present invention.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the illustrated embodiments. <Embodiment 1> FIG. 1 shows Embodiment 1 of a semiconductor device according to the present invention. The semiconductor device 10 according to the present invention is a diode in the illustrated example, and is incorporated in a semiconductor substrate 11 made of N-type silicon having a specific resistance value of, for example, 20 Ω · cm.

On the surface of the semiconductor substrate 11, a first impurity region 12 is formed as a cathode. The first impurity region 12 exhibits P-type conductivity, which is opposite to the conductivity type of the semiconductor substrate 11. On the surface of the semiconductor substrate 11, a second impurity region 13 is formed at a distance from the first impurity region 12. The second impurity region 13 is a high-concentration impurity region having the same conductivity type as that of the semiconductor substrate 11 and having a higher impurity concentration than that of the semiconductor substrate 11. This second impurity region 13 is used as a cathode of a diode, and also functions as a channel stopper described later.

An electric insulating film 14 is formed on the surface of the semiconductor substrate 11 by, for example, thermal oxidation of the semiconductor substrate 11. In the illustrated example, the insulating film 14 directly covers the semiconductor substrate 11 and has a thickness of, for example, 1 μm.
4a and an upper layer 14b partially covering the lower layer and having a thickness of, for example, 1 μm.

A contact hole 15 for exposing the first impurity region 12 is formed in a portion of the lower layer 14a exposed from the upper layer 14b, and a lead line extending on the insulating film 14 through the contact hole 15 is formed. That is, the electric path 16 is connected to the first impurity region 12. The electric circuit 16 extends to a region above the second impurity region 13. Further, a well-known wiring (not shown) is connected to the second impurity region 13, and the first impurity region 12 is used as an anode through the wiring and an electric path 16 extending from the first impurity region 12. The second impurity region 13 is used as a cathode, and a reverse voltage is applied between the two.

When a reverse voltage is applied between the anode 12 and the cathode 13, as shown by the phantom line in FIG. Depletion layer 17 (17) toward impurity region 13 of
a, 17b, 17c and 17d) extend. In the illustrated example, since the cathode 13 has the same conductivity type as the semiconductor substrate 11 and is formed of the high-concentration impurity region 13 having a higher impurity concentration than the substrate, the depletion layer 17 extends due to an increase in the reverse voltage value. However, the extended end does not extend beyond the second impurity region 13, so that the second impurity region 13 serving as a cathode also functions as a channel stopper. The channel stopper function of the second impurity region 13 prevents the depletion layer 17 from affecting the peripheral circuit.

After the depletion layer 17 reaches the second impurity region 13 with the increase in the reverse voltage value, if the voltage value further increases, the extension of the depletion layer 17 is restricted. Therefore, the electric field is easily concentrated in the depletion layer 17. The conductive layer 18 and the third impurity region 19 are provided as electric field relaxation means for suppressing the breakdown in the depletion layer 17 due to the concentration of the electric field and increasing the breakdown voltage value in the depletion layer 17. .

In the illustrated example, the conductive layer 18 is formed of the insulating film 14.
And a conductor formed between the lower layer 14a and the upper layer 14b. The conductive layer 18 can be formed of polysilicon having a thickness of, for example, 1000 ° and doped with phosphorus as an impurity. The conductive layer 18 is formed in the second impurity region 1
The region extends from the region corresponding to 3 to the side where the first impurity region 12 is provided beyond the region and returns to the extended end 18a. The conductive layer 18 is maintained at the same potential as the semiconductor substrate 11 by being electrically connected to the semiconductor substrate 11.

The third impurity region 19 is formed in the semiconductor substrate 11
Is formed between the first impurity region 12 and the second impurity region 13 on the surface of the substrate. Third impurity region 19
Represents the same conductivity type as that of the semiconductor substrate 11, and the impurity concentration thereof is set higher than that of the semiconductor substrate 11 and lower than that of the second impurity region 13. The impurity concentration of the third impurity region 19 is, for example, within the above-described concentration range, as in the conventional electric field reduction region (FFR), for example, the impurity concentration that provides the highest breakdown voltage value when used alone. It is desirable to adopt a value.

In the first embodiment, the third impurity region 19
The second impurity region 13 extends from the second impurity region 13 to the side where the first impurity region 12 is provided, continuing to the impurity region 13, and returns to the extended end 19 a spaced from the first impurity region 12. Further, the conductive layer 18 does not extend to the side of the first impurity region 12 beyond the extended end 19a of the third impurity region 19, and therefore, the extended end 18a of the conductive layer 18 is Region 19 is located closer to second impurity region 13 than extension end 19a.

In the semiconductor device 10 of the specific example 1 in which the conductive layer 18 and the third impurity region 19 are provided, the first impurity region 12 serving as the anode and the second impurity region 13 have the same potential via the electric path 16. When a reverse voltage is applied between the semiconductor substrate 11 and the semiconductor substrate 11, as shown by the phantom line in FIG. The depletion layer 17a extends along the surface of the eleventh layer. The leading ends of the depletion layers 17a are denoted by reference numerals 17b and 17c in FIG.
As shown by, the semiconductor substrate 11 sequentially extends toward the second impurity region 13 along the surface of the semiconductor substrate 11.

Depletion layer 1 on the surface of semiconductor substrate 11
When the tip of 7 reaches the third impurity region 19, the third impurity region 19 regulates the movement of the tip of the depletion layer 17, that is, the extension of the depletion layer 17 with the increase in the reverse voltage value. In order to prevent the breakdown from occurring in the depletion layer 17, the extension is properly performed.

Due to the extension of the depletion layer 17, as shown by reference numeral 17 c in FIG. 1, the tip of the depletion layer 17 on the surface of the semiconductor substrate 11 becomes the extension end 18 of the conductive layer 18.
When the position indicated by the symbol A corresponding to a is reached, the movement of the depletion layer 17 on the surface of the semiconductor substrate 11 is prevented. Therefore, when the reverse voltage value further increases, the reverse voltage value increases. The lower part of the tip of the depletion layer 17c is, as indicated by reference numeral 17d, a second impurity region 13c.
It swells greatly toward. At this time, the largest concentration of the electric field is observed in the depletion layer 17 in the portion indicated by the symbol A.

A portion A where the largest electric field concentration occurs
As long as the breakdown does not occur, the depletion layer 17 reaches the second impurity region 13 as indicated by reference numeral 17d at the lower portion bulging below the portion indicated by reference numeral A.
The second impurity region 13 prevents the depletion layer 17 from extending beyond the second impurity region 13 by the channel stopper function as described above.

The breakdown voltage characteristics of the semiconductor device 10 including the electric field relaxation means composed of the combination of the conductive layer 18 and the third impurity region 19 enabling the depletion layer 17 to extend as described above are different from those of the conventional semiconductor device. A comparison is shown in the graph of FIG.

The horizontal axis of the graph of FIG. 2 indicates the maximum thickness dimension value (μm) of the insulating film 14, and the vertical axis indicates the breakdown voltage value (V) of the semiconductor device. A characteristic line 20 indicates the withstand voltage characteristic of the semiconductor device 10 according to the present invention, a characteristic line 21 indicates that of the conventional example in which only the shield electrode is provided as the electric field relaxation means, and a characteristic line 22 indicates the electric field relaxation means. A conventional example in which only an electric field reduction region is provided is shown.

In the semiconductor device 10 according to the present invention, when the thickness of the insulating film 14 exceeds 2.5 μm, a high breakdown voltage exceeding 400 V can be obtained. This is because the breakdown voltage at the location indicated by the symbol A in the depletion layer 17 is at least the anode 1
This means that the junction breakdown voltage between the semiconductor substrate 2 and the semiconductor substrate 11 has become equal to or higher than the withstand voltage. Further, in the semiconductor device 10 according to the present invention, even when the thickness of the insulating film 14 is 2 μm, the semiconductor device 10 exhibits a withstand voltage characteristic of approximately 400 V which is close to the junction withstand voltage. It is considered that the breakdown voltage at this time is a breakdown voltage value at a location indicated by the symbol A in the depletion layer 17.

On the other hand, in the prior art shown by the characteristic lines 21 and 22, when the thickness of the insulating film exceeds 2.5 μm, the breakdown voltage similar to that in the present application is obtained only by the one prior art shown by the characteristic line 22. Although a value can be obtained, when the thickness of the insulating film is 2 μm, the breakdown voltage is much lower than 350 V in all cases. This means that in the prior art, when the thickness of the insulating film is 2 μm, the breakdown voltage in the depletion layer becomes a value significantly lower than 350 V, and the electric field relaxation effect as in the present application cannot be obtained.

Thus, the semiconductor device 1 according to the present invention
According to 0, both electric field relaxation means, which were thought to cause a reduction in the electric field relaxation effect when a conventional conductive layer and an impurity region for electric field relaxation are simply combined, satisfy the positional relationship of a specific combination. As a result, even if a thin insulating film having a thickness of 2 μm is used as the insulating film 14, an extremely high breakdown voltage of approximately 400 V, which is about 80 V higher than the conventional breakdown voltage value of such a thin insulating film, can be obtained. This makes it possible to improve the breakdown voltage characteristics.

Therefore, the withstand voltage of the semiconductor device can be increased and the thickness of the semiconductor device can be reduced.
It is possible to reduce the size of a semiconductor device having excellent withstand voltage.

<Embodiment 2> In the embodiment 2 shown in FIG. 3, the third impurity region 19 is arranged at a distance from the second impurity region 13 and is close to the second impurity region 13. The base end 19b of the second impurity region 13
The extension end 18a of the conductive layer 18 is located at an intermediate position corresponding to the distance from the impurity region 13.

In the semiconductor device 10 of the second embodiment, the conductive layer 1
8 is located at the intermediate position, the movement of the tip of the depletion layer 17 extending along the surface of the semiconductor substrate 11 is restricted by the conductive layer 18, that is, the code A corresponding to the extended end 18a. Is located between the third impurity region 19 and the second impurity region 13.

Therefore, in the specific example 2, the position indicated by the symbol A is in the semiconductor substrate 11, and the semiconductor substrate 11 has the respective impurity concentrations of the third impurity region 19 and the second impurity region 13. Is lower than that of the third impurity region 1 based on the difference in the impurity concentration.
9 shows a lower suppression effect than the extension suppression effect of the depletion layer 17 in FIG. Therefore, after the tip of the depletion layer 17c reaches the position indicated by the symbol A, the depletion layer 17c expands toward the second impurity region 13 below the tip as the reverse voltage increases. In this case, the bulge does not receive the strong constraint as shown in the first embodiment.

Accordingly, the semiconductor device 10 of the second embodiment is
According to the above, when the reverse voltage increases after the tip of the depletion layer 17 c reaches the position indicated by the symbol A, the depletion layer 17 c
Since the effect of suppressing the extension of d can be reduced, and the rate of increase of the electric field at the position indicated by the symbol A can be reduced, the breakdown of the depletion layer 17 at the position indicated by the symbol A can be reduced. This can be more reliably prevented, and further excellent pressure resistance can be obtained.

<Embodiment 3> In the semiconductor device 10 of Embodiment 3 shown in FIG. 4 and FIG.
8 'is provided. 4, the insulating film 14 shown in FIG. 5 is omitted for simplification of the drawing.

The conductive layer 18 'of the third embodiment includes a plurality of narrow portions 23 having a uniform width dimension w of, for example, 3 μm.
As clearly shown in FIG. 5, each narrow portion 23 has a circuit 1 extending from the first impurity region 12 which is an anode.
6 along the respective width directions in the direction of extension and in the direction of extension of the electric circuit 16, for example, an interval s of, for example, 3 μm.
Are arranged in an aligned manner. Each narrow part 23
Is electrically connected to the second impurity region 13 via a connection portion 24 arranged along the electric path 16 as shown in FIG. In the example shown in FIG. 4, the second impurity region 13 functioning as a cathode and a channel stopper is replaced with the first impurity region 12 functioning as an anode.
Is formed.

In the semiconductor device 10 according to the third embodiment, when a reverse voltage is applied between the first impurity region 12 and the semiconductor substrate 11, as shown by a virtual line in FIG. The depletion layer 17 a extends along the surface of the semiconductor substrate 11 from the anode 12 toward the second impurity region 13 below the anode 16.

With the increase in the reverse voltage value, the leading edge of the depletion layer 17 on the semiconductor substrate 11 is moved closer to the edge portion 23 of the narrow portion 23 located closest to the first impurity region 12.
When a reaches a, the extension of the depletion layer 17a is regulated at this point A1.

Further, when the voltage value increases, the distance from the first impurity region 12 to the position corresponding to the slit s defined between the narrow portions 23 in accordance with the increase in the voltage value. (17′a, 1 ′
7'b...) Are formed.

When the electric field at the position indicated by the point A1 of the depletion layer 17a approaches the critical value due to the increase in the voltage value, before the electric field value reaches the critical value, the tip of the depletion layer 17a is moved to the forward position. Are separated from each other. As a result, the depletion layer is allowed to extend by the length up to the position indicated by the reference symbol A2, so that the electric field is relaxed.

Hereinafter, as the voltage value increases, the depletion layer 1
7, the growth is allowed stepwise (depletion layers 17a, 17a).
b, 17c), when the depletion layer 17 finally reaches the second impurity region 13, the channel stopper function of the second impurity region 13 prevents the depletion layer 17 from extending.

The semiconductor device 10 provided with the conductive layer 18 'which enables the depletion layer 17 to expand stepwise as described above.
FIG. 6 shows a comparison between the breakdown voltage characteristic of the semiconductor device and that of the conventional semiconductor device.
Is shown in the graph.

The horizontal and vertical axes of the graph of FIG. 6 are the same as those in the graph of FIG. A characteristic line 20 'shown in the graph of FIG. 6 shows the breakdown voltage characteristic of the semiconductor device 10 of the third embodiment, and a characteristic line 21 shows that of the conventional example in which a continuous shield electrode is provided as electric field relaxation means. Show.

In the conventional example showing the characteristic line 21, when the thickness of the insulating film is 3 μm or less, only a low breakdown voltage which does not reach the junction breakdown voltage can be obtained. On the other hand, in the semiconductor device 10 of the third embodiment, as in the first embodiment, when the thickness of the insulating film 14 exceeds 2.5 μm, a high breakdown voltage exceeding 400 V can be obtained. Even if the thickness of the insulating film 14 is 2 μm, a high breakdown voltage exceeding 350 V, which is more than about 45 V higher than the breakdown voltage obtained in the conventional example, and higher than the conventional one can be obtained. Withstand voltage characteristics can be obtained.

<Embodiment 4> In the embodiment 3, the conductive layer 18 'having the narrow portion 23 having a uniform width is provided. On the other hand, the semiconductor device 1 of the specific example 4 shown in FIG.
0, the narrow portion 2 located on the second impurity region 13
The width dimension of 3 'is made substantially equal to that of the second impurity region 13, so that the narrow portion 23' of the conductive layer 18 'is formed on the second impurity region 13 as shown in FIG. Can be continuously covered. Further, in order to improve the breakdown voltage of the semiconductor device 10, as shown in FIG. 4, the edge portion 13 located on the side of the first impurity region 12 of the impurity region 13 is formed.
It is desirable that a corresponds to the slit position of the conductive layer 18 '. As a result, the depletion layer 17 becomes the second impurity region 1
3, the reverse voltage value can be increased.

<Embodiment 5> In the semiconductor device 10 of Embodiment 5 shown in FIG. 8, the conductive layer 18 'has a lattice shape. As shown in FIGS. 4 and 8, the second impurity region 13
Is arranged around the first impurity region 12, when the longitudinal dimension is increased so that the narrow portion 23 as shown in FIG. The depletion layer extends along the longitudinal direction below the narrow portion, and as a result, is immediately short-circuited to the second impurity region 13, thereby impairing the function as the electric field relaxation means.

However, as shown in the specific example 5 of FIG. 8, by using the lattice-shaped conductive layer 18 ', as described along the specific example 4, the depletion layer 17 in the extending direction of the electric circuit 16 is formed. In addition to being able to control the growth stepwise, the expansion of the depletion layer 17 in the width direction of the electric circuit 16 can also be controlled stepwise. This prevents the short-circuit phenomenon caused by the extension of the conductive layer 18 ′ in the width direction of the circuit 16 and prevents the conductive layer 18 ′ from crossing the second impurity region 13 so that the conductive layer 18 ′ crosses the width of the circuit 16. Direction.

Therefore, according to the lattice-shaped conductive layer 18 ',
The conductive layer can be extended in the width direction of the electric circuit 16 without causing the above-described short-circuit phenomenon caused by the extension of the conductive layer 18 'in the electric circuit 16 in the width direction. The degree of freedom of wiring for leading the connection portion 24 for connecting to the impurity region 13 is increased.

<Embodiment 6> In the semiconductor device 10 of Embodiment 6 shown in FIG. 9, the conductive layers 18 'have dimensions different from each other so as to allow concentric arrangement with each other. And a plurality of narrow portions 23 having a rectangular frame shape. Each narrow portion 23 is connected to second impurity region 13 via connection portion 24. In the specific example 6, since the connection portion 24 can be provided at an arbitrary portion within a range of 360 degrees around the first impurity region 12, the arrangement of the connection portion 24 is smaller than that of the specific example 5. The degree of freedom is further increased.

<Embodiment 7> In the semiconductor device 10 of the embodiment 7 shown in FIG. 10, the conductive layer 18 'has the width dimensions (W1, W2, W3, W4, W5) of the plurality of narrow portions 23 and 23'. ) Is from the narrow portion 23 at the distal end position on the first impurity region 12 side to the narrow width portion 23 ′ at the base end position on the second impurity region 13 side.
For example, 1 μm, 2 μm, 3 μm and 4 μm
The number gradually increases, such as m. The slit width s between the narrow portions 23 and 23 ′ is, for example, 3 μm, and is the same as each other.

In the semiconductor device 10 of the embodiment 7, the embodiment 3
As described above, with the increase of the reverse voltage applied between the first impurity region 12 and the semiconductor substrate 11, the position of the leading end of the depletion layer 17 is changed to each narrow portion 23.
First impurity regions 12 at
A corresponding to the proximity edge 23a located at a position close to
1, A2, A3, A4, and A5 are defined step by step.

From this, as the voltage value increases,
The position of the tip of the depletion layer 17 is sequentially changed to each point A1, A2, A3, A4,
Go to A5. By the way, as described above, each narrow portion 2
3 and 23 'are the same, but each width dimension (W1, W2) of the plurality of narrow portions 23 and 23' is the same.
2, W3, W4, W5) gradually increase, so points A1, A2, A3, A
4, Each interval between A5 gradually increases.

Therefore, according to the seventh embodiment, as the voltage value increases, the position of the tip of the depletion layer 17 is sequentially changed at each point A.
When moving to 1, A2, A3, A4, and A5, the rate of extension of the depletion layer with respect to the increase in the voltage value increases, so that the electric field relaxation effect further increases.

The horizontal and vertical axes of the graph of FIG. 11 are the same as those in the graphs of FIGS. 2 and 6, respectively. A characteristic line 20 'shown in the graph of FIG. 11 shows the breakdown voltage characteristics of the semiconductor device 10 of the third embodiment, and a characteristic line 25
13 shows the breakdown voltage characteristics of Example 7. Specific example 7 indicated by a characteristic line 25
According to the above, even if the thickness of the insulating film is 2 μm,
A high breakdown voltage that greatly exceeds the junction withstand voltage of 400 V is obtained.

<Embodiment 8> In the embodiment 7, an example was shown in which the width of the narrow portions 23 and 23 'was gradually increased, but each narrow portion except the narrow portion 23' on the second impurity region 13 was shown. The width of the width portion 23 is set to the same value, for example, 2 μm. Instead of this width, the slit width s between the narrow portions 23 and 23 ′ is set to the slit S 1 located on the side of the first impurity region 12.
, The width dimension is gradually reduced, for example, 5 μm, 4 μm, 3 μm, and 2 μm from the second impurity region 13 toward the slit S4.

According to the eighth embodiment, the points A1, A2, A3, A3 as described above are obtained without gradually reducing the width of each narrow portion 23.
4, The interval between A5 can be gradually increased. Therefore, when the narrow portion 23 is formed by photolithography, the narrow portion 23 having a narrow width as in the specific example 7 is not formed, and therefore, high precision for obtaining the narrow portion 23 having a fine width dimension is obtained. Since the distance between the points A1, A2, A3, A4, and A5 at which the tip position of the depletion layer 17 moves can be gradually increased with high accuracy without the need for the control technique of Semiconductor device 10 having the same breakdown voltage characteristics as
Can be manufactured.

<Embodiment 9> As shown in Embodiment 9 of FIG. 13, the thickness of the insulating film 14 on the semiconductor substrate 11 can be reduced near the tip of the conductive layer 18 '. By reducing the thickness of the insulating film 14, the effect of suppressing the extension of the depletion layer 17 is reduced, whereby the number of the narrow portions 23 of the conductive layer 18 'can be reduced. , The size of the semiconductor device 10 can be reduced.

<Embodiment 10> In the semiconductor device 10 of the embodiment 10 shown in FIG.
8 'and the third impurity region 19 are used in combination. As described in the specific examples 1 and 2, the impurity concentration of the third impurity region 19 indicates the same conductivity type as that of the semiconductor substrate 11, and the impurity concentration thereof is higher than that of the semiconductor substrate 11 and the second impurity concentration. It is set lower than that of impurity region 13. Also, the tip of the conductive layer 18 ',
That is, the edge 18 a ′ located on the side of the first impurity region 12 of the narrow portion 23 closest to the first impurity region 12 is connected to the first impurity region 12 of the second impurity region 13. It is closer to the second impurity region 13 than the adjacent extension end 19a.

According to the semiconductor device 10 of the tenth embodiment, the conductive layer 18 ′ and the third impurity region 1 serving as both relaxation means are provided.
With the combination of 9, a stable and higher withstand voltage characteristic can be obtained irrespective of variation in the thickness dimension of the insulating film 14.

In the above description, a diode is shown as an example of the semiconductor device according to the present invention. However, the present invention is not limited to this, and can be suitably applied to, for example, a MOS transistor and other semiconductor elements.

[0070]

According to the present invention, as described above, the extending end of the conductive layer toward the first impurity region is set to be longer than the extending end of the third impurity region toward the first impurity region. Is also located on the side of the second impurity region, the breakdown voltage value in the depletion layer can be significantly increased, whereby the thickness of the electrical insulating film on the semiconductor substrate does not increase, A predetermined withstand voltage characteristic can be given to the semiconductor device.

According to the present invention, as described above,
The conductive layer, in which the slit is defined and maintained at substantially the same potential as the semiconductor substrate, appropriately and gradually regulates the extension of the depletion layer from the second impurity region toward the channel stopper, so that the electric field in the depletion layer is reduced. Concentration is effectively prevented,
Since the reverse voltage value can be increased when the elongation of the depletion layer reaches the channel stopper that is finally constrained, the increase in the breakdown voltage value in the depletion layer causes Without increasing the thickness dimension,
The withstand voltage of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a semiconductor device of Example 1 according to the present invention.

FIG. 2 is a graph showing a comparison between the semiconductor device of Example 1 and a conventional semiconductor device in terms of the relationship between their breakdown voltage and the thickness of an insulating film.

FIG. 3 is a cross-sectional view showing a semiconductor device of Example 2 according to the present invention.

FIG. 4 is a plan view schematically showing a part of a semiconductor device according to Embodiment 3 of the present invention;

5 is a cross-sectional view taken along line VV shown in FIG.

FIG. 6 is a graph showing a comparison between the semiconductor device of Example 3 and a conventional semiconductor device in terms of the relationship between their breakdown voltage and the thickness of an insulating film.

FIG. 7 is a cross-sectional view illustrating a semiconductor device of Example 4 according to the present invention.

FIG. 8 is a plan view schematically showing a part of a semiconductor device of Example 5 according to the present invention.

FIG. 9 is a plan view schematically showing a part of a semiconductor device of Example 6 according to the present invention.

FIG. 10 is a sectional view showing a semiconductor device of Example 7 according to the present invention.

FIG. 11 is a graph showing a comparison between the semiconductor device of Example 7 and a conventional semiconductor device in terms of the relationship between their breakdown voltage and the thickness of an insulating film.

FIG. 12 is a sectional view showing a semiconductor device of Example 8 according to the present invention.

FIG. 13 is a sectional view showing a semiconductor device of Example 9 according to the present invention.

FIG. 14 is a cross-sectional view illustrating a semiconductor device of Example 10 according to the present invention.

[Explanation of symbols]

 Reference Signs List 10 semiconductor device 11 semiconductor substrate 12 first impurity region 13 second impurity region 14 insulating film 16 electric path 17 (17a, 17b ...) depletion layer 18, 18 'conductive layer 19 third impurity region 23, 23' conductive layer Narrow part

Claims (10)

[Claims] 1. A semiconductor substrate showing either a p-type or n-type conductivity type and a p-type or n-type conductivity type on an electric insulating film provided on a surface of the semiconductor substrate. A first impurity region to which a reverse potential is applied between the semiconductor substrate and the semiconductor substrate via an extending electric path, and a depletion layer extending from the first impurity region below the electric circuit along the electric circuit. A second impurity region formed on the surface of the semiconductor substrate at a distance from the first impurity region, the second impurity region having one conductivity type and having an impurity concentration higher than the impurity concentration of the semiconductor substrate; An electric field relaxing means for preventing concentration of an electric field in the depletion layer, wherein the electric field relaxing means removes the region from a region corresponding to the second impurity region in the electric insulating film. Beyond the first
A conductive layer extending to the side of the impurity region and being substantially at the same potential as the semiconductor substrate; and a first conductive type formed between the first and second impurity regions on the surface of the semiconductor substrate. The semiconductor device has an impurity concentration higher than the impurity concentration of the semiconductor substrate and lower than the impurity concentration of the second impurity region, and extends from or near the second impurity region toward the first impurity region. And a third impurity region formed at a distance from the first impurity region, and an extended end of the conductive layer to the side of the first impurity region is located on the side of the first impurity region. A semiconductor device, which is located closer to the second impurity region than the extension end of the third impurity region. 2. The semiconductor device according to claim 1, wherein the third impurity region is formed at a distance from the second impurity region, and the extended end of the conductive layer is located at an intermediate position corresponding to the distance. Item 2. The semiconductor device according to item 1. 3. A semiconductor substrate having one of p-type or n-type conductivity and a p-type or n-type conductivity type, the semiconductor substrate being provided on an electric insulating film provided on a surface of the semiconductor substrate. A first impurity region to which a reverse potential is applied between the semiconductor substrate and the semiconductor substrate via an extending electric path, and a depletion layer extending from the first impurity region below the electric circuit along the electric circuit. A second impurity region formed on the surface of the semiconductor substrate at a distance from the first impurity region, the second impurity region having one conductivity type and having an impurity concentration higher than the impurity concentration of the semiconductor substrate; An electric field relaxing means for preventing concentration of an electric field in the depletion layer, wherein the electric field relaxing means removes the region from a region corresponding to the second impurity region in the electric insulating film. Beyond the first
A conductive layer extending to the side of the impurity region and being substantially at the same potential as the semiconductor substrate, wherein the conductive layer is viewed in a longitudinal section along the extending direction of the electric circuit, and has a width direction in each of the extending directions. A plurality of narrow portions which are arranged along with each other and are arranged at intervals in the extending direction, and a slit is defined between the narrow portions. 4. The semiconductor device according to claim 3, wherein the conductive layer has a lattice-like planar shape. 5. Each of the narrow portions of the conductive layer has a first shape.
4. The semiconductor device according to claim 3, wherein said semiconductor device has an annular planar shape surrounding a region corresponding to said impurity region. 6. The semiconductor device according to claim 3, wherein an edge portion of said second impurity region close to said first impurity region corresponds to said slit position of said conductive layer. 7. The width dimension of the narrow portion of the conductive layer is different from the narrow portion disposed on the side of the second impurity region to the narrow portion disposed on the side of the first impurity region. 4. The semiconductor device according to claim 3, wherein the number gradually decreases toward the portion. 8. The width dimension of the slit of the conductive layer is:
4. The semiconductor device according to claim 3, wherein the number increases gradually from the slit located on the side of the second impurity region to the slit located on the side of the first impurity region. 9. The electrical insulating film according to claim 1, wherein a thickness dimension is gradually reduced from a portion corresponding to said second impurity region to a portion corresponding to said first impurity region. Item 4. The semiconductor device according to item 3. 10. The semiconductor device according to claim 1, wherein the relaxing means is further formed between a first impurity region and a second impurity region in a region corresponding to the conductive layer on the surface of the semiconductor substrate. Having an impurity concentration higher than that of the second impurity region and lower than the impurity concentration of the second impurity region, extending from the second impurity region toward the first impurity region, and A third impurity region formed at an interval from the first impurity region, and an extended end of the conductive layer toward the first impurity region is connected to the third impurity region toward the first impurity region. 4. The semiconductor device according to claim 3, wherein the second impurity region is located closer to the second impurity region than the extended end of the second impurity region.
13. The semiconductor device according to claim 1.