JPH10116998A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, where high-speed switching can be made by eliminating the fear of element breakdown by surge voltage, together with its manufacture. SOLUTION: In a semiconductor device which has a p anode region 14 and an n<-> cathode region 16 in contact through a pn junction, the first defective region 16a is provided in the position near the pn junction out of the n<-> cathode region 16 where a small number of carriers are accumulated in ON condition, and a small number of carries contributing to the reverse recovery current in its early stage after off inversion are reduced, whereby the rise of the reverse recovery current is made small so as to shorten the reverse recovery time. Furthermore, the second defective region g is provided in the position far from the first defective region 16a viewed from pn junction, whereby a small number of carriers contributing to the reverse recovery current in the later half of the reverse recovery time are reduced to converge the reverse recovery current in its early stage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a pn junction and a method of manufacturing the same, and more particularly, to reduce a reverse recovery charge and a surge voltage after a forward voltage is turned off. And a method of manufacturing the same.

[0002]

2. Description of the Related Art As one type of semiconductor device having a pn junction, there is a switching diode used together with a switching element such as a transistor for switching a current. The general structure thereof is as shown in FIG. 9, in which a p anode region 93, an n ⁻ region 95, and an n ⁺ cathode region 96 are formed in a semiconductor crystal such as Si, and an anode electrode 91 and a cathode electrode 98 are provided at both ends. Are provided. Here, a pn junction is located between the p anode region 93 and the n ⁻ region 95. As shown by a curve x in the graph of FIG. 10, the impurity concentration of the n ⁻ region 95 is lower than that of the p anode region 93. Has been lowered.

When a forward voltage is applied to this semiconductor device and a current flows, holes (holes) are injected from the p anode region 93 into the n ⁻ region 95 across the pn junction. The injected holes are minority carriers and recombine with electrons in the n ⁻ region 95 and disappear. The necessary electrons are supplied from the n ⁺ cathode region 96.

Here, when the applied voltage is inverted, the n ⁻ region 9
Since holes that have been injected into 5 and have not yet disappeared return to the p anode region 93 beyond the pn junction, a current I _R in the reverse direction transiently flows as shown in the graph of FIG. Since the reverse current I _R continues while holes remain in the n ⁻ region 95, the duration thereof (hereinafter referred to as “reverse recovery time T _R ”) is the lifetime of the minority carrier in the n ⁻ region 95. And several hundreds of microseconds. This hinders high-speed switching. Incidentally, called the reverse recovery charge Q _R reverse recovery time over the time integral to T _R of the reverse current I _R in the graph of FIG. 11, it means that energy loss is large and it is large.

[0005] JP-A-55-38058, technique to improve performance of the switching by shortening the reverse recovery time T _R is disclosed. In the semiconductor device disclosed in the same publication, generation-recombination centers (lattice defects such as hetero atoms) are distributed outside a region that becomes a depletion layer after voltage reversal in an n-type region by a method such as electron beam irradiation or ion irradiation. It was made. That is, if applied to FIG. 9, a region 96a in which lattice defects are distributed (see the curve y in the graph of FIG. 10) in the n ⁺ cathode region 96 outside the range in which the depletion layer spreads after the voltage reversal is provided. It is a thing. That is, since the lifetime is short minority carrier in the region 96a lattice defects exist many, in which the reverse recovery time T _R shortened and the reduction of the reverse recovery charge Q _R can be expected by providing such regions .

[0006]

However, the semiconductor device disclosed in the above publication has the following problems.

That is, in this semiconductor device, since the region where the lattice defects are distributed exists at a position far from the pn junction, the minority carriers in the region close to the pn junction such as the n ⁻ region 95 in FIG. Has not been shortened at all. The first half (the portion before the peak) of the reverse current I _R in FIG. 11 is caused by the minority carriers in this region, and the minority carrier at a position far from the pn junction as in the region 96a in FIG. This contributes to the latter half of the direction current I _R (the part after the peak). Therefore, the transient current characteristics are as shown by curve c in the graph of FIG. In curve c, since by shortening the reverse current I _R reverse recovery time without hardly reducing the peak value of T _R, the slope of the second half portion (dI _R / dt) is a steep. Since the product of the parasitic inductance L of the inclined dI _R / dt and the circuit is to be superimposed on the action reversed voltage as surge voltage, there is a case where the element is destroyed beyond the reverse breakdown voltage of the pn junction. Since there is a trade-off surge voltage becomes higher the more you reduce the reverse recovery time T _R, can not in practice be sufficiently reduced reverse recovery time T _R.

Accordingly, the present invention solves the above-mentioned problems of the prior art, that is, a semiconductor which can eliminate the trade-off between the reverse recovery time and the surge voltage, and can perform high-speed switching without fear of element destruction due to the surge voltage. It is an object to provide an apparatus together with a manufacturing method thereof.

[0009]

Means for Solving the Problems According to a first aspect of the present invention, there is provided a semiconductor device having one conductivity type semiconductor region and another conductivity type semiconductor region forming a pn junction. A semiconductor device in which a low-concentration region whose impurity concentration is lower than the impurity concentration of the other-conductivity-type semiconductor region is formed at least in a portion adjacent to a pn junction portion in a semiconductor region, wherein another low-concentration region has another impurity concentration. This is characterized by providing a first defect region having a higher lattice defect concentration than a portion.

In this semiconductor device, when a forward voltage is applied to cause a current to flow, carriers in the other conductivity type semiconductor region enter the low-concentration region beyond the pn junction. These carriers are minority carriers in the low-concentration region and recombine with the majority carriers and disappear, but disappear in the first defect region in the low-concentration region because the lattice defect concentration is higher than other portions. Life time is extremely short. Here, when the applied voltage is inverted, minority carriers that have entered the low-concentration region from the other conductivity type semiconductor region and have not yet disappeared transition across the pn junction again to return to the other conductivity type semiconductor region. Direction current flows. However, as described above, the minority carrier has a short lifetime in the first defect region and disappears immediately after the voltage reversal. Therefore, only the minority carrier remaining in the region other than the first defect region contributes to the reverse current thereafter. Becomes Furthermore, since the first defect region does not contribute to the disappearance of minority carriers after depletion, the time change rate of the reverse current in the latter half of the reverse recovery time does not increase.

Therefore, the rise of the reverse current is smaller than that of the semiconductor device having no first defect region,
For this reason, the reverse recovery time is shortened, the switching speed is increased, and the reverse recovery charge is also reduced, thereby reducing the energy loss. Also, since the peak of the reverse current is small and the time change rate of the reverse current in the latter half of the reverse recovery time is small, the element is not destroyed due to the superposition of the surge voltage.

As described above, in the semiconductor device according to the first aspect, by providing the first defect region in which the minority carrier has a short lifetime in the low concentration region, the minority carrier contributing to the reverse current in the first half of the reverse recovery time is reduced. It is intended to be extinguished early. Therefore, the effect is greater when the first defect region is provided as close to the pn junction as possible in the low concentration region. Note that the entire low-concentration region may be used as the first defect region. However, if a part of the low-concentration region is used as the first defect region, a layer having a low lattice defect concentration remains in the low-concentration region, so that leakage current can be suppressed. .

According to a second aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the other portion is located farther from the first defect region as viewed from a pn junction in the one conductivity type semiconductor region. This is characterized by providing a second defect region having a higher lattice defect concentration than the first defect region (excluding the first defect region).

In this semiconductor device, in the first half of the reverse recovery time, the reverse current is reduced by the action of the first defect region in the same manner as described above. Since the second defect region is provided in the region where the minority carriers contributing to the reverse current thereafter exist, the reverse current is reduced even in the latter half of the reverse recovery time, and the reverse recovery time is further increased as a whole. And the reverse recovery charge are reduced.

In the first and second aspects of the present invention,
One of the one conductivity type semiconductor region and the other conductivity type semiconductor region is an n-type semiconductor and the other is a p-type semiconductor (either one may be an n-type semiconductor). Therefore, the minority carriers that have entered the low concentration region are holes when the other conductivity type semiconductor region is a p-type semiconductor, and are electrons when the other conductivity type semiconductor region is an n-type semiconductor. Lattice defects are abnormalities such as dislocations, vacancies, and heteroatoms (excluding those acting as dopants) in the crystal lattice of a semiconductor, which have an effect of shortening the minority carrier lifetime. .

According to a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising a semiconductor region of one conductivity type and a semiconductor region of another conductivity type forming a pn junction. For a semiconductor having a structure in which a low-concentration region in which the impurity concentration is lower than the impurity concentration of the other conductivity type semiconductor region is formed at least in a portion adjacent to the pn junction, The ion irradiation is performed so that the ions are distributed in the low-concentration region, and a first defect region having a higher lattice defect concentration than other portions is formed in the low-concentration region.

This method of manufacturing a semiconductor device is a method of manufacturing the semiconductor device according to claim 1. In this manufacturing method,
One-conductivity-type semiconductor region and other-conductivity-type semiconductor region, and a low-concentration region for the semiconductor having the structure described above,
Ion irradiation is performed to form a first defect region in which lattice defects are distributed at a high concentration. This ion irradiation is performed by adjusting the range of the ions so that the irradiated ions that have entered the semiconductor are distributed in the low concentration region. This adjustment is performed by determining the acceleration voltage, ion type, and the like of the ions to be irradiated in consideration of the average range and the half width of the distribution. That is, when the acceleration voltage is high, the average range is large (deep) and the half width of the distribution is large (wide). On the other hand, when the acceleration voltage is low, the average range is small (shallow) and the half width of the distribution is small. It becomes smaller (narrower). In addition, as for the ion species, if the accelerating voltage is the same, generally, the half value width of the distribution becomes smaller (narrower) for the light element, and conversely, the half width of the distribution becomes larger (wider) for the heavy element. ) Tends to be.
If necessary, a mask is attached to the surface of the semiconductor so that the distribution range of the ions (the range of the half-value width) is located in the low concentration region. If a mask having the same stopping power as that of a semiconductor is used as a mask in this case, it is convenient for calculating the range.

When the ions are distributed in the low concentration region, the distribution region becomes the first defect region having a high lattice defect concentration. After the ions are distributed, it is preferable to perform a heat treatment such as annealing to stabilize lattice defects. Further, before or after the formation of the first defect region, a step of forming the second defect region according to claim 2 may be performed. The second defect region may be formed by performing ion irradiation under different conditions (such as ion species and acceleration voltage) as in the case of the first defect region. Alternatively, electron beam irradiation may be used instead of ion irradiation.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First Embodiment (Element Configuration) The semiconductor device according to the first embodiment has the basic structure shown in FIG. That is, in this semiconductor device, the p ⁺ anode region 13, the p ⁻ anode region 14, the n ⁻ region 16, and the n ⁺ cathode region 1
7 are formed in order. Here, a portion between the p ⁻ anode region 14 and the n ⁻ region 16 is a pn junction. Note that p ⁻ anode region 14 is formed much thinner than n ⁻ region 16. An anode electrode 11 and a cathode electrode 19 are provided at both ends with a metal such as Al.
The anode electrode 11 is ohmically connected to the p ⁺ anode region 13 and the cathode electrode 19 is ohmically connected to the n ⁺ cathode region 17.

The impurity concentration in each region is shown in FIG.
Has a profile (corresponding to the AA cross section in FIG. 1) as shown by curve a in the graph of FIG. That is, p
^The impurity concentration of the ⁻ anode region 14 is lower than that of the p ⁺ anode region 13 and the impurity concentration of the n ⁻ region 16 is lower than that of the n ⁺ cathode region 17. Further, the impurity concentration of the n ⁻ region 16 is lower than that of the p ⁻ anode region 14 with the pn junction interposed therebetween. Therefore, the carrier (hole) concentration in the p ⁻ anode region 14 is lower than that in the n ⁻ region 16. Higher than carrier (electron) concentration. Note that the curve a in FIG. 2 shows only the concentration and does not distinguish the types of impurities, but p ⁺
The impurities in the anode region 13 and the p ⁻ anode region 14 are acceptors such as B, Al, and Ga, while n ⁻
The impurities in region 16 and n ⁺ cathode region 17 are P, S
They differ in that they are donors such as b and As.

The semiconductor device has an n ⁻ region 16.
Are provided with a first defect region 16a. The first defect area 16a is formed as shown by a curve b in the graph of FIG.
This is one in which lattice defects are distributed at a high concentration at a position near the pn junction in the n ⁻ region 16. That is, the n ⁻ region 16 includes the first defect region 16a and the region 1 adjacent to the pn junction.
6b and a region 16c remote from the pn junction. Lattice defects are anomalies such as dislocations, vacancies, and heteroatoms in the crystal lattice of Si, and have the property of being a generation-recombination center between holes and electrons. Therefore, the first defect region 1
In 6a, the minority carrier (here, a hole) has a significantly shorter lifetime.

The first defect region 16a is formed by irradiating a Si crystal with He ions, as described later. Therefore, the distribution of the lattice defects is a Gaussian distribution like a curve b. In FIG. 1, the range where the distribution density is a half of the maximum value is called the first defect region 16a. Therefore,
Strictly speaking, lattice defects formed based on ion irradiation are slightly distributed outside the first defect region 16a, but p ⁻
In the anode region 14 and the p ⁺ anode region 13, the characteristics are not so affected.

In such an element structure, the n ⁻ region 16 and the n ⁺ cathode region 17 correspond to the “one conductivity type semiconductor region” of claim 1, and the n ⁻ region 16 corresponds to the “low concentration region”. . Further, the first defect region 1 therein
6a corresponds to a "first defect area". On the other hand, the p ⁻ anode region 14 corresponds to the “other conductivity type semiconductor region”.

(Operation) This semiconductor device operates as a switching diode. First, the ON state will be described. When a voltage is applied in a direction in which the anode electrode 11 is positive and the cathode electrode 19 is negative (forward direction), holes in the p ⁻ anode region 14 and the p ⁺ anode region 13 are accelerated toward the cathode electrode 19 by an electric field, Free electrons in n ⁻ region 16 and n ⁺ cathode region 17 are accelerated toward anode electrode 11. Therefore, current flows from the anode electrode 11 to the cathode electrode 19 through the semiconductor device. This state is the ON state.

In this ON state, holes and electrons accelerated by the electric field are converted into p ^- anode region 14 and n ^- region 1
6 and recombine at the pn junction, and disappear. However, since the number of holes is larger, excess holes
It enters the n ^- region 16 beyond the junction. The holes are minority carriers in the n ⁻ region 16 and recombine with electrons that are majority carriers, and disappear. However, it takes a certain time (lifetime) to actually disappear. Therefore, while the on-current is flowing, holes are accumulated in n ⁻ region 16.

The lifetime of a hole in n ⁻ region 16 is several hundred μs in a place other than first defect region 16a.
c, which is relatively long, but within the first defect region 16a, 10
Very short, about nsec. This is because lattice defects distributed at a high concentration in the first defect region 16a act as generation-recombination centers to promote the disappearance of holes.

Here, the applied voltage is inverted, and the anode electrode 1
When 1 is negative and the cathode electrode 19 is positive (reverse direction), the direction of the electric field inside the semiconductor device is also reversed, so that the holes accumulated in the n ⁻ region 16 are reversed in the anode electrode. It will be accelerated toward eleven. Therefore, while holes remain in n ⁻ region 16, a current in the opposite direction to the on-current (reverse current I _R ) flows through the semiconductor device, and the current disappears when holes in n ⁻ region 16 disappear. That is, the reverse current I _R is transient. This situation is shown in the graph of FIG. Hereinafter, in the history after the voltage inversion, the period from the voltage inversion until the magnitude of the reverse current I _R becomes maximum is referred to as “first half of off”, and the period after that, when the current value converges to 0, is referred to as “second half of off”. I do.

In this semiconductor device, the reverse current I
_R is caused by the contribution of holes accumulated in the region adjacent to the pn junction. The reverse current I _R rises while holes disappear in the first half of the off-time (downward in FIG. 3). The reverse current converges to 0 while the depletion layer expands in the latter half of the off-time. Gradient dI _R / d of the reverse current in the off-late
t is almost the same as in the case of the semiconductor device in which the first defect region 16a is not provided (broken line f in FIG. 3), and a high surge voltage that causes element destruction does not occur. Note that the reverse current I _R in the latter half of the off-time is due to the contribution of holes accumulated in a region away from the pn junction. Reverse current I
_{After R} converges to 0, the transistor is in an off state in which current is blocked by a depletion layer extending across the pn junction.

Thus, in this semiconductor device, n ^- region 1
The first defect region 16 is formed in the region depleted in the first half of the off-state in FIG.
It can be understood that by providing a, the peak of the reverse current I _R is reduced, and the reverse recovery time T _R is also reduced accordingly. Further, the reverse recovery charge Q _R is small correspondingly the reverse recovery time spans T _R time integral of the reverse current I _R.
Therefore, a semiconductor device in which switching from ON to OFF is performed at high speed and excellent in energy efficiency is realized. Then, the inclination dI _R / dt of the reverse current I _R is small, the surge voltage does not also increases.

Further, in the case where a region where lattice defects are distributed at a high concentration is provided, there is a concern that the ON voltage may increase.
Other than a, lattice defects are scarcely distributed, especially p ⁻
Since there is almost no distribution in the anode region 14 and the p ⁺ anode region 13, an increase in on-state voltage does not matter. In addition, since there is a region in the n ⁻ region 16 where lattice defects are not much distributed, the leakage current is small.

(Manufacturing Method) Next, a method of manufacturing the semiconductor device will be described. In manufacturing this semiconductor device, an n ⁻ substrate is used as a silicon substrate.

First, as shown in FIG. 4, a donor impurity element such as P, Sb or As is introduced into the n ^- silicon substrate 20 by thermal diffusion ((a) → (b)). As a result, n ⁺ cathode regions 17 and 17 are formed on both surfaces of the substrate, while n ⁻ region 16 remains therebetween. n ⁺ cathode region 1
7 and 17, the impurity (donor) concentration is n ⁻ region 16
Is higher. Then, one n ⁺ cathode region 17 is polished and removed, and the n ⁻ region 16 is exposed to the surface ((b) → (c)).

[0034] Then, as shown in FIG. 5, and polished n ^-
B (boron) or the like (A
(I, Ga, etc.) may be ion-implanted and diffused to form the p ⁻ anode region 14 ((a) → (b)). Then, ion implantation is repeated at a shallower implantation depth to form the p ⁺ anode region 13 ((b) → (c)).

Further, as shown in FIG. 6, an anode electrode 11 is formed of a metal such as Al on the p ⁺ anode region 13 and, in this state, an ion acceleration device such as a cyclotron is used to increase the acceleration energy of 24 MeV. The first defect region 16a is formed in the n ⁻ region 16 by radiating He ²⁺ ions from the substrate and annealing ((a) → (b)). This irradiation condition is such that the average range of the ions is located at the center of the range where the first defect region 16a should be, and the half value width of the distribution concentration is n ⁻
The ion species and the acceleration energy are set so as not to deviate from the region 16. Annealing after ion irradiation is a process for thermally stabilizing lattice defects generated by irradiation, and almost all He ²⁺ ions themselves escape from the Si crystal during this annealing. Thereafter, if the cathode electrode 19 is formed of a metal such as Al on the surface on the n ⁺ cathode region 17 side, the semiconductor device shown in FIG. 1 is completed ((b) → (c)).

In this manufacturing method, when forming the first defect region 16a in the n ⁻ region 16, a method is employed in which ions are distributed by ion irradiation to generate lattice defects in the Si crystal. Since the center of the distribution and the half width of the distribution concentration are adjusted by the ion species and the acceleration energy, and the thickness of the aluminum foil between the accelerator and the sample, the p ⁻ anode region 14 and the p ⁺ anode region 13 are adjusted. The first defect region 16a can be formed at a position as close to the pn junction as possible in the n ⁻ region 16 without substantially distributing lattice defects. For this reason, without increasing the on-voltage,
It is possible to manufacture a semiconductor device in which switching from on to off is fast and energy efficiency is excellent.

[Second Embodiment] (Element Configuration) A semiconductor device according to a second embodiment is provided within the cathode regions (16, 17) of the semiconductor device of the first embodiment shown in FIG. In addition to the first defect region 16a, a second defect region (indicated by g in FIG. 1) in which lattice defects are distributed is provided. The second defect area g is
It is provided at a position farther from the first defect region 16a when viewed from the position of the pn junction. As shown in FIG. 7, the distribution profile of the lattice defect in this semiconductor device includes a curve b corresponding to the first defect region 16a (same as the curve b in FIG. 2) and a curve c corresponding to the second defect region g. It has become. Note that the second defect area g corresponds to the “second defect area” in claim 2.

According to FIG. 7, the peak position of the curve c is n
⁺ Inside the cathode region 17. This is due to p
This is to locate the second defect region g at the farthest point where the depletion layer spreads from the n-junction. The peak height of the curve c is lower than the peak height of the curve b. This is to prevent too large an inclination dI _R / dt of the reverse recovery current. The half width of the curve c is larger than the half width of the curve b. This is to prevent the second defect region from being depleted in the middle of the latter half of the off-state, thereby preventing the reverse recovery time from becoming sufficiently short. However, the width of the half width is not absolute, and the first defect region 16a is viewed from the pn junction.
If it is farther away, a certain effect can be expected whether it is wide or narrow. In FIG. 7, a curve a is an impurity concentration profile, which is the same as the curve a in FIG.

(Operation) The operation of this semiconductor device is not significantly different from the operation of the semiconductor device of the first embodiment in the ON state, but not only in the first defect region 16a but also in the second defect region g. This also has the effect of shortening the lifetime of holes due to lattice defects.

Therefore, when the applied voltage is reversed from the forward direction to the reverse direction, the reverse current I _R transiently flows due to the holes accumulated in the n ⁻ region 16 and the n ⁺ cathode region 17, but the time characteristic is , As shown in FIG. That is, the rise of the reverse current I _R in the off half is the same as in the first embodiment, in the second half-off promptly reverse current I _R is zero than the case of the first embodiment Has converged. In the latter half of the off-time when the depletion layer spreads, holes accumulated in a region contributing to the reverse current I _R , that is, a region farther from the first defect region 16a as viewed from the pn junction, due to the presence of the second defect region g. Because it disappears quickly. For this reason,
As compared with the case of the first embodiment, the reverse recovery time T _R is shorter, reverse recovery charge Q _R is small.

Although the slope dI _R / dt of the reverse current in the latter half of the off-state is larger than that of the first embodiment, it is far greater than the slope of the curve c in FIG. It is so small that the destruction of blocking due to superimposition of surge voltage is not a problem.

Thus, in this semiconductor device, n ⁻ region 1
6, a first defect region 16a is provided at a position near the pn junction as in the first embodiment, and a second defect region g is located at a position farther from the first defect region 16a as viewed from the pn junction. the because as earlier disappears in the second half of the hole off provided not only the peak of reverse current I _R is small,
Convergence of the reverse current I _R in the second half off early. Therefore, to the extent that the surge voltage is not a problem, a further reduction of the reverse recovery time T _R and the reverse recovery charge Q _R is achieved by a semiconductor device capable of high-speed switching and high energy efficiency is achieved I have. By appropriately adjusting the defect concentration in the second defect region, the reverse recovery time and the time change rate of the reverse current can be adjusted appropriately.

(Manufacturing Method) The semiconductor device is provided with the first
The semiconductor device is manufactured by the manufacturing method in which the step of forming the second defect region g is added to the method of manufacturing the semiconductor device according to the embodiment. The formation of the second defect region g can be performed by ion irradiation similarly to the formation of the first defect region 16a. However, since the formation position, the width, and the distribution density are different from those of the first defect region 16a, the irradiation conditions are appropriately adjusted. (Ion species, acceleration energy, irradiation dose, etc.) are changed. Note that electron beam irradiation may be used instead of ion irradiation. Also, the first defect region 16a
May be carried out before or after the ion irradiation for the formation of.

As described in detail above, according to each of the above-described embodiments, a region in which lattice defects are distributed at a high density is formed in the cathode region, thereby contributing to the first half-off reverse current I _R. reduce the accumulation hole (first embodiment), since further was off late moderately to significantly reverse slope dI _R / dt of the (second embodiment), adverse effects of the surge voltage is not a problem within, also reduces the reverse recovery charge Q _R with shortening the reverse recovery time T _R, enable fast switching and high energy efficiency and a semiconductor device is realized with a manufacturing method thereof.

It should be noted that the present invention is not limited to the above embodiments, and various improvements and modifications can be made without departing from the spirit of the present invention. For example, in each of the above embodiments, the anode having a two-layer structure including the p ⁻ anode region 14 and the p ⁺ anode region 13 is adopted, but an anode having another structure may be used. As another structure, a divided structure described in Japanese Patent Application Laid-Open No. H6-140642 can be considered.

The impurity concentration of the p-type region (anode) and the n-type region (cathode) adjacent to each other across the pn junction can be reversed so that the cathode region has a higher concentration. However, in this case, the minority carriers accumulate in the ON state on the anode (p-type) side (therefore, the minority carriers are electrons).
The first and second defect regions are formed not in the cathode region but in the anode region.

[0047]

As is apparent from the above description, according to the present invention, since the reverse recovery time is shortened while the peak of the reverse recovery current is reduced, high-speed switching can be performed without fear of element destruction due to surge voltage. There has been provided a semiconductor device with a good trade-off between the recovery time and the surge voltage, together with a method for manufacturing the same.

[Brief description of the drawings]

FIG. 1 is a diagram showing a structure of a semiconductor device according to an embodiment.

FIG. 2 is a profile of an impurity concentration and a defect concentration in the semiconductor device according to the embodiment.

FIG. 3 is a graph showing current characteristics when the semiconductor device according to the embodiment is off;

FIG. 4 is a view (No. 1) illustrating the method for manufacturing the semiconductor device according to the embodiment.

FIG. 5 is a view (No. 2) illustrating the method for manufacturing the semiconductor device according to the embodiment.

FIG. 6 is a view (No. 3) illustrating the method for manufacturing the semiconductor device according to the embodiment.

FIG. 7 is a profile of an impurity concentration and a defect concentration in a semiconductor device according to a second embodiment.

FIG. 8 is a graph showing current characteristics when the semiconductor device according to the second embodiment is off.

FIG. 9 is a diagram showing a general structure of a conventional semiconductor device.

FIG. 10 is a profile of impurity concentration and defect concentration in a conventional semiconductor device.

FIG. 11 is a graph showing the off-state current characteristics of a conventional semiconductor device.

[Explanation of symbols]

13 p ^- anode region 16 n ^- region 16a first defect region g second defect region

Claims (3)

[Claims] 1. A semiconductor device comprising a semiconductor region of one conductivity type and a semiconductor region of another conductivity type forming a pn junction, wherein an impurity concentration of at least a portion adjacent to a pn junction portion in the semiconductor region of one conductivity type is different from that of the other conductivity type. A semiconductor device in which a low concentration region lower than the impurity concentration of the type semiconductor region is formed, wherein a first defect region having a higher lattice defect concentration than other portions is provided in the low concentration region. . 2. The semiconductor device according to claim 1, wherein another portion (excluding the first defect region) is located at a position farther than the first defect region as viewed from a pn junction in the one conductivity type semiconductor region. A second defect region having a higher lattice defect concentration than the second defect region. 3. The semiconductor device according to claim 1, further comprising a semiconductor region of one conductivity type and a semiconductor region of another conductivity type forming a pn junction. Irradiation is performed on a semiconductor having a structure in which a low concentration region lower than the impurity concentration of the type semiconductor region is formed so that ions are distributed in the low concentration region from a direction non-parallel to the pn junction surface. A first region having a higher lattice defect concentration than other portions in the low concentration region;
A method for manufacturing a semiconductor device, comprising forming a defect region.