JP5277882B2 - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-cost semiconductor device that has sufficiently high di/dt resistance to withstand a lightning surge and a low forward voltage VF, and to provide a method of manufacturing the same. <P>SOLUTION: On a first principal surface side (top side) of an n<SP>-</SP>semiconductor substrate 51, a p<SP>+</SP>anode region 52 and a plurality of p<SP>+</SP>guard ring regions 54 outside the p<SP>+</SP>anode region 52 are arranged, an n semiconductor region 53 having higher concentration than the n<SP>-</SP>semiconductor substrate 51 is arranged between the p<SP>+</SP>anode region 52 and p<SP>+</SP>guard rings 54, and an n semiconductor region 53 having higher concentration than the n<SP>-</SP>semiconductor substrate 51 is arranged between the p<SP>+</SP>guard ring regions 54. The n semiconductor region has an impurity concentration of 1&times;10<SP>15</SP>cm<SP>-3</SP>to 1&times;10<SP>17</SP>cm<SP>-3</SP>. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device mounted on a power module or the like and a manufacturing method thereof, and more particularly to a semiconductor device having a high tolerance against a lightning surge applied to a power module and a manufacturing method thereof.

  FIG. 10 is a diagram illustrating an example of a power module. As shown in FIG. 10, this power module includes a converter unit 1, a brake unit 2, an inverter unit 3, and a thermistor 4. Usually, the converter diode 5 of the converter unit 1 is constituted by a PIN diode. For example, when the module rating is 1200 V or 600 V, a PIN diode having a withstand voltage of 1600 V or higher or 800 V or higher is used as the converter diode 5, respectively.

  The reason why the breakdown voltage exceeding the rating is required in this way is to prevent the breakdown of the PIN diode in such a case where the module may have a breakdown voltage exceeding the rating. Further, the PIN diode used as the converter diode 5 is required to have a low forward voltage VF. For example, in the converter diode 5 whose module rating is 1200V, the required value of the forward voltage VF is about 1.2 to 1.5V.

FIG. 11 is a cross-sectional view showing a configuration of a conventional planar PIN diode. As shown in FIG. 11, a p ⁺ anode region 13 is arranged on the first main surface side (front side) of the n ⁻ semiconductor substrate 12, and a plurality of p ⁺ guard ring regions 14 and 15 are arranged outside the p ⁺ anode region 13. To do. An insulating film 16 such as an oxide film is disposed on the end of the p ⁺ anode region 13, on the n ⁻ semiconductor substrate 12 and on the p ⁺ guard rings 14 and 15, and an anode electrode 17 is disposed on the p ⁺ anode region 13.

On the other hand, the n ⁺ cathode region 11 is arranged on the second main surface side (back side) of the n ⁻ semiconductor substrate 12, and the cathode electrode 18 is arranged on the n ⁺ cathode region 11.
In the present specification and the accompanying drawings, a layer or region with n or p is a sign that electrons or holes are carriers. Moreover, ⁺ or ⁻ attached to n or p represents a relatively high impurity concentration or a relatively low impurity concentration, respectively.

The dimensions and the like of each part of the conventional converter diode 5 are as follows. When the module rating is 1200 V and the withstand voltage is 1600 V, the thickness of the n ⁻ semiconductor substrate 12 made of an FZ wafer having a specific resistance of about 120 Ωcm is about 300 μm. The depth of the p ⁺ anode region 13 is 6 to 8 μm, and the dose is 1 × 10 ¹⁵ cm ⁻² .
When the module rating is 600V and the withstand voltage is 800V, the thickness of the n ⁻ semiconductor substrate 12 made of a diffusion wafer having a specific resistance of about 40 Ωcm is about 80 μm. The p ⁺ anode region 13 is the same as the module rating of 1200V.

In the power module described above, when a lightning surge or the like occurs during converter operation, a surge with a high reverse recovery current attenuation factor (hereinafter referred to as di / dt) is applied to the converter unit 1. Therefore, the converter diode 5 enters a severe reverse recovery operation mode and cannot withstand high di / dt, and may be destroyed as shown in FIG.
FIG. 12 is a waveform diagram when a high di / dt surge enters the conventional converter unit 1 and the converter diode 5 is destroyed. In FIG. 12, for a current, one scale is 100 A, for a voltage, one scale is 200 V, and for a time, one scale is 1 μsec.

In order to prevent such a problem from occurring, in recent years, it is required that the converter unit 1 mounted on the power module can withstand a high di / dt surge such as a lightning surge. Hereinafter, in this specification, the tolerance against di / dt is expressed as di / dt tolerance.
By the way, when the current is excessively concentrated on the outer peripheral portion of the chip during the reverse recovery operation mode of the diode and the heat is generated, the diode is destroyed. In order to avoid this, it has been proposed to improve the reverse recovery resistance by forming a region having a short lifetime only at the electrode end of the diode by irradiation with He ions (see, for example, Patent Document 1).

The technology described in the above patent document relates to soft recovery characteristics during reverse recovery when operating as a semiconductor device, and prevention of breakdown during reverse recovery due to soft recovery. In normal recovery characteristics, di / dt is about 500 to 1000 A / μsec.

  In contrast, the lightning surge di / dt expected to enter the converter section is about 3500 A / μsec. Therefore, the di / dt tolerance obtained by the technique described in the above-mentioned patent document is insufficient for high di / dt such as lightning surge. As a result of experiments by the present inventors, it has been found that the technique described in the above-mentioned patent document cannot obtain a high di / dt resistance effective against lightning surges.

  For example, by introducing a lifetime killer over the entire surface of the diode and reducing the lifetime over the entire surface of the chip, it has been found that the di / dt resistance is improved to some extent. For this purpose, the forward voltage VF is greatly increased. Need to be increased. However, as described above, since the forward voltage VF must be lowered in the converter diode, it is not preferable to increase the forward voltage VF.

  In addition, the di / dt resistance can be improved to some extent by locally reducing the lifetime at the outer periphery and end of the chip, but a sufficiently high di / dt resistance to withstand lightning surge is obtained. It is not possible. Also, in this case, it is necessary to form a thick shielding film on the part that is not introduced in order to introduce a lifetime killer locally, or to remove the shielding film, which complicates the manufacturing process and increases the chip cost. There is an inconvenience.

Further, even if a region having a short lifetime is locally formed in the depth direction using He ions, protons, or the like on the chip surface or in the vicinity thereof, sufficient di / dt resistance cannot be obtained. Moreover, when diffusing heavy metals as a lifetime killer, it is difficult to control the diffusion depth.
Therefore, as disclosed in Patent Document 2, p ⁺ diffusion regions 23, 24, 25 (23) having a depth of 14 to 20 μm (design value) are formed on the surface of the n ⁻ semiconductor layer 22 (n ⁻ semiconductor substrate). P ⁺ anode region, and 24 and 25 are p ⁺ guard ring region). The entire surface of the chip is irradiated with He ions, and a lifetime killer is introduced from a position d2 shallower than the position d1 of the pn junction surface 31 composed of the n ⁻ semiconductor layer 22 and the p ⁺ diffusion region 23 to a position d3 deeper than the entire chip. The low lifetime region 32 is formed. At the time of He ion irradiation, the depth of the p ⁺ diffusion region 23 is equal to or greater than the half width of the He ion irradiation, the He ion peak position is deeper than the He ion irradiation half width, and the depth of the p ⁺ diffusion region 23 is the same. The range is 80 to 120%. The names and symbols described in Patent Document 2 are used as they are.

By doing so, it is possible to obtain a semiconductor device having a sufficiently high di / dt resistance to withstand lightning surge and a low forward voltage VF.
Further, Patent Document 3 discloses the receding length L of the anode electrode in a region where the p ⁺ conductive type semiconductor layer 11 and the anode electrode 16 are not in contact with each other, and the diffusion length of holes in the n ⁻ conductive type semiconductor layer 14. Longer than. As a result, since the carrier concentration in the termination region is reduced, it is disclosed that local current concentration does not occur at the end of the p ⁺ conductivity type semiconductor layer 11 during recovery. The names and symbols described in Patent Document 3 are used as they are.
JP 2001-135831 A JP 2005-340528 A Japanese Patent No. 3444081

However, when He ions are irradiated as shown in Patent Document 2, the irradiation cost is high and the yield rate is deteriorated, resulting in an increase in cost.
Further, as shown in Patent Document 3, the active area must be increased, and the chip area is increased and the cost is increased due to the increase in the active area.
An object of the present invention is to provide a low-cost semiconductor device having a sufficiently high di / dt resistance enough to withstand lightning surge and a low forward voltage VF, and a method for manufacturing the same, by solving the above-described problems. is there.

To achieve the above object, a first conductivity type semiconductor layer (corresponding to a semiconductor substrate) and a second conductivity type first semiconductor region (anode) selectively disposed on the first main surface of the semiconductor layer. A second semiconductor region (corresponding to an n semiconductor region) disposed on the outside of the first semiconductor region in contact with the first semiconductor region, and on the second semiconductor region And an insulating film disposed on an end of the first semiconductor region, a first main electrode (corresponding to an anode electrode) disposed in contact with the insulating film and the first semiconductor region, and the semiconductor layer A first conductive type third semiconductor region (corresponding to the cathode region) disposed on the second main surface, and a second main electrode (corresponding to the cathode electrode) disposed in contact with the third semiconductor region; In a semiconductor device having
The impurity concentration of the second semiconductor region and the third semiconductor region is higher than the impurity concentration of the semiconductor layer, and the impurity concentration of the second semiconductor region is 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . range near is,
The length of the insulating film toward the said first semiconductor region from the end portion of the first semiconductor region and constituting you longer than the diffusion length of holes in the first semiconductor region.

The depth of the second semiconductor region may be less than or equal to the depth of the first semiconductor region.
A second conductivity type guard ring region may be disposed in the second semiconductor region.
A lifetime killer may be introduced into at least the second semiconductor region by electron beam irradiation or heavy metal diffusion .

Forming a first conductive type second semiconductor layer having an impurity concentration higher than an impurity concentration of the first semiconductor layer on a first main surface of the first conductive type first semiconductor layer (corresponding to a semiconductor substrate); And a second conductive type first semiconductor region (anode region) penetrating the second semiconductor layer and reaching the first semiconductor layer is selectively formed, and the second semiconductor region remaining outside the first semiconductor region is formed. Forming a semiconductor layer as a second semiconductor region (corresponding to an n semiconductor region), forming an insulating film on the second semiconductor region and on an end of the first semiconductor region, and the first semiconductor layer Forming a first conductive type third semiconductor region on the second main surface, forming a first main electrode in contact with the insulating film and the first semiconductor region, and in contact with the third semiconductor region In a method for manufacturing a semiconductor device comprising a step of forming a two main electrode, The impurity concentration of the second semiconductor region, and a manufacturing method in the range of ^{1 × 10 15 cm -3 ~1 ×} 10 17 cm -3.

According to the present invention, p n ⁺ contact with the anode region and the lateral ^- that impurity concentration than the semiconductor substrate is provided with high n semiconductor regions to suppress the amount of holes injected from the p ⁺ anode region into the n semiconductor region . By suppressing the amount of holes, the amount of accumulated holes in the n semiconductor region can be suppressed, and the reverse recovery resistance (di / dt resistance) can be improved while suppressing the forward voltage VF to a low level.

Furthermore, the introduction of a lifetime killer by electron beam irradiation or heavy metal diffusion can further improve the di / dt resistance with a low forward voltage VF.
Further, an insulating film covering the p ⁺ anode region above longer than the hole diffusion length, by stretching the inside of the p ⁺ anode region, the injection of holes in the curvature portion of the p ⁺ anode region is suppressed The di / dt resistance can be further improved.

  Further, in the present invention, by providing the n semiconductor region, it is not necessary to introduce expensive He ions, and the chip size can be reduced by suppressing the extension of the depletion layer, thereby reducing the cost. it can.

  Embodiments of the invention will be described in the following examples.

FIG. 1 is a cross-sectional view of a main part of a semiconductor device according to a first embodiment of the present invention. In FIG. 1, a p ⁺ anode region 52 is disposed on the first main surface side (front side) of an n ⁻ semiconductor substrate 51, and a plurality of p ⁺ guard ring regions 54 are disposed outside the p ⁺ anode region 52. n between p ⁺ anode region 52 and ^{p +} guard ring region 54 ^- a high concentration of n semiconductor region 53 is disposed from the semiconductor substrate 51, also between ^{p +} guard ring region 54 n ^- a semiconductor substrate 51 high concentration An n semiconductor region 53 is arranged. An insulating film 55 such as an oxide film is disposed on the end of the p ⁺ anode region 52, the n semiconductor region 53, and the p ⁺ guard ring region 54, and the anode electrode 56 is disposed on the p ⁺ anode region 52.

On the other hand, an n ⁺ cathode region 57 is disposed on the second main surface side (back side) of the n ⁻ semiconductor substrate 51, and a cathode electrode 58 is disposed on the n ⁺ cathode region 57.
The portion where the p ⁺ anode region 52 is projected from the first main surface to the second main surface is the active region 59 of the PIN diode, and the outside of the p ⁺ anode region 52 is the p ⁺ guard ring region 54 and the n semiconductor. This is a breakdown voltage structure region 60 constituted by the region 53.

As described above, when the impurity concentration of the n semiconductor region 53 is increased, the hole injection efficiency in the curvature portion of the p ⁺ anode region 52 is suppressed. Further, as shown in FIG. 2, when the impurity concentration of the n semiconductor region 53 is increased, the lifetime in this portion is lowered. By suppressing the injection efficiency and reducing the lifetime, the amount of holes accumulated in the n semiconductor region 53 at the curvature portion is reduced. This decrease in the amount of holes increases the di / dt resistance. As a result, the lightning surge resistance is improved. On the other hand, since the injection of holes from the p ⁺ anode region 52 in the active region 59 is not suppressed, the forward voltage VF does not increase and can be used as a diode for a converter.

FIG. 2 is a graph showing the relationship between the impurity concentration and the lifetime of holes.
Furthermore, it demonstrates concretely.
When the depth from the surface of the p ⁺ anode region 52 (diffusion depth) is A and the depth from the surface of the n semiconductor region 53 (diffusion depth) is B, B ≦ A (in FIG. 1) B = A). Here, the depth from the surface means the depth of the deepest part. This is because, if the B> A, n semiconductor region 53 surpasses ^{p +} anode region 52, n of a flat portion of the bottom of the ^{p +} anode region 52 ^- semiconductor substrate 51 and the ^{p +} anode region 52 intersects The impurity concentration in the vicinity of the pn junction increases, leading to a decrease in breakdown voltage and an increase in leakage current due to a decrease in lifetime. Incidentally, A is a withstand voltage of 600V to 1600V class and is in the range of about 2 μm to 22 μm.

When the impurity concentration of the n ⁻ semiconductor substrate 51 is N1 and the impurity concentration of the n semiconductor region 53 is N2, N1 <N2 and 1 × 10 ¹⁵ cm ⁻³ ≦ N2 ≦ 1 × 10 ¹⁷ cm ⁻³ . (See FIG. 2). When N2 is less than 10 ¹⁵ cm ⁻³ , the lifetime has almost no dependency on the impurity concentration. On the other hand, when N2 exceeds 10 ¹⁷ cm ⁻³ , the elongation at the surface of the depletion layer is hindered, resulting in a decrease in breakdown voltage. N1 is a diode for a converter, for example, with a withstand voltage of 800V, about 1 × 10 ¹⁴ cm ⁻³ , and 1600V, about 3 × 10 ¹³ cm ⁻³ .

Further, the depth A from the surface of the p ⁺ anode region 52 and the depth C from the surface of the p ⁺ guard ring region 54 are the same (C = A). This is because the p ⁺ anode region 52 and the p ⁺ guard ring region 54 are formed simultaneously in order to reduce the cost. However, in order to ensure a breakdown voltage, C> A may be set.
When the impurity concentration N2 of the n semiconductor region 53 is changed, an optimum design such as the impurity concentration and diffusion depth of the p ⁺ guard ring region 54 corresponding to the impurity concentration N2 is required. Further, the present invention can be applied even when the breakdown voltage structure is a field plate type.

3 to 6 are cross-sectional views of the main part manufacturing process showing the manufacturing method of the semiconductor device of FIG.
In FIG. 3, an n semiconductor layer 53 a to be an n semiconductor region 53 is formed on the entire surface of the first main surface side (front side) of the n ⁻ semiconductor substrate 51. The n semiconductor layer 53a is, n ^- is formed by diffusing an impurity such as phosphorus on the surface of the semiconductor substrate 51 (or, n ^- formed by epitaxially growing an n impurity layer on the semiconductor substrate 51). The n ⁻ semiconductor substrate 51 is, for example, an FZ wafer. The n semiconductor layer 53a may be formed by diffusing impurities after forming the p ⁺ anode region 52 and the p ⁺ guard ring region 54.

In FIG. 4, a p ⁺ anode region 52 reaching the n ⁻ semiconductor substrate 51 from the surface of the n semiconductor layer 53a is selectively formed by diffusion (combination of ion implantation and heat treatment). At this time, a plurality of p ⁺ guard ring regions 54 surrounding the p ⁺ anode region 52 are formed apart from the p ⁺ anode region 52 simultaneously with the formation of the p ⁺ anode region 52. The diffusion depth of the p ⁺ anode region 52 and the p ⁺ guard ring region 54 is about 2 μm to 22 μm. The n semiconductor layer 53 a remaining outside the p ⁺ anode region 52 becomes the n semiconductor region 53.

In FIG. 5, an n ⁺ cathode region 57 is formed on the second main surface side (back side) of the n ⁻ semiconductor substrate 51.
In FIG. 6, an insulating film 55 such as an oxide film is formed on the end of the p ⁺ anode region 52, on the n semiconductor region 53 and on the p ⁺ guard ring region 54. In some cases, after the p ⁺ anode region 52 is formed, the p ⁺ guard ring region 54 is formed deeper than the diffusion depth of the p ⁺ anode region 52. In this case, two diffusions are required.

Subsequently, an anode electrode 56 and a cathode electrode 58 are formed on the p ⁺ anode region 52 and the n ⁺ cathode region 57.

  FIG. 7 is a fragmentary cross-sectional view of a semiconductor device according to a second embodiment of the present invention. The difference from FIG. 1 is that the lifetime of the n semiconductor region 53 is further shortened by introducing a lifetime killer by irradiating the entire surface with an electron beam. By further shortening the lifetime of the n semiconductor region 53, the amount of accumulated holes is reduced and the di / dt resistance is further increased. However, if the entire surface is irradiated with an electron beam, the lifetime of the active region 59 is shortened, leading to an increase in the forward voltage VF. Therefore, in converter applications, it is necessary to control the electron beam dose to suppress the increase of the forward voltage VF as much as possible.

FIG. 8 is a diagram showing the relationship between the di / dt tolerance and the forward voltage VF when the electron beam irradiation amount is controlled. In the forward voltage VF in the figure, the low level on the left side is a case where electron beam irradiation is not performed, and the middle middle level and the high level on the right side are cases where electron beam irradiation is performed. The di / dt tolerance can be improved by increasing the electron dose and introducing a lifetime killer.
In addition, since the crystal defect becomes a donor at the electron beam irradiated portion, the impurity concentration of the n semiconductor region 53 is increased, and there is an effect of suppressing injection of holes from the p ⁺ anode region 52.

On the other hand, by performing electron beam irradiation on the end of the p ⁺ anode region 52 and the breakdown voltage structure region 60 in contact therewith, the di / dt resistance can be increased without increasing the forward voltage VF as described above. This is the same even if it is performed near the pn junction between the p ⁺ anode region 52 and the n semiconductor region 53.
Moreover, the same effect can be expected even when a heavy metal such as gold or platinum is introduced instead of electron beam irradiation to reduce the lifetime.

FIG. 9 is a fragmentary cross-sectional view of a semiconductor device according to a third embodiment of the present invention. The difference between FIG 1 is that coated by stretching the p ⁺ p ⁺ anode region 52 extending the length W than the diffusion length of holes in the insulating film 55 on the end of the anode region 52. By doing so, in addition to the effect of suppressing the injection of holes by the n semiconductor region 53 described above, the injection of holes at the curvature portion of the p ⁺ anode region 52 due to the stretching of the insulating film 55 is further suppressed, and di / The dt resistance is further improved. Further, by providing the n semiconductor region 53, the extension of the depletion layer on the surface is reduced, the area occupied by the breakdown voltage structure region 60 is reduced, the chip size can be reduced, and the cost can be reduced. .

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for a semiconductor device mounted on a power module or the like, and are particularly suitable for a PIN diode used for a converter. Of course, the present invention can also be applied to free wheeling diodes used in inverters.

Sectional drawing of the principal part of the semiconductor device of 1st Example of this invention. Diagram showing the relationship between impurity concentration and lifetime FIG. 1 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 3 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 4 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. FIG. 5 is a cross-sectional view of the main part manufacturing process of the semiconductor device of FIG. Sectional drawing of the principal part of the semiconductor device of 2nd Example of this invention The figure which shows the relationship between di / dt tolerance and the forward voltage VF at the time of controlling electron beam irradiation amount Sectional drawing of the principal part of the semiconductor device of 3rd Example of this invention. Circuit diagram showing an example of an automotive power module Sectional drawing which shows the structure of the conventional planar type PIN diode Waveform diagram showing the waveform when a surge enters the conventional converter

Explanation of symbols

51 n ^- semiconductor substrate 52 p ⁺ anode region 53 n semiconductor region 53a n semiconductor layer 54 p ⁺ guard ring region 55 insulating film 56 anode electrode 57 n ⁺ cathode region 58 cathode electrode 59 active region 60 breakdown withstanding region 61 electron beam irradiation region

Claims (5)

A first conductivity type semiconductor layer, a second conductivity type first semiconductor region selectively disposed on the first main surface of the semiconductor layer, and in contact with the first semiconductor region, outside the first semiconductor region; A second semiconductor region of a first conductivity type disposed; an insulating film disposed on the second semiconductor region and an end of the first semiconductor region; and in contact with the insulating film and the first semiconductor region A first main electrode disposed; a third semiconductor region of a first conductivity type disposed on a second main surface of the semiconductor layer; and a second main electrode disposed in contact with the third semiconductor region. In semiconductor devices,
The impurity concentration of the second semiconductor region and the third semiconductor region is higher than the impurity concentration of the semiconductor layer, and the impurity concentration of the second semiconductor region is 1 × 10 ¹⁵ cm ⁻³ to 1 × 10 ¹⁷ cm ⁻³ . range near is,
Wherein a said longer be Rukoto than the diffusion length of holes in the length of the insulating film said first semiconductor region of toward on said first semiconductor region from the end portion of the first semiconductor region.   The semiconductor device according to claim 1, wherein a depth of the second semiconductor region is equal to or less than a depth of the first semiconductor region. The semiconductor device according to claim 1, wherein a second conductivity type guard ring region is disposed in the second semiconductor region.   The semiconductor device according to claim 1, wherein a lifetime killer is introduced into at least the second semiconductor region by electron beam irradiation or heavy metal diffusion. Forming a first conductivity type second semiconductor layer having an impurity concentration higher than the impurity concentration of the first semiconductor layer on the first main surface of the first conductivity type first semiconductor layer;
A second semiconductor layer of a second conductivity type that penetrates through the second semiconductor layer and reaches the first semiconductor layer is selectively formed, and the second semiconductor layer remaining outside the first semiconductor region is formed as a second semiconductor. A process of making an area;
Forming an insulating film on the second semiconductor region and on an end of the first semiconductor region;
Forming a first conductive type third semiconductor region on the second main surface of the first semiconductor layer; forming a first main electrode in contact with the insulating film and the first semiconductor region;
Forming a second main electrode in contact with the third semiconductor region;
In the manufacturing method of the semiconductor device having
The impurity concentration of the second semiconductor region is 1 × 10 ¹⁵ cm ^-3 ~ 1x10 ¹⁷ cm ^-3 A method for manufacturing a semiconductor device, characterized in that: