JPS58153375A - Semiconductor element and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain the short gate length of a semiconductor element by a method wherein a resist pattern having an opening on a semiconductor element region is provided, evaporation is performed obliquely from the mutually reverse directions to adhere a Ti layer on the surface of the pattern and the opening inside wall face protruding the lower edge, and the gate electrode having the sectional area regulated in the reversely convex type according to the protruded part is formed on the bottom of the opening. CONSTITUTION:An n type layer 22 is formecd in the surface layer of a semiinsulating GaAs substrate 21, a resist pattern 23 having a window at the part corresponding to the position of a gate is provided, and a Ti layer 24 is adhered on the surface of the pattern 23 and on the inside wall on one side of the window according to evaporation diagonally from the upper part at first. At this time, the evaporating angle is specified to make the protruding part to be generated in parallel with the bottom at the lower edge part of the layer 24 adhered on the inside wall part of the window, then the evaporating angle is turned to the reverse direction, the Ti layer 25 is adhered on the layer 24 the same, and the layer 25 having the protruded part also at the facing position with the inside wall part of the window. Accordingly the window whose sectional area is reduced according to the protruded parts is made to be generated on the bottom of the window, a Pt layer 26 is evaporated on the whole surface, and the gate electrode 27 having the reversely convex type sectional shape is formed in the window.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed semiconductor device having a short gate length and a method for manufacturing the same.

Figure 1 is a process explanatory diagram of the conventional ME8FET manufacturing method. First, as shown in Figure 1, a semi-insulating substrate l
An n-type conductive layer 12't- is formed on the substrate 12' by ion implantation.

Next, a resist mask is formed by photolithography, and the semiconductor substrate (semi-insulating base tIj11 and n-type conductive layer 1
Source/drain regions 13, 14Th shown in FIG. 1(5) are formed in this semiconductor substrate by performing high concentration ion implantation into the semiconductor substrate (consisting of 2) and further annealing.

Next, a resist pattern is formed by photolithography,
After evaporating an ohmic metal and lifting off all unnecessary parts, the source and drain electrodes 15 and 16 are formed in the source and drain regions 13.
Finally, a resist pattern is similarly formed by photolithography, dirt metal is evaporated, and unnecessary parts are lifted off to form a dirt electrode 17t on the semiconductor substrate, as shown in FIG. 1G). Form in place.

By the way, in ME8FET, the smaller the distance between source and dirt or dirt and 19247.

Furthermore, the smaller the gate length, the greater the high frequency characteristics.

However, as described above, in the conventional manufacturing method using photolithographic mask alignment, there is a limit to the reduction of the distance between the source and the dirt or between the dirt and the drain due to limitations in mask alignment accuracy and resistor pattern width.

In addition, in the above method, mask alignment f:
It was necessary to conduct the process twice, and if the dirt electrode 17 came into contact with the source/drain regions 13 and 14 due to mask displacement or the like, the gate breakdown voltage deteriorated, resulting in poor yield.

Similarly, there is a limit to reducing the gate length due to the resist pattern width limit, and l! Furthermore, if the r-) length is small, parasitic resistance due to the dart electrode increases, which has the disadvantage of limiting high frequency characteristics.

The present invention was made in order to eliminate the above-mentioned conventional drawbacks, and its entire purpose is to provide a semiconductor device and a method for manufacturing the same that can manufacture M E 8 FETs with improved high frequency characteristics with high yield.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of a semiconductor device and a method for manufacturing the same according to the present invention will be described below with reference to the drawings. First, Figure 2 (5)
21 is a semi-insulating GaAs substrate, and an n-type conductor *# 22' is formed on the surface of the semi-insulating GaAs substrate 21 by selective ion implantation and annealing.

Next, as shown in Figure 2 (b), by photolithography,
A resist arm turn 23t- having a window at the r-t position on this n-type conductive layer 22 is formed. Next, from the direction indicated by arrow A diagonally upward, titanium 24 is 0.1 to 0.3
Wearing about 3fi. There is no problem even if this titanium is replaced with an insulator such as silicon oxide. At this time, the angle is such that a part of the titanium 24 comes into contact with the semi-insulating GaAm substrate 21.

Next, as shown in FIG. 2, 10, titanium 25 is further steamed from the other diagonally upward direction (the direction opposite to the direction of the arrow in FIG. 2). At this time too.

If the angle is such that a part of the titanium 25 comes into contact with the semi-insulating GaAs substrate 21, a dart window surrounded by the titanium 25 can be formed in the center of the resist pattern 23. Subsequently, an eye 4226 serving as a vertically upper tH'-to electrode is deposited.

Here, lift-off is performed using the resist pattern 23 to further remove the remaining titanium.

f-) Electrode 27 with an inverted convex cross-sectional structure as shown in FIG.
You can form an association.

Finally, a system tonerization is performed to remove the source/drain electrodes 2 by lift-off of an organic metal such as Au-Ge.
8.29 and has the structure shown in Figure 2 ■
B2 FF1T *Can be manufactured.

In addition, after forming the 2-diagram 00 reverse convex dirt electrode, a resist layer having holes in the region including the source, dirt, and drain is formed, and the impurity is removed by using the resist I lean and the reverse convex dirt electrode as a mask. When high-concentration ion implantation is performed, the resist pattern is removed, and annealing is performed, source/drain regions 3O are formed in the semi-insulating G-mounted substrate 21.

31 can be formed.

After this, when the ohmic electrode is completely lifted off, #I2
11 [F] As shown, the source of 1liili mystery
ME8FET t-can be manufactured with a drain region.

As explained above, in the example of Yuki 1, Figure 2 (
c) As shown in Fig. 2), by utilizing the directionality of the vapor deposition of titanium 24 and 25, a smaller dart window is formed inside the resist nolene 23, as shown in Fig. 20. A reverse convex dart electrode can be obtained.

This allows the gate length to be controlled not only by the window size of the resist turn 2''1, but also by the titanium 24.25 (D deposition angle and thickness), resulting in a very short y-
The r-t electrode 27t having a length of t can be formed with high precision and a good yield.

In addition, since the dirt electrode structure has an inverted convex shape, the dirt electrode has a large cross-sectional area despite the short gate length, so there is an advantage that the parasitic dirt resistance caused by the dart electrode 27 can be completely reduced.

Furthermore, since the dart electrode is made of a single metal, there is no risk of dirt deterioration due to mutual diffusion of different metals, unlike dart electrodes that have multiple types of metals.
−) The reliability of the electrode is improved.

As described above, an MB8FET with high reliability and excellent high frequency characteristics can be manufactured at a high yield by using a monometallic inverted convex dart electrode and its manufacturing method using oblique evaporation.

In addition, in the case of an inversely convex dart electrode, the sides of the dart electrode overhang, so even if high-precision ion implantation is performed using the f-) electrode as a mask, the implanted region will not come into contact with the dart electrode. First, there is no risk of deterioration of dirt breakdown voltage due to contact between the dirt electrode and the highly concentrated W surface source/drain region.

The protruding distance i of the overhang is very small (1000~zooo, i, so (7) distance M [Yo, the distance between the source and the dirt, and the distance between the gate and the drain is determined, so the distance between the source and the dirt is determined. The total resistance between dirt and drain can be made very small.

In this way, by adding the ion implantation method, the high frequency characteristics of the FET can be further improved.

In the first embodiment, a semiconductor element having an inverted convex dart electrode 27 made of a single metal and a method for manufacturing the same have been described.
A method of forming the drain electrode using self-alignment will be explained with reference to FIG.

First, in the first embodiment, as shown in FIG. 2, 24.25t of titanium is deposited diagonally upward in the opposite direction, and 26t of platinum is deposited from vertically upward, and then lifted off by the resist I# turn 23. After performing the third
As shown in the figure, a resist mother turn 32t having a hole sized to include the source and drain regions is formed by photolithography.

Next, an ohmic metal 33t is deposited and lift-off is performed using a resist pattern 32 (FIG. 3(c)).

Finally, the chip 17 remaining on the semi-insulating GaA@substrate 21
When 25' is removed, the ohmic metal 33 deposited on the titanium 25 is also lifted off, and the ME8FET with the source/P-rain electrodes 28, 29 and the dirt electrode 34 is
T-Can be manufactured.

In this way, the source/drain poles 28, 29 are formed at predetermined positions in the self-line by the non-overview resist/turn 32, and at the same time, the r-) electrodes 3
4 and the source/drain electrode 28.29 distance S is titanium 2
Since the thickness is determined to be 4.25 mm, the distance between the r-meter electrode 34 and the source/drain electrodes 28 and 29 can be made very small.

This makes it possible to reduce the resistance between the source and r-) and between the dirt and drain, and by making the entire FET smaller, Mg8F has excellent cylindrical frequency characteristics.
ET can be manufactured with good yield.

Here, in the second embodiment, the source/drain electrode 28
．． 29, I explained how to form it with Selfa Line,
r-) Since the top surface of the electrode 34 is coated with a separate metal (ohmic gold &33), the gate electrode 34 is altered due to mutual diffusion between the ohmic metal 33 and the dart electrode 34, and the dart electrode 34 is There is a risk of deterioration.

In order to avoid this, a third embodiment will be explained next with reference to FIG. First, following the step shown in FIG. 2 of the first embodiment, 35 t of titanium is vapor-deposited from vertically above.

next,#! Fruit of 2! 3rd Blood Prisoner shown in 911, Figure 3 0
If you follow the process shown in ! As shown in FIG. 4 (6), the top surface of the platinum 26 serving as the dirt metal and the oak gold maple 33 are separated by the titanium 35.

Finally, when all the titanium 24,25'i remaining on the semi-insulating GaAs substrate 21 is removed, the metal 33 on the platinum 26 that will become the r-) electrode is also lifted on by the titanium 35, As shown in the gate vI
An r-t IIL pole 36 can be formed that is comprised of a single metal (platinum 26) with no dissimilar metals on top of the t-pole 36 (platinum 26).

In this way, in the third embodiment, in addition to the advantages of the second embodiment, the e-) electrode 36 is made of a single metal, improving dart reliability.

Here, the second. After the step shown in FIG. 3(A) of the third embodiment, a resist pattern 32, titanium 24°25 and e-) semi-insulating GaAs substrate 21 is used as a metal t mask.
ion implantation of impurities into the resist) a4 fi-
After lift-off by turn 32, annealing is performed, followed by resist 9 turn 321! as shown in the third factor again. 5, low resistance source/drain regions 37.381- are formed in the semi-insulating GaAa substrate 21 in contact with the source/drain electrodes 28.29. Can be formed.

At this time, if the ion implantation energy is increased to form deep source/drain regions, the lateral spread of the implanted impurities will cause the source/drain regions 37.381-ff to become deeper. The electrode 36 can be accessed.

For this reason, since a high concentration layer exists under the source and drain electrodes 37 and 38, each electrode is connected to the semi-insulating GaAs substrate 21.
Similarly, due to the high concentration layer existing near the dirt, the resistance between the source and drain can be reduced. In this way, by adding ion implantation, parasitic resistance can be reduced and high frequency characteristics can be increased. After depositing a first gold or insulating material diagonally in both directions of the first resist pattern having a window at the P-) position, a second metal for an electrode is deposited on the window at the T-gate position. The first metal or insulator is removed from the first metal and the second metal is used to completely form a dart electrode having an inverted convex cross-sectional structure. 'Registno'? Since the ion-implanted t-row source/drain regions are formed using the turn as a mask, it is possible to form darts with a short ff-) length that exceeds the limit of resist drilling in conventional manufacturing methods.

Along with this, it is possible to manufacture an Mg8 FET t- with short distances between the source and f-) and between the dirt and drain, and it is also possible to form 11 source and drain poles very close to the f-) electrode in a self-aligned line. Mk' and 8FBTk with improved high frequency characteristics can be manufactured with high yield.

[Brief Description of the Drawings] Figures 1 (e) and 11) are process explanatory diagrams of the conventional MESFET manufacturing method, and Figures 2 to 2 [F] are respectively the manufacturing method of the semiconductor book of the present invention. Fig. 4 (e) and Fig. 4 are process explanatory diagrams of the second embodiment of the semiconductor device manufacturing method of the present invention, respectively. 5 are process explanatory diagrams of the third embodiment of the semiconductor device manufacturing method of the present invention, and FIG. 5 is a process explanatory diagram of the fourth embodiment of the semiconductor device manufacturing method of the present invention. 21... Medium insulating GaAs substrate, 22... N-type conductive layer. 23.32...Register no and turn, 24.25.3
5...Titanium%26...Platinum, 27.34.36.
... Dirt electrode, 28... Source electrode, 28... Drain 1130.37... Source region, 31.38.
...Drain electrode, 33...Ohmic metal. Patent Applicant: Oki Electric Industry Co., Ltd. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Procedural Amendments September-3, 1980 Kazuo Wakasan, Commissioner of the Patent Office, 1. Indication of the case, 1978 Application No. 85042 No. 2111
I04 Semiconductor device and SOO manufacturing method 3, relationship with the case of the person making the amendment Patent Applicant (6111) Oki Electric Co., Ltd. 4, Agent 5, Date of amendment order Showa year, month, day (fA
6. Subject of amendment 2. Claims (1) A semiconductor device characterized by having an r-) electrode formed of a single metal and having an inverted convex cross-sectional structure on a semiconductor substrate. (2) A first structure having a hole in the r-) region above the operating region of the field effect transistor formed on the first surface of the semiconductor substrate.
The first metal or insulator is placed diagonally in both directions at such an angle that it forms a turn in the resist and is not deposited on the center of the hole, but on the semiconductor substrate around the hole. After the first step of depositing the first metal or the insulating layer on the semiconductor substrate, the first metal or insulating layer is deposited as a PC electrode in the vertical direction on the semiconductor substrate. Step 2: After applying the metal glue 7''It, etching the first metal or insulator to form a dirt plate having a reverse convex cross-sectional structure made of a single metal. , a second resist pattern having holes including source/drain/P-) regions is formed, and ion implantation is performed on the semiconductor substrate using the second resist pattern as a mask to form a cell. A method for manufacturing a semiconductor device comprising a third step of forming source/drain regions in a 7-aligned manner. (3) In the third step, the first metal or insulator and the #!2 metal glue are removed. After performing this, a third resist pattern having holes is formed in the active region of the field effect transistor including the source, dirt, and drain regions, and a third resist pattern is formed after a third metal having ohmic characteristics is deposited. The semiconductor according to claim 2, characterized in that the first metal or insulator is etched and the third metal is removed to form the source and drain in a self-lined manner. Device manufacturing method. (4) In the third step, after depositing the second metal, a fourth metal is continuously deposited, and the first metal or insulator is deposited by the first resist/mother turn. and after lift-off of the second and ±th metals, a third
After forming a resist IJI turn and depositing a third metal, the third resist pattern is removed and the first metal or insulator is etched to form a third metal paste 7 to 7. 3. The method for manufacturing a semiconductor confectionery according to claim 2, wherein the third metal on the ff-) electrode is lifted off by etching the third metal on the ff-) electrode.

Claims (4)

[Claims] (1) A semiconductor device characterized by having an f-) electrode made of a single metal and having an inverted convex cross-sectional structure on a semiconductor substrate. (2) A first structure having a hole in the y-t region above the operating region of the field effect transistor formed on the first surface of the semiconductor substrate.
A resist pattern is formed, and the first metal or insulator is deposited diagonally in both directions at an angle that allows it to be deposited on the semiconductor substrate around the hole, without depositing it on the center of the hole. With the first step. [ as a PC-meter electrode in the vertical direction on the semiconductor substrate
After the first metal or insulator and the second metal are completely lifted off using the first resist pattern, the first metal or insulator is etched. A second step of forming a metal dirt electrode having an inverted convex cross-sectional structure, forming a second resist pattern having holes including source/drain/dirt regions, and connecting this second resist pattern with the gate electrode. A method of manufacturing a semiconductor device which is different from the third step of performing ion implantation onto the semiconductor substrate using a mask as a mask to form source/drain regions in a self-aligned manner. (3) The third step is to apply a third resist having holes in the active region of the field effect transistor including the source/r-)-drain region after lift-off of the first metal or insulator and the second metal. After forming a pattern and depositing a third metal having ohmic characteristics, the third resist pattern is removed, the first metal or insulator is etched, and the third metal is lifted off to form a source. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the drain is formed by fan-in. (4) In the third step, after the second metal is vapor-deposited, a fourth metal is continuously deposited, and the first metal or insulator and the second and third metals are separated by the first resist pattern. After performing lift-off, a third resist pattern is formed in the active region of the field effect transistor including the source, dirt, and drain regions, and a third metal is deposited, and then the third resist pattern is removed and a third resist pattern is formed. Claim 1, characterized in that after a third metal lift-off is performed by etching the first metal or insulator, a fourth metal is etched to lift-off the third metal on the dirt electrode. 2. A method for manufacturing a semiconductor device according to item 2.