JPS61176162A - Field-effect semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable to enhance the operating speed of an MOSFET or to enable the MOSFET to operate in a high frequency by a method wherein the structure thereof is made into a structure, wherein the MOSFET is provided with a Schottky gate electrode having a T-shaped section and both sides of the T-shaped vertical part thereof are embedded with an insulating film. CONSTITUTION:A high-impurity concentration region 18 is formed in the n-type active region excluding the channel part therein, and after that, a fifth SiO2 film 17 is removed and an etching is performed on a WSi film 13 from both sides thereof using a third SiO2 film 14 as a mask to make finer the lineal width thereof. The lineal width is processed finer into a lineal width of 0.3mum finer than the initial lineal width of 1mum. Then, after the SiO2 film 14 is removed, a sixth SiO2 film 19 is coated over the whole surface of the substrate in a thickness of 2,500Angstrom . Then, the WSi layer being left is removed by performing a dry etching and a window 20 is formed. A multilayer gate electrode 25 consisting of Ti, Pt and Au is formed in the window 20. By this way, the contact width (channel part) of the gate electrode 25 can be extremely lessened, and moreover, the resistivity Rg of the gate electrode can be brought into a sufficiently low value.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a so-called MES FE that uses a Schottky barrier as a gate in a field effect transistor (FET) structure that is often used in the microwave region.
The present invention relates to the structure and manufacturing method of T.

MEtal Sem1-co uses GaAs for oscillation and amplification in the frequency range of several GHz to 20 GHz, and utilizes the Schottky barrier between metal and semiconductor.
FETs are becoming widely used, but in order to improve the performance of such transistors, it is desired that the channel length be shortened to reduce parasitic capacitance and parasitic resistance.

To achieve this, finer patterns and higher precision are required.
In addition, the application of self-alignment (self-alignment) technology is becoming more important in their manufacturing.

[Conventional technology]

GaAs MESFET for microwave using conventional technology
The structure of is shown in Figure 2. Its structural features can be summarized as follows.

(1) Source resistance (Rs) 3, drain resistance (Rd
) 4, the n-type GaAs layer 2 other than the channel part is made thicker, and a so-called recessed structure (a structure in which the gate and channel part 6 are arranged in a deep recessed part) is adopted. many.

(2) The Schottky gate electrode 5 is made of aluminum strip and is placed at the bottom of the recess structure.

(3) The source and drain ohmic contact electrodes 7.8 are made of AuGe-Au and are arranged at the highest point of the n-type GaAs layer.

[Problem that the invention seeks to solve]

The prior art methods described above result in various deficiencies as described below.

(1) The gate electrode must be made thinner in order to shorten the channel length l and reduce its Schottky junction capacitance, but it must be formed at the bottom of the groove, making microfabrication difficult, making controllability and reproducibility difficult. is poor, thus reducing yield.

(2) Furthermore, since the cross-sectional shape of the gate electrode is rectangular, if the channel length is shortened, the thickness must also be reduced for processing purposes, so that the gate resistance R rapidly increases.

(3) Since aluminum is used for the gate electrode, it cannot be said that reliability is high in terms of heat resistance, electromigration silane, etc.

(4) The recessed structure is inherently disadvantageous in terms of precision in mask alignment patterning, and the gate electrode 5 is made of aluminum material, the source and drain electrodes 7 and 8
Because it uses gold thread material, it is not suitable for processing semiconductor devices that require microfabrication.

[Means for solving problems]

The above-mentioned problem includes a Schottky gate electrode having a T-shaped cross section, and the lower end of the vertical portion of the T-shape contacts the semiconductor substrate to form a Schottky junction. Further, both sides of the vertical portion of the T-shape are solved by a structure of a field effect semiconductor device having a structure buried by an insulating film formed on the source and drain regions with high impurity concentration.

Further, manufacturing of such a field effect semiconductor device is solved by the following method.

That is, two layers of a high heat resistant material film and then an insulating film are laminated on a region of one conductivity type element of a compound semiconductor substrate, and these two layers are etched away leaving a strip pattern.

Next, impurities of one conductivity type are introduced into the semiconductor substrate using the strip pattern as a mask, and then the high heat resistant material film of the strip pattern is side-etched to narrow the pattern width.

The problem is solved by a method for manufacturing a field effect semiconductor device, which includes a step of depositing an insulating film over the entire surface of the element forming area and then removing the side-etched high heat-resistant material film to form a Schottky junction window. Ru.

[Effect]

In the present invention, a source contact region,
High concentration ion implantation and annealing are performed to form a drain contact region, and the source resistance Rs and drain resistance Rd are reduced.

In addition, by side-etching this refractory metal silicide, submicron-width gate windows are formed in self-alignment with the source and drain contact regions, and the gate electrode is shaped like a T-shape. , gate resistance R
Significantly reduce g.

Furthermore, the gate electrode adopts a multilayer electrode made of gold thread with a highly reliable Ti-Pt-Au composition, and the T-shaped gate electrode is supported by an insulating spacer, so it is resistant to thermal cycles, mechanical vibrations, and shocks. However, it is durable.

〔Example〕

Hereinafter, the structure and manufacturing method of an embodiment of the present invention will be described in detail.

As shown in FIG. 1(a), a semi-insulating substrate 1 of GaAs doped with chromium (Cr) is prepared, and a first silicon dioxide (Stow) film 9 is formed on one main surface thereof. Next, the window 10 of the SiO□ film is selectively removed as an element forming portion.

The SiOz film is formed by a CVD method or a sputtering method, and a normal photolithography method can be applied to selectively remove SiO□. Then,
Using the SiO□ film 9 with the window 10 as a mask, silicon St'' is ion-implanted into the semi-insulating substrate.

Silicon ion implantation was performed at 175 KeV and at a dose of 2.
6×101! carried out in al-2.

Next, SiO! is formed using a chemical etching method. The film 9 is removed, and a second 5iO- film 11 is deposited in a similar manner by about 1,000 people. Thereafter, the substrate is annealed in nitrogen gas at about 850° C. for 15 minutes to form an n-type active region 12. This is shown in Figure 1 (g)).

Next, as shown in FIG. 1(C), a SiOz film 1
1, and a layer 13 of a refractory metal silicide, for example, tungsten silicide (WSi) with a thickness of approximately 500 mm, and a third SiO□ film 14 of 2000 mm thick are formed on the semi-insulating substrate 1.
person-covered person-covered.

The above-mentioned WSi is easily deposited by vacuum evaporation or sputtering.

Next, the SiO□ film 14 is selectively removed by photolithography, leaving the gate portion, and then SiO
Using the z film as a mask, the WSi layer is dry etched using a mixed gas of CF a and 0□ to obtain the shape shown in FIG. 1 (dl).

Next, as shown in FIG. 1+8), a fourth 5iCh film 15 is again deposited on the main surface of the substrate to a thickness of about 6,000 layers, and a window region 16 having an area slightly larger than the n-type region 12 is selected by etching. open to the public.

Next, using the Sing film 15 and the WSi film 13 as masks, silicon ions are implanted at 175 K e V and at a dose of 1.7XIO "am-". This is shown in FIG. 1(f).

Next, a fifth 5-tot film 17 is applied over the entire surface by approximately 1,000 coats. After that, the substrate was heated at about 850°C in nitrogen gas.
By performing annealing for 15 minutes, a high impurity concentration region 18 is formed in the n-type active region 12 except for the channel portion. This is shown in Figure 1 (phantom).

The two n3 type high impurity regions 18 constitute a source contact region and a drain contact region, respectively.

Next, after the fifth SiO□ film 17 is removed, side etching of the WSt is performed from both sides by dry etching using a mixed gas of CF and 02 using the third Sin film 14 as a mask. , make the line width thinner.

Side etching is performed evenly from both sides, and the line width is reduced from the original 1 μm to 0.3 μm. This is the first
It is shown in FIG.

Then, the remaining SlO! on top of the WSi layer! membrane 14
After removing the sixth SiO
The membrane 19 was applied to 2,500 people, as shown in FIG.

The remaining WSi layer is then coated with CF4 and 0. When removed by dry etching using a mixed gas of
), a window 20 with a width of 0.3 μm is formed.
The mold area is exposed.

This window 20 has n on both sides as shown in FIG.

equidistant from the type source and drain contact regions,
Moreover, it is formed in a self-aligned manner with a minute gap determined by side etching of WSi.

This window 20 becomes a window for creating a gate Schottky junction.

Then, n0 type contact) 5iOd9 on 81 area 18
is selectively removed to expose source contact region 21 and drain contact region 22.

AuG is used in the source and drain contact regions, respectively.
A source electrode 23 and a drain electrode 24 are formed from the electrodes having an e-Au structure using a normal lift-off method, respectively.

Further, a multilayer gate electrode 25 having a Ti-Pt-Au configuration is formed in the window 20 in the gate electrode portion. In this case, Ti becomes the Schottky barrier metal. This state is the first figure)
Shown below.

In the GaAs field effect transistor manufactured through the manufacturing process described above, the contact width (channel length) of the gate electrode in contact with the n-type region can be made extremely small, and the resistance value Rg of the gate electrode can be kept to a sufficiently low value. You can.

In the above explanation, the high-melting point metal silicide used to form the gate window is not limited to WSi, but it can withstand high-temperature heat treatment, does not adversely affect the GaAs substrate, and has etching characteristics different from insulating films such as SiO2. A silicide of a high melting point metal may also be used.

In addition, as an insulating film, 5t3Na, A1zC)3
, AIN, etc. are also applicable.

Furthermore, the present invention is applicable not only to a single gate FET but also to an FET with multiple gates or an FE with such a structure.
It is also applicable to integrated circuits containing T.

〔Effect of the invention〕

As explained above, by applying the structure and manufacturing method of the present invention, it has become possible to operate the MES FETo at higher speeds or at higher frequencies.

[Brief explanation of drawings]

FIGS. 1(a) to 1) are cross-sectional views illustrating an apparatus for manufacturing a field-effect semiconductor device according to the present invention in the order of steps, and FIG. 2 is a cross-sectional view of a field-effect semiconductor device manufactured by a conventional method. In the drawing, 1 is a GaAs substrate, 2 is an n-type gap, s3 is a source resistance, 4 is a drain resistance, 5 is a gate electrode, 6 is a channel part, 7 is a source electrode,
8 is a drain electrode, 9, 11.14.15.17.
19 is a SiO film, 10 is an element forming part window, 12
is an n-type active region, 13 is a WSi layer, and 16 is n″
20 is a gate window, 21 is a source contact, 22 is a drain contact M region, 23 is a source electrode, 24 is a drain electrode, and 25 is a gate electrode. Figure 1Figure 1

Claims (2)

[Claims] (1) Schottky gate electrode with a T-shaped cross section;
The lower end of the vertical portion of the T-shape is in contact with the substrate to form a Schottky junction, and both sides of the vertical portion of the T-shape are buried with an insulating film formed on the source and drain regions with high impurity concentration. A field-effect semiconductor device characterized by a structure. (2) A step of laminating two layers of a high heat resistant material film and then an insulating film on a one conductivity type element formation region of a compound semiconductor substrate, a step of etching away the two layers leaving a band-shaped pattern, and a masking of the band-shaped pattern. a step of introducing an impurity of one conductivity type into the semiconductor substrate as a step, a step of narrowing the pattern width of the high heat resistant material film of the strip pattern by side etching, a step of depositing an insulating film on the entire surface of the element forming area, a step of applying the side etched A method for manufacturing a field effect semiconductor device, comprising the step of removing a high heat resistant material film to form a Schottky junction window.