JPH06151467A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To provide the manufacturing method of a self-alignment GaAs MESFET with a T-type gate electrode having 'a two-layer structure composed of a film of the alloy of a high-melting point metal which can be easily shortened in gate length and has a sufficiently low gate resistance and Ti/Au. CONSTITUTION:Ion implantation and activating annealing treatment of an ion- implanted area are performed by a self-alignment technique using a gate electrode provided with a film of the alloy of a high-melting point metal. Then the heads of a gate electrode 6 and alignment mark 7 are exposed by performing reactive ion etching after applying a first resist 11 and flattening the resist 11. After the electrode 6 and mark 7 are exposed, a Ti thin film 12 is vapor-deposited on the surfaces of the electrode 6, mark 7, and resist 11 and a second resist 13 is applied and patterned. After removing the Ti in the opening of the pattern formed of the resist 13 by wet etching and forming a T-type gate electrode having a sufficiently low gate resistance Rg by performing lifting off after vapor-depositing metals 14 and 15 having low specific resistivity, such as Ti, Au, etc., a source and drain electrodes 16 and 17 are formed of an AuGe/Ni alloy.

Description

Detailed Description of the Invention

[0001]

The present invention relates to compound semiconductors, especially Ga
The present invention relates to a method of manufacturing a Schottky gate field effect transistor (hereinafter referred to as MESFET) using As, and particularly to a method of manufacturing a T-type gate electrode.

[0002]

2. Description of the Related Art Currently, a high frequency analog integrated circuit MMIC (Monolithic Microwave) using a GaAs MESFET.
IC) is being actively developed, but in order to realize an integrated circuit that operates at a higher frequency and consumes less power, the cutoff frequency ft and the maximum oscillation frequency fmax of the MESFET forming the integrated circuit are Is high is essential. Therefore, in order to increase the cut-off frequency ft, M
A method of shortening the gate length Lg of the ESFET and increasing the mutual conductance gm has been taken. Another important issue is how to reduce the source resistance Rs and the gate resistance Rg in order to reduce the noise figure NF, which is important as an analog integrated circuit. On the other hand, conventionally GaAs MES
Recess gate FET has been adopted as a FET manufacturing technology, but since recess etching that determines the electrical characteristics of MESFET is performed by the wet etching method, there is a problem in precise control of etching amount and in-plane uniformity and reproducibility of the wafer. It was Therefore, recently, self-alignment using a refractory metal alloy film, which has been conventionally developed for high-speed digital ICs and has excellent in-plane uniformity, as a gate electrode.
Many attempts have been made to apply the structure FET to a high frequency analog integrated circuit.

2A to 2D are cross-sectional views in each main process for explaining a conventional method of manufacturing a self-aligned structure GaAs MESFET using a refractory metal alloy film.

In the figure, first, the alignment mark 7 is formed on the semi-insulating substrate 1 by wet etching using the resist 18 as a mask (FIG. 2a). At this time,
In order for the reduction projection exposure apparatus (stepper) to detect the alignment mark 7 with sufficient accuracy, it is necessary that a step of 100 nm or more is formed on the surface of the semi-insulating substrate 1. Next, using the resist 2 as a mask on the semi-insulating substrate 1, ²⁹ Si ^{+ is used} for an acceleration voltage of 30 keV and a dose amount of 4 × 1.
N of MESFET by selective ion implantation under the condition of 0 ¹² cm ^-2
The shaping layer 3 is formed (FIG. 2b). Next, semi-insulating GaA
The refractory metal alloy film 4 such as WSi is formed on the surface of the substrate 1.
Is deposited by sputtering, and the refractory metal alloy film 4 is etched by reactive ion etching (RIE) using the resist 5 as a mask to form a gate electrode 6 (FIG. 2c). Next, using the resist 8 and the gate electrode 6 as a mask, ²⁸ Si ^{+ is used} for the acceleration voltage of 80 keV and the dose amount of 2 × 10.
Ions are implanted under the condition of ¹³ cm ⁻² to form the n-type high concentration layer 9 by self-alignment (FIG. 2d). Next, an insulating film 10 made of SiO ₂ or the like is deposited on the surface of the semi-insulating GaAs substrate 1 to a thickness of about 10 to 500 nm by a plasma CVD method or the like, and this is used as a protective film at a temperature of about 800 ° C. in an N ₂ atmosphere. Heat treatment (annealing) for about 15 minutes is performed to activate the implanted impurities (FIG. 2e). Next, a predetermined portion of the insulating film 10 is opened with buffered hydrofluoric acid or the like, and an AuGe / Ni alloy is deposited to a thickness of about 200 nm by a lift-off method, followed by heat treatment (sintering) to form the source electrode 16 and the drain electrode. 17 is formed to complete the GaAs MESFET (FIG. 2f).

[0005]

In a conventional method of manufacturing a GaAs MESFET used for a high frequency analog integrated circuit MMIC, a self-alignment (self-alignment) method which is advantageous in terms of controllability and uniformity of electric characteristics in place of the recess gate structure FET is used. The adoption of matching structure FETs has been considered.
However, the specific resistance of the refractory metal alloy film used for such a self-alignment structure is WS.
i is about 50 to 500 μΩ · cm, which is 20 to 200 times the specific resistance of conventional aluminum of 2.5 μΩ · cm,
As the gate length becomes shorter, the cross-sectional area of the gate electrode decreases, and the increase in the gate resistance Rg becomes non-negligible, which is a major factor limiting the high frequency characteristics of the FET.

For this reason, there is an attempt to reduce the gate resistance Rg by depositing a metal having a low specific resistance such as Au on the gate electrode after the heat treatment (annealing), but it is possible to obtain a high reproducibility of 1 μm or less by a simple method with good reproducibility. It was very difficult to deposit Au on the gate electrode made of the melting point metal alloy film.

The present invention is to provide a method of manufacturing a self-aligned structure GaAs MESFET using a refractory metal alloy which can theoretically produce a T-type gate electrode having a sufficiently low gate resistance Rg no matter how small the gate length is. To aim.

[0008]

In order to achieve the above object, the present invention first uses a self-alignment technique by a gate electrode using a refractory metal alloy film to perform ion implantation and activation of an implantation region. After annealing (heat treatment), the first resist is applied and flattened, and reactive ion etching is performed to locate the alignment marks formed at the same time when the gate electrode and the gate electrode are formed. A Ti film is vapor-deposited on the surface of the first electrode and the alignment electrode and the alignment mark, and then the second resist is applied to form a pattern to be the upper part of the gate electrode in alignment with the alignment mark. Further, the Ti film in the opening of the second resist pattern is removed by wet etching, and a metal having a low specific resistance such as Ti / Au is vapor-deposited to perform lift-off to obtain a gate resistance Rg.
Of the T-type gate electrode having a sufficiently low

Incidentally, in the case of an alignment mark in which a recess is provided only in a part of the substrate as in the conventional case, the Ti film blocks the laser beam for detecting the alignment mark of the reduction projection exposure apparatus (stepper) and the resist is flattened. Since the step is almost eliminated, the alignment mark cannot be detected and the mask position above the gate electrode cannot be aligned. In order to solve this problem, in the present invention, a new alignment mark is formed at the same time as the gate electrode is formed, and an alignment mark having a sufficient step is formed in the gate electrode heading step, thereby forming a mask on the gate electrode. Positioning is possible.

[0010]

In this way, the ion-implanted layer of the MESFET is formed by the self-alignment method using the high melting point metal alloy film, and after annealing, the high melting point metal alloy film and Ti / By forming a T-type gate composed of two layers of Au, a GaAs MESFET having a T-type gate electrode having a short-gate high-melting-point metal alloy film as a Schottky electrode and having a sufficiently low gate resistance Rg can be easily manufactured. be able to. As a result, the ME having excellent high frequency characteristics such as the cutoff frequency ft and the maximum oscillation frequency fmax is excellent.
SFET can be produced and GaA using this MESFET
The sMMIC has excellent high-frequency characteristics and can be operated with lower power consumption.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a sectional view in each main step for explaining a method of manufacturing a self-aligned structure GaAs MESFET having a T-type gate electrode, for explaining one embodiment of the first invention. is there.

In the figure, first, the semi-insulating substrate 1 is
Strike 2 as a mask²⁹Si⁺ Acceleration voltage of 30 keV,
Dose amount 4 × 10¹²cm^-2Selective ion implantation under conditions of M
The n-type operating layer 3 of the ESFET is formed (FIG. 1a). next
On the surface of the semi-insulating GaAs substrate 1, high melting material such as WSi
The point metal alloy film 4 is formed to a thickness of about 500 nm by the sputtering method.
Then, using the resist 5 as a mask, the reactive ion
Etching the refractory metal alloy film 4 by etching (RIE).
Gate electrode 6 and reduction projection exposure apparatus (step
Form the alignment mark 7 for mask overlay
(Fig. 1b). Next, the resist 8 and the gate electrode
Use pole 6 as a mask,²⁸Si⁺ Acceleration voltage 80 keV,
Dose 2 × 10¹³cm^-2Self-alignment by ion implantation under the conditions
To form the n-type high concentration layer 9 (FIG. 1c). Then semi-insulated
On the surface of the crystalline GaAs substrate 1 ₂ Insulation film 10 such as
Deposited with a thickness of about 10-500 nm by plasma CVD method etc.
N as a protective film₂ Around 800 ℃ in the atmosphere
Injected after heat treatment (annealing) for about 15 minutes
The impurities are activated (FIG. 1d). Next, the insulating film 10
After removing it with hydrofluoric acid, etc.
It is applied in a thickness of m to flatten the resist. At this time
Gist 11 with a low viscosity is more suitable for flattening, and
It is also effective to perform heat treatment (post-baking) (Fig. 1
e). Then O ₂ Reactive ion etching with plasma
The resist 11 is etched by (RIE) to obtain the target.
Cue electrode 6 and alignment mark 7
U At this time, an optical method is used for the final film thickness of the resist 11.
Monitored using the film thickness measuring device used, about 300 nm
(Fig. 1f). Next, if the gate electrode 6
And the resist 1 where the head of the alignment mark 7 is exposed
50 Ti film 12 on the surface of No. 1 by electron beam evaporation method.
vapor-deposited to a thickness of nm, apply a second resist 13 and
The alignment mark 7 formed simultaneously with the
The pattern on the gate electrode is exposed by exposing it to light and developing it.
(Fig. 1g). At this time,
With an alignment mark that only has a recess in a part of the plate
Is a thin film projection aligner (stepper) aligner.
In addition to blocking the laser beam for detecting the ment mark, the resist
Alignment because it is flattened and steps are almost eliminated
The mark cannot be detected and the mask position above the gate electrode
I can't make it. In order to solve this problem, the present invention
Is a new alignment mark when the gate electrode is formed.
And a sufficient step in the gate electrode heading process.
By forming an alignment mark with
The mask position above the gate electrode can be aligned. Next
Then, the Ti film 12 in the opening of the second resist 13 is fluorinated by 1%.
After removing with an acid, the Ti film 14 and
The Au film 15 was vaporized to a thickness of 50 nm and 500 nm, respectively.
Wear (Fig. 1h). Next, in the acetone
Lift off the metal film to complete the T-shaped gate electrode
(Fig. 1i). After that, lift-off method using resist
The AuGe / Ni alloy with a thickness of about 200 nm.
And heat-treat (sinter) the source electrode 16 and
And the drain electrode 17 are formed to form a GaAs MESFET
Complete (Fig. 1j).

In this way, a self-aligned structure GaAs MESFET having a T-type gate electrode is manufactured. It is needless to say that the present embodiment is merely an example, and improvements and changes can be made without departing from the configuration of the present invention.

[0014]

As described above, according to the present invention, a T-type gate electrode having a two-layer structure of a refractory metal alloy film having an extremely short gate length Lg and Ti / Au having a low electric resistance can be easily manufactured. be able to. As a result, the gate length Lg of the MESFET can be shortened, the gm of the FET can be increased, and in addition, a GaAs MESFET having an extremely small gate-source capacitance Cgs and a sufficiently low gate resistance Rg can be easily manufactured. Therefore, the GaAsMMIC using the MESFET according to the present invention has excellent high frequency characteristics and can be operated with lower power consumption.

[Brief description of drawings]

FIG. 1 is a sectional view of a manufacturing process of a GaAs MESFET according to the present invention.

FIG. 2 is a sectional view of a conventional GaAs MESFET manufacturing process.

[Explanation of symbols]

 1 semi-insulating substrate 2 resist 3 n-type operating layer 4 WSi 5 resist 6 gate electrode 7 alignment mark 8 resist 9 n-type high concentration layer 10 insulating film 11 first resist 12 Ti film 13 second resist 14 Ti film 15 Au film 16 Source electrode 17 Drain electrode 18 Resist

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical display location H01L 21/28 301 G 7376-4M 21/027 21/306 N 9278-4M 8617-4M H01L 21 / 265 A 7352-4M 21/30 301 M 7376-4M 29/80 M

Claims (4)

[Claims] 1. A step of depositing a refractory metal alloy film which maintains a Schottky junction on the surface of a semi-insulating substrate by sputtering or the like, and the refractory metal by a reactive ion etching or the like using a resist or the like as a mask. A step of etching the metal alloy film to form a gate electrode and an alignment mark for mask overlay of a reduction projection exposure apparatus (stepper); and a first step on the surface of the semi-insulating substrate on which the gate electrode and the alignment mark are formed. A step of applying a resist to flatten the first resist; a step of etching the first resist by reactive ion etching or the like to cue the gate electrode and the alignment mark; A first metal such as Ti is deposited on the head of the alignment mark and the surface of the first resist. A step of applying a second resist on the surface of the substrate on which the first metal is deposited, and forming a resist pattern serving as an upper electrode on the gate electrode in alignment with the alignment mark; Removing the first metal in the opening with hydrofluoric acid or the like;
And a step of depositing a second metal having a low specific resistance such as Au on the second resist pattern to perform lift-off, and a method for manufacturing a field effect transistor. 2. The refractory metal alloy film comprises tungsten silicide (WSi), tungsten silicon nitride (WSiN), tungsten nitride (WN),
2. The method for manufacturing a field effect transistor according to claim 1, comprising at least one of a refractory metal film or a refractory metal alloy film such as tungsten aluminum (WA1). 3. The first metal is not limited to Ti but is Al or Ni.
The method for manufacturing a field effect transistor according to claim 1, wherein the field effect transistor is made of a metal that can be easily wet-etched with hydrofluoric acid, hydrochloric acid, or the like. 4. The method for manufacturing a field effect transistor according to claim 1, wherein the second metal is not limited to Au but is made of a metal having a low electric resistivity such as Al.