JPH02278738A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve machining accuracy and throughput by forming a resist pattern which is thicker than a desired pattern length on a metal film on a substrate, by etching a metal film with this resist pattern as a mask, and by performing anisotropic etching on both side surfaces of the metal pattern. CONSTITUTION:A metal film 2 is formed on a semiconductor substrate 1 and a resist pattern 3 is formed on the upper surface of this metal film 2. In this case, the resist pattern 3 should be thicker than a desired pattern length 1SM. Then, the metal film 2 is etched utilizing the resist pattern 3 and a metal pattern 4 is formed on the semiconductor substrate 1. Anisotropic etching is performed to both side surfaces 4a and 4b of the metal pattern 4 which is thicker than the desired pattern length 1SM, thus machining to a metal pattern 5 of a desired pattern length 1SM. Thus, it becomes possible to obtain a fine metal pattern.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a field effect transistor having a submicron gate length.

[Conventional technology]

Recently, microfabrication technology for semiconductor devices has been attracting attention. For example, miniaturizing the gate length of a field effect transistor increases the speed of the transistor and improves its high frequency characteristics. Furthermore, the degree of integration of the semiconductor device can be improved.

In conventional semiconductor device manufacturing technology, a field effect transistor is manufactured by forming a fine pattern using a lift-off technique using a multilayer resist (high-speed GaAs I
Self-aligned implantation technique for C n+ layer (“5ELF-A
LIGN IMPLANTATION PORn ”-
LAYERTECIINOLOGY (SAINT) FO
RHIGH-3PEEDGaAs ICs''), Electronics Letters (ELECTl?0NIC8LE
TTER3), 4th February 1982
Vo1.1g No, 3. pp, 119-121)
Alternatively, a method is known in which a semiconductor device is manufactured by exposing a fine pattern using an electron beam exposure device.

[Problem to be solved by the invention]

However, the method using a multilayer resist has the disadvantage that the process itself is complicated and the processing accuracy is poor.

Furthermore, the method using an electron beam exposure apparatus requires processing such as adjusting the exposure amount to prevent the proximity effect, and has the disadvantage that processing throughput cannot be increased.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device with good processing accuracy and high throughput.

[Means to solve the problem]

In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes three steps. Here, in the first step, a metal film is formed on the substrate, and a resist pattern that is thicker than a desired pattern length is formed on this metal film. In the second step, the metal film is etched using this resist pattern as a mask to form a metal pattern that is thicker than the desired pattern length. In the third step, anisotropic etching is performed on both sides of the metal pattern to process the metal pattern into a desired pattern length.

[Effect]

Since the present invention is configured as described above, the pattern length of the metal pattern obtained by the resist pattern is further reduced by anisotropic etching from the side.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the accompanying drawings. In the description, the same elements are denoted by the same reference numerals, and repeated description will be omitted.

FIG. 1 is a process diagram showing the basic concept of the present invention. First, a metal film 2 is formed on a semiconductor substrate 1 by a vacuum evaporation method or the like. A resist film (not shown) is formed on the upper surface of the metal film 2 by spin coating, and a resist pattern 3 is formed using photolithography (see FIG. 3(a)).
. In this case, the resist pattern 3 is made thicker than the desired pattern length lSM. Next, the metal film 2 is etched using this resist pattern 3, and the semiconductor substrate 1 is etched.
A metal pattern 4 is formed on top. Since the etched metal pattern 4 is etched using the resist pattern as a mask, it is thicker than the desired pattern length 'S)l (see FIG. 1(b)). Next, anisotropic etching is performed on both sides 4 a s 4 b of this metal pattern 4 to obtain a desired pattern length 'S'.
It is processed into a metal pattern 5 of H ((C) in the same figure). According to this manufacturing method, it is possible to obtain a fine metal pattern that is thinner than the pattern length obtained with a resist pattern.

Next, an application example of manufacturing a field effect transistor using the above embodiment will be described. FIG. 2 shows the manufacturing process of a field effect transistor according to this application example. First, a resist pattern 7 is formed on a semi-insulating GaAs2Z plate 6. Using this resist pattern 7 as a mask, ions that become n-type impurities in the FET 6M region, for example, S
L2 is implanted at a low acceleration voltage to form a low concentration (n'' type) active layer region 6a (FIG. 2(a)).

Thereafter, this resist pattern 7 is removed, and a SiO□ film 8 of 1000 angstroms in thickness is continuously formed on the active layer region 6a by atmospheric pressure CVD and an AI film 9 of 5000 angstroms in thickness by vacuum evaporation. Furthermore, this AI
For example, a resist pattern 1 having a width of 0.5 μm is formed on the upper surface of the film 9.
0 is formed using photolithography technology ((b) in the same figure)
. This resist pattern 10 is thicker than the target pattern length. Next, using this resist pattern 10 as a mask, the AI film 9 is etched to form an A1 dummy electrode 11 (metal pattern) (FIG. 3(C)). This AI dummy electrode 11 is thicker than the target pattern length and is located on the gate formation region of the GaASu layer 6.

Thereafter, a photoresist is applied by spin coating, and a resist pattern 12 is formed by photolithography. Using this resist pattern 12 as a mask, ions that will become n-type impurities are implanted at a high acceleration voltage to form n + -type regions 6s6d that will become source formation regions and drain formation regions in the GaAs substrate 6 (FIG. 2(d)). ) Next, the resist pattern 12 is removed, and the AI dummy electrode 11 is subjected to directional etching from an angle of 0 to 10 degrees with respect to the substrate plane by ion milling to narrow the pattern length of the A1 dummy 71!511. ((e) in the same figure).

After that, by plasma CVD method, SiN or 5i
An insulating film 13 such as ON is formed on the SiO2 film 8 to a thickness of 1000 angstroms (FIG. 1(f)), and the insulating film 13 on the side wall of the Al dummy electrode 11 is removed using buffered hydrofluoric acid (FIG. 1(f)). g)).

Next, the At dummy mtItll is removed using hydrochloric acid or the like to obtain a fine-sized gate pattern 13g on the gate formation region. Furthermore, an opening 13s113d is provided in the insulating film 13 on the n+ type region 6S6d using buffered hydrofluoric acid ((h) in the same figure).
).

Next, the gate pattern 13g and the opening 13s113d
The S t O2 film 8 exposed to the Si
Openings 8g, 8s, and 8d are formed in the O□ film 8 (FIG. 2(i)). Thereafter, an annealing process is performed to activate the ion implantation region. Finally, ohmic electrodes 14 and 15 are formed on the n+ type region 6s6d, and a gate electrode 16 is formed on the gate formation region.

Note that this invention is not limited to the above embodiments. For example, after forming the n-type regions 6s and 6d and reducing the pattern length of the Al dummy electrode 11 (see FIG. 2(e)), the intermediate resistance between the n+-type region 6s6d and the active layer region 6a is determined. By forming n-type regions with ion implantation on both sides of the Al dummy electrode 11, LDD (Light
tly-Doped Drain) structure can be formed. In this case, source resistance and drain resistance can be reduced, short channel effects can be reduced, and mutual conductance can be increased.

Furthermore, the material of the semiconductor substrate is not limited to GaAs, but may also be InP.

〔Effect of the invention〕

Since this invention is configured as explained above,
A semiconductor device with good processing accuracy and high throughput can be manufactured.

In particular, when manufacturing a field effect transistor, the electrodes can be formed in self-alignment with the dummy gate pattern, resulting in good reproducibility.

Further, by directional etching from the side surface of the metal pattern, a dummy gate pattern for forming a fine gate electrode of half micron or quarter micron can be easily formed.

[Brief explanation of drawings]

FIG. 1 is a process diagram showing the basic concept of the present invention, and FIG. 2 is a process diagram showing a method for manufacturing a field effect transistor according to an applied example of the present invention. 1... Semiconductor substrate, 2... Metal film, 3.7.10.
12...Resist pattern, 4.5...Metal pattern, 6-...-GaAsuffi, 8・''S
tO2 film, 9. A1 film, 11... A1 dummy electrode, 13... Insulating film, 14.15... Ohmic electrode, 16... Gate electrode. Representative Patent Attorney Yoshiki Hase
Mountain 1) Imaaki Yukimoto's basic concept Figure 1 Application example step 1 ('/3) Figure 2 (1) Application example process (2/3) Figure 2 (2)

Claims (1)

[Claims] A first step of forming a metal film on a substrate and forming a resist pattern thicker than a desired pattern length on the metal film; etching the metal film using the resist pattern as a mask; a second step of forming a metal pattern thicker than a desired pattern length; performing anisotropic etching on both sides of the metal pattern;
A method of manufacturing a semiconductor device comprising a third step of processing the metal pattern into a desired pattern length.