JP2707612B2 - Method for manufacturing field effect transistor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a field effect transistor. More specifically, the present invention relates to a method for manufacturing a self-aligned field effect transistor using a substrate such as a compound semiconductor.

[Summary of the Invention]

The present invention minimizes the gate-source distance as much as possible,
A method of manufacturing a self-aligned field effect transistor capable of setting a gate-drain distance to an arbitrary length, comprising: a first semiconductor region (source region) and a second semiconductor region on a surface of a semiconductor substrate; (Drain region) is formed.

2. First and second insulating layers are formed only on the source and drain regions using a first insulating material such as Si ₃ N ₄ .

3. The third and fourth insulating layers are continuously formed using the first insulating material on the mutually facing side walls of the first and second insulating layers.

4. The fifth and sixth insulating layers are continuously formed on the opposing side walls of the third and fourth insulating layers by using a second insulating material such as SiO ₂ having a conjugate relationship with the first insulating material. Form a layer.

5. On the surface of the semiconductor substrate between the fifth and sixth side walls, a second
The seventh insulating layer is formed using a first insulating material or a third material which has a conjugate relationship with the insulating material.

6. Selectively remove at least one of the fifth and sixth insulating layers.

If the gate electrode is formed in the region where the insulating layer is selectively removed, the distance between the gate and the source is short,
In addition, the distance between the gate and the drain can be arbitrarily set according to the thickness of the seventh insulating layer.

[Conventional technology]

MES (Met) is used as a high-speed and high-frequency transistor for high-speed digital signal processing or microwave amplification.
Field effect transistors such as Al Semiconductor) FET, J (Junction) FET, and HEMT (High Electron Mobility Transistor) are used. In recent years, ICs integrating these transistors have been developed.

To improve the performance of high-speed and high-frequency transistors,
A technique for forming a fine pattern is important. For example, MESFET
As shown in FIG. 2, the gate-source distance 10 is made as short as possible to reduce the source resistance, and the gate length 9 is made as short as possible to obtain a high mutual conductance, as shown in FIG. It is desirable to set the gate-drain distance 11 to an appropriate length to reduce the gate-drain capacitance and increase the effective transconductance. FIG. 2 shows a conventional photolithographic method.
MESFET. A low-concentration N-type active layer 2 is formed on the surface of a semiconductor substrate 1 such as semi-insulating GaAs by ion implantation, and a high-concentration N-type ion implantation is performed to form a source region 3 and a drain region 4. Do. A source electrode 6 and a drain electrode 7 are formed in a source region and a drain region, respectively, and SiO ₂ 8a is formed between the source region and the drain region.
Is formed, and a portion of the SiO ₂ to be a gate region is removed by a photolithographic method to form a gate electrode 5 of a Schottky barrier. In such a normal photolithography method, there is a limit in resolution based on the accuracy of mask alignment and the wavelength of the light source used, and the distance between the gate and the source is set to 0.
It is extremely difficult to reduce the thickness to 5 μm or less. as a result,
The source resistance becomes non-negligible and reduces the effective transconductance. In order to obtain high transconductance, it is necessary to shorten the gate length. However, it is difficult to form a gate length of 0.5 μm or less with good reproducibility by a usual photolithography method.

Also, electron beam exposure and X-ray exposure have been studied, and there have been reports that the resolution has been improved to 0.1 μm or less, which is useful for forming fine patterns. However, the apparatus is extremely expensive and is not suitable for mass production. Therefore, fine processing by a usual photolithography method is desired.

In order to solve these problems, various new manufacturing methods have been devised, and some of their features and problems will be described.

FIG. 3 shows a self-aligned field effect transistor using a T-type dummy gate. When forming a source region and a drain region, a source region and a drain region are formed by ion implantation using an undercut or T-type dummy gate in a portion to be a gate region on Si ₃ N ₄ 8b, Except for the T-shaped columnar part, that is, the gate region
This is a self-alignment method called a SAINT method in which SiO ₂ 8a is formed and Si ₃ N ₄ in a gate region is removed to form a gate electrode (K. Yamasaki, IEEE Transactions on Electron
Devices Vol.29 No.11 PP.1772 1982). This self-alignment technique is extremely useful for forming fine patterns,
Since the undercut is used in the SAINT method of FIG. 3, the distance between the gate and the source is equal to the distance between the gate and the drain.

Further, as shown in FIG. 4, after the gate electrode 5 is formed, SiO ₂ is deposited on the front surface, and anisotropic etching leaves only the side wall insulators 12 on both side walls of the gate electrode. Form source and drain electrodes on both sides of the insulator. It is a self-aligned method called the SACSET method (T.Furutsuk
a, IEDM Technical Digest, 1984 PP.344).

According to the SACSET method of FIG. 4, the distance between the gate and the source can be made as short as about 0.2 μm. However, the insulator thickness 13 on the side wall is equal on both sides of the side wall. That is, the distance between the gate and the source is equal to the distance between the gate and the drain. Therefore, the distance between the gate and the source is 0.2 μm
If the distance between the gate and the drain is as short as 0.2 μm, the source resistance can be reduced.
The drain-to-drain capacitance increases.

In the self-alignment method as described above, the distance between the gate and the source is equal to the distance between the gate and the drain. That is, the source and the drain can be formed only at positions symmetrical with respect to the gate. In order to avoid a decrease in the effective transconductance due to this symmetry, a gate can be relatively easily formed at an asymmetric position by using an oblique evaporation method by evaporation or an exposure method by an electron beam. However, in the oblique deposition method, it is difficult to form the film uniformly with good reproducibility, and there is a design restriction that the source must be in only one direction with respect to the gate. If an exposure method using an electron beam is used, an asymmetric gate can be formed with good reproducibility at a gate-source distance of about 0.1 μm. However, the exposure apparatus itself is extremely expensive, and mass production is difficult. Was extremely low.

[Problems to be solved by the invention]

The present invention provides a high-speed, high-frequency method in which the distance between the gate and the source can be set to be short, and the distance between the gate and the drain can be set to an arbitrary length by the ordinary photolithography method excellent in mass productivity. The field effect transistor of the present invention is intended to be realized.

[Means for solving the problem]

In order to achieve the above-mentioned object, the present invention utilizes an opposing side wall of an insulator on a source and a drain region, closes to a source, has a very short gate length, and reduces a gate-drain distance. Provided is a method of manufacturing a self-aligned field-effect transistor that can be set to an arbitrary length. That is, an insulating layer is formed on a surface of a semiconductor substrate on a region to be a source and a drain by a first insulating material such as Si ₃ N ₄ , and the first insulating material is continuously applied to side walls facing each other. Then, an insulating layer is formed on the side wall with a _second insulating material having a conjugate relationship with the first insulating material, for example, SiO ₂ or the like. The conjugation relationship here means the first
A relationship in which the second insulating material is not etched by the etchant used to etch the insulating material;
Or the opposite relationship. Further, an insulating layer is formed between the side walls by a first or third insulating material having a conjugate relationship with the second insulating material on the surface of the semiconductor substrate, and the insulating layer formed by the second insulating material is formed. Self-aligned by selectively removing the layer to make it a gate region, the distance between the gate and source is extremely short, and the distance between the gate and drain can be set to any length. Field effect transistor can be realized.

[Action]

The thickness of the third insulating layer formed by continuously forming the first insulating material on the side walls of the insulating layer on the first and second semiconductor regions is the gate-source distance, and is formed by the second insulating material. The thickness of the removed insulating layer defines the gate length. Further, since the distance between the gate and the drain between two opposing side walls defines the distance between the gate and the drain, a self-aligned gate can be formed and an asymmetric gate field effect transistor can be realized.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS.

An active layer 22 is formed by implanting an N-type low concentration impurity to be a channel by ion implantation or the like over the entire surface of a semi-insulating semiconductor substrate 21 such as GaAs. A photoresist 25 is applied as a mask material to the surface of the semiconductor substrate 21 to remove the photoresist on the regions to be the first and second semiconductor regions, and selectively remove high-concentration N-type impurities. The first semiconductor region 23 and the second semiconductor region 24 are formed by implantation by an implantation method or the like. (FIG. 1a). In this embodiment, the first semiconductor region is described as a source region, and the second semiconductor region is described as a drain region. As the material of the mask, SiO ₂ or the like may be used in addition to the photoresist.
Next, while leaving the photoresist 25 used in FIG. 1A, Si ₃ N ₄ is applied as a first insulating material 26 in this embodiment by a CVD method or the like (FIG. 1B). Next, if the photoresist 25 and Si ₃ N ₄ on the photoresist are removed by etching as a lift-off method or a planarization technique, the first insulating layer 26a and the second insulating layer 26a are formed only on the source region and the drain region, respectively. The two insulating layers 26b can be left (FIG. 1c). Next, in order to form third and fourth insulating layers, Si ₃ N ₄ as the first insulating material is continuously applied again on the entire surface (FIG. 1d). Next, the first insulating material 26 deposited in FIG. 1D is etched by anisotropic dry etching, for example, a reactive ion etch (RIE) method, so that the first insulating material 26 is coated on the side walls. Only the attached first insulating material can be left, and the third insulating layer 26c and the fourth insulating layer 26d can be formed (FIG. 1e). Third insulating layer 26c deposited on the side wall of the first insulating layer
Since the thickness 27 becomes the distance between the gate and the source, it is important to form the insulating layer to a predetermined thickness of about 0.2 μm. Next, a second insulating material 28 having a conjugate relationship with the first insulating material, for example, SiO _{2 is applied} to the entire surface (FIG. 1f).
Next, if SiO ₂ as the second insulating material is etched by anisotropic dry etching, the SiO ₂ deposited on the side walls of the third and fourth insulating layers can be left, and the fifth insulating layer 28
a and the sixth insulating layer 28b can be formed (first
Figure g). Fifth insulating layer 28 applied to sidewalls of third insulating layer
The thickness 29 of a becomes the gate length. By controlling the thickness of the insulating layer, the gate can be formed with a required gate length, for example, about 0.5 μm with good reproducibility. Next, the fifth and sixth
The first surface of the semiconductor substrate facing between the side walls of the insulating layer
Is applied and etched to planarize, thereby forming a seventh insulating layer 30 (FIG. 1h). Next, a photoresist 25 is applied on the second semiconductor region including the sixth insulating layer 28b provided on the side wall of the region to be the drain, and a fifth insulating layer of SiO ₂ as the _second insulating material is formed. Only 28a is selectively removed. In order to remove only SiO ₂ , an insulating material having a conjugate relationship with SiO ₂ , for example, Si ₃ N ₄ may be used as the material of the first, second, third, fourth, and seventh insulating layers. The seventh insulating layer 30 need not be the same as the material of the third and fourth insulating layers, but may be formed using a third insulating material, such as Al ₂ O ₃ , which has a conjugate relationship with the _second insulating material. Is also good. In this manner, the opening 31 of the gate region can be formed by removing the fifth insulating layer 28a provided on the side wall of the third insulating layer 26c (FIG. 1i). Next, a material for forming a Schottky barrier, for example, Mo or the like is formed in the opening 31 of the gate region to form a gate electrode 32 (FIG. 1j). Next, the first semiconductor region 23 (source region) and the second semiconductor region 24
An opening is formed in the Si ₃ N ₄ on the (drain region) by etching (FIG. 1 k). Next, a source electrode 33 and a drain electrode 34 are formed in the source and drain openings, respectively.

Through the above steps, a field-effect transistor that is self-aligned, has a short gate-source distance, and can set the gate-drain distance to an arbitrary length using a normal photolithography method. Can be done.

In this embodiment, the field effect transistor is a MESFET
However, the invention may be applied to other field-effect transistors, for example, a MOSFET using a silicon semiconductor substrate,
Although the first insulating material is described as Si ₃ N ₄ and the second insulating material is SiO ₂ , the first insulating material may be Al ₂ O ₃ and the second insulating material may be SiO ₂ . The method for manufacturing a field effect transistor using the region of the fifth insulating layer as a gate region has been described. However, the region of the sixth insulating layer is used as a gate region, the second semiconductor region is used as a source region, and the first semiconductor is used. The region may be a drain region. Further, the region of the fifth insulating layer is a first gate region, and the region of the sixth insulating layer is a second gate region.
The gate region may be used as a field-effect transistor that shields between the first gate and the drain with the second gate.

〔The invention's effect〕

In the field effect transistor according to the present invention, the gate is formed by using the source side wall of the source and the drain facing each other, so that the distance between the gate and the source can be reduced, the source resistance can be reduced, and the gate and the drain can be reduced. By setting the distance to an arbitrary length, the gate-drain capacitance can be reduced and the withstand voltage can be increased, realizing high-frequency field-effect transistors and ICs for high-speed digital signal processing or amplification in the microwave region. I can do it.

[Brief description of the drawings]

1a to 1 are process diagrams showing a method for manufacturing a field effect transistor according to an embodiment of the present invention, FIG. 2 is a sectional view of a field effect transistor using a conventional photolithographic method, and FIG. FIG. 4 is a cross-sectional view of a conventional self-aligned field-effect transistor using a gate, and FIG. 4 is a cross-sectional view of a self-aligned field-effect transistor using an insulator formed on a gate side wall. 1, 21 semiconductor substrate 2, 22 active layer 3, 23 first semiconductor region (source region) 4, 24 second semiconductor region (drain region) 5, 32 gate electrode 6 , 33 ...... source electrode 7, 34 ...... drain electrode _{8a ...... SiO 2 8b ...... Si 3} N 4 9 ...... gate length 10 ...... gate-source distance 11 ...... gate-drain distance 12 ...... sidewall of the insulator 13 thickness of insulating material ...... sidewall 25 ...... photoresist 26 ...... first insulating material (Si ₃ N ₄₎ 26a ...... first insulating layer 26b ...... second insulating layer 26c ... .. Third insulating layer 26d fourth insulating layer 27 thickness of third insulating layer 28 second insulating material (SiO ₂ ) 28a fifth insulating layer 28b sixth Insulating layer 29: thickness of fifth insulating layer 30: seventh insulating layer 31: opening in gate region

Claims (1)

(57) [Claims] A first semiconductor region opposed to the semiconductor substrate at a distance from a surface of the semiconductor substrate; and a first semiconductor region on the first semiconductor region on the surface of the semiconductor substrate.
Forming first and second insulating layers with a first insulating material;
Forming a third and a fourth insulating layer on the first and the second insulating layer by using the first insulating material, respectively; and opposing side walls of the third and the fourth insulating layer. To
Fifth and sixth insulating layers are formed successively on the third and fourth insulating layers, respectively, by a second insulating material having a conjugate relationship with the first insulating material, and the fifth and sixth insulating layers are formed. On the surface of the semiconductor substrate between the side walls of the insulating layer,
Forming a seventh insulating layer with one of the first insulating material and the third insulating material in a conjugate relationship with the second insulating material; Selectively removing at least one of the insulating layers.