JPH0818056A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To reduce the ion implantation process, and lessen the manhour in manufacture, and enlarge the freedom in design, and further, improve the accuracy in alignment between a source and a drain region and an offset region. CONSTITUTION:This is the manufacture of a field effect transistor which has a process of forming an ion implantation stopping layer 25 on a semiconductor layer 22, a process of processing this ion implantation stopping layer 25 with patterns including a channel region and an offset region 24, and processing the end on drain side at least of the ion implantation stopping layer 25, and a process of forming source and drain regions 23 having offset regions 24 on the semiconductor layer 22 by implanting ions of impurities from above this ion implantation stopping layer 25.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a field effect transistor, and more particularly, to improvement of a method of manufacturing a thin film transistor having an offset region.

[0002]

2. Description of the Related Art A thin film transistor (TFT) is being developed as a drive circuit of a liquid crystal device or a load transistor of a static memory (SRAM). TFT
Then, a channel region, a source region and a drain region of a MOS transistor are formed in a semiconductor layer made of polysilicon or amorphous silicon.

In the TFT, a TFT having an offset region has been developed in order to prevent a drain leak current when the transistor is turned off. By providing the offset region, it is possible to weaken the electric field strength particularly at the drain junction and reduce the drain leak current when the transistor is off.

TF having an offset area according to a conventional example
The principle of the manufacturing method of T will be described with reference to FIG.
As shown in FIG. 6A, first, a non-doped polysilicon film 4 is formed on the substrate 2, and then a thermal oxidation method or a CV method is used.
The insulating film 6 is formed on the non-doped polysilicon film 4 by the D method. After that, a metal mask 8 which also serves as a gate electrode is formed in a pattern such that the channel portion is not doped with impurity ions. Then, the low-concentration ion implantation region 4a serving as an offset region (see FIGS. 6B and 6C)
In order to obtain the above, low-concentration ions 10 with high energy are implanted through the insulating film 6.

Next, in order to obtain a high-concentration ion-implanted region 4b (see FIG. 6 (C)) to be the source / drain region,
Part of the insulating film 6 is removed, and as shown in FIG. 6B, high-concentration ions 12 are implanted again to complete the formation of the low-concentration ion-implanted region 4a which is the offset region.

Then, as shown in FIG. 6C, the source electrode 14 and the drain electrode 16 are formed, and the top gate type TFT is completed.

[0007]

However, this T
The FT manufacturing method has the following problems. First
Moreover, in order to form the low concentration ion implantation region 4a and the high concentration ion implantation region 4b, it is necessary to perform the ion implantation method twice. Therefore, the number of manufacturing steps is increased.

Secondly, at the time of ion implantation for forming the low concentration ion implantation region 4a, it is necessary to implant ions with high energy from above the insulating film 6, so that the mask of the channel portion needs to be made of metal. There is. Therefore, the degree of freedom in design is limited.

Thirdly, the positional variation between the source / drain region and the offset region is limited by the photolithographic accuracy, and the reproducibility of parasitic capacitance and the like is not very good. Fourth,
In the conventional manufacturing method, the reverse stagger type (bottom gate type)
There is a significant increase in the number of processes when manufacturing transistors.

The present invention has been made in view of the above situation, reduces the number of ion implantation steps, and reduces the number of manufacturing steps.
It is an object of the present invention to provide a method for manufacturing a field effect transistor, which has a large degree of freedom in design and can also perform good alignment accuracy between a source / drain region and an offset region.

[0011]

In order to achieve the above object, a method of manufacturing a field effect transistor according to the present invention comprises:
Forming an ion implantation blocking layer on the semiconductor layer; processing the ion implantation blocking layer with a pattern including a channel region and an offset region; and processing at least the drain side end of the ion implantation blocking layer into a tapered shape. And a step of ion-implanting impurities from above the ion-implantation blocking layer to form source / drain regions having offset regions in the semiconductor layer. In the present invention, the “semiconductor layer” is used in a broad sense including a bulk semiconductor substrate.

The ion implantation blocking layer is composed of an insulating film or a resist film. The semiconductor layer is formed on the gate insulating film laminated on the gate electrode (bottom gate structure), and the ion implantation blocking layer is configured to function also as an etching stopper during etching in a later step. be able to.

The ion implantation blocking layer may be removed after the ion implantation process for forming the source / drain regions, and a gate insulating film and a gate electrode may be formed on the semiconductor layer (top gate structure). The step of processing at least the drain side end of the ion implantation blocking layer into a tapered shape can be realized by performing plasma ashing from above the resist film in an atmosphere containing an oxidizing gas.
Alternatively, a resist film having a predetermined pattern is formed on the ion implantation blocking layer with weak adhesion, wet etching is performed on the resist film, and etching is also performed from the interface between the resist film and the ion implantation blocking layer. It can also be realized by advancing.

[0014]

In the method of manufacturing a field effect transistor according to the present invention, at least the drain side end of the ion implantation blocking layer is processed into a taper shape, and impurities are ion implanted from above the ion implantation blocking layer. As a result of the ion implantation, impurity ions are not implanted into the semiconductor layer located below the ion implantation blocking layer other than the tapered portion, and a channel region is formed. In the tapered portion of the ion implantation blocking layer, a certain amount of impurity ions reach the semiconductor layer and are ion-implanted by adjusting the taper angle and the thickness of the ion implantation blocking layer. Therefore, an offset region, which is a low concentration impurity region, is formed in that portion in a self-aligned manner. For the semiconductor layer not covered with the ion implantation blocking layer,
Impurity ions of a predetermined amount are implanted to form source / drain regions of relatively high concentration.

That is, in the method of manufacturing a field effect transistor according to the present invention, the source / drain region and the offset region can be simultaneously formed by one ion implantation. The offset region is formed in self-alignment with the source / drain region, and its width can be easily controlled by the taper angle of the ion implantation blocking layer. Therefore, the alignment accuracy between the source / drain region and the offset region is also improved, and the parasitic capacitance of the transistor can be reduced.

Further, in the present invention, the ion implantation blocking layer can be constituted by other than the metal mask. Furthermore, if the manufacturing method of the present invention is adopted, the manufacturing process does not increase even when manufacturing a bottom gate type field effect transistor.

[0017]

The method for manufacturing a field effect transistor according to the present invention will be described in detail below with reference to the embodiments shown in the drawings. First, the principle of the manufacturing method according to the present invention will be described with reference to FIGS. 1 and 2. For ease of explanation, in the examples shown in FIGS. 1 and 2, only an essential part of the manufacturing process is shown without manufacturing an actual transistor.

First, as shown in FIG.
The semiconductor layer 22 is formed thereon. The substrate 21 is not particularly limited, but when manufacturing a TFT for a liquid crystal display (LCD), for example, a transparent glass substrate is used. When manufacturing SRAM TFTs, etc.,
As the substrate 21, a semiconductor substrate such as single crystal silicon is used.

The semiconductor layer 22 is not particularly limited, but for example, a non-doped polysilicon film, a non-doped amorphous polysilicon film or the like is used. An insulating film or the like may be formed between the semiconductor layer 22 and the substrate 21. After forming the semiconductor layer 22, the ion implantation blocking layer 25 is formed by a thermal oxidation method, a CVD method, or the like. This ion implantation blocking layer 25 is formed by ion implantation in a later step.
It is a layer that functions as an ion blocking layer and is not particularly limited as long as it is a layer having a sufficient film quality as an ion implantation blocking layer, and is composed of, for example, SiO ₂ , SiN _x , SiO _x N _y , a resist, and the like. Sufficient film thickness t to prevent injection
_B (see FIG. 2).

Next, as shown in FIG. 1A, the ion implantation blocking layer 25 is processed by a photolithography process and an etching process so as to have a pattern serving as a mask at the time of ion implantation in a subsequent process, and Both ends are tapered.
This taper shape processing can be performed by either wet etching or dry etching. However, by mixing O _{2 in} the etching gas of the RIE etching apparatus and etching while ashing the resist, it is possible to easily and accurately and reproducibly. A tapered shape can be formed. When the ion implantation blocking layer is composed of a resist,
The taper shape can be achieved by changing the exposure condition and the development condition.

The method of forming the tapered ion implantation blocking layer 25 by wet etching and the method of forming it by dry etching will be described in more detail. When forming by wet etching,
First, an insulating film to be the ion implantation blocking layer 25 is formed on the semiconductor layer 22 to be the channel portion of the transistor by a thermal oxidation method,
A film thickness sufficient to function as ion implantation blocking is formed by using a CVD method, a sputtering method, or the like.

Then, the photoresist film is set to about 1.5 μm.
To form a resist film 26a having a pattern having a size obtained by adding the offset region and the processing margin to the channel length. Next, wet etching is performed, but note the following points in order to obtain a tapered shape. That is, when the wet etching method is used, the taper shape of the ion implantation blocking layer 25 is such that the etchant penetrates between the photoresist film 26 a and the ion implantation blocking layer, and the ion implantation blocking layer 25 has a depth smaller than that of the ion implantation blocking layer 25. The horizontal direction of the interface is possible because the etching is faster. That is, the taper angle is equal to the photoresist film 26a.
Is proportional to the adhesion between the ion implantation blocking layer 25 and the ion implantation blocking layer 25.

In order to obtain an acute taper angle θ (see FIG. 2), the process may be advanced in the direction of weakening the adhesion of the photoresist film 26a. Specifically, the adhesion can be controlled by lowering the post bake temperature of the photoresist film or shortening the post bake time. For example, the taper angle in the conventional wet etching is 70 degrees, while the post bake time (120 ° C.) is about 1/100 of that in the conventional case.
The ion implantation blocking layer 2 having a taper angle θ of 30 to 40 degrees at both ends is formed by etching after setting it to 3 to 1/4.
5 is obtained.

Also, in order to obtain a taper shape, an RIE device
When using, as shown in Fig. 1 (A),
Photoresist with a pattern corresponding to the width of the channel region
After forming the strike film 26b, the resist film 26b is
O₂ Taper in a mixed process gas containing
While singing, the ion implantation blocking layer 25 is tapered.
Touch. That is, the etching of the ion implantation blocking layer 25
Is the etching rate of the photoresist film 26b.
The resist film 26b is etched later than
Under the condition that the underlying semiconductor layer 22 is etched
Plasma etching such as RIE under high rate conditions
Perform As a result, the resist film 26 having a tapered shape
And a tapered ion implantation blocking layer 25 is obtained.
Also, there is no problem in the process. Specifically, ion implantation
The blocking layer is SiN_XIn case of SF₆Is 150 SCCM, He is
150 SCCM, O₂ 50 to 150 SCCM in the chamber
RI under pressure of 20 Pa and RF power of 1200 W
If E is performed, the ion injection with the taper angle θ shown in FIG.
The entry blocking layer 25 is obtained. In this case, the taper angle θ is O₂ 
It can be controlled by setting the partial pressure to an appropriate value.
When the entrance blocking layer 25 is composed of a photoresist film alone
Is O ₂ O in gas only ashing mode₂ Flow rate,
Control taper angle θ by setting pressure and power to appropriate values
it can.

After the ion implantation blocking layer 25 having a tapered end is formed in this manner, as shown in FIG.
The resist 26 is removed, and the high concentration (the dose amount is 10 ¹⁴ to 1
An ion implantation 27 of 0 ₁₆ cm ^-2 ) is performed. As a result, as shown in FIG. 1C, in the semiconductor layer 22, a high-concentration doping region of the impurity ions to be the source / drain regions 23 and a low-concentration doping region of the offset region 24 are formed once. It is formed by driving.

At this time, as shown in FIG. 2, the taper angle θ
Is defined by θ = tan ⁻¹ (t _D / l _OF ). In addition,
In the formula, t _D is the minimum film thickness that the impurity ions cannot pass through the insulating film 25 at the time of ion implantation, and l _OF is the length of the offset region formed by the ion implantation. The depth at which the ions are implanted varies depending on the type of the insulating film 25, but mainly changes depending on the acceleration voltage and the ion species at the time of ion implantation. For example, at an acceleration voltage of 100 KV, B
When implanting (boron) ions, the impurity concentration distribution exhibits a Gaussian distribution in the depth direction. In that case, the peak position of the B ion is about 0.3 μm from the surface, and in order to completely block the B ion, an insulating film having a thickness of about 1.5 μm, which is about 5 times the peak position, is required. And an acceleration voltage of 40 KV requires an insulating film thickness of 0.7 μm, which is about ½ of that. Further, in the case of P (phosphorus) ions, since the mass is larger than that of B, the implantation depth is about 1/3.
Becomes shallower. That is, the film thickness required for the ion implantation blocking layer 25 composed of an insulating film is about 1/3 of B, about 0.5 μm at an acceleration voltage of 100 KV, about 0.3 at 40 KV.
μm, and about 10 μV, it becomes about 0.1 μm. Therefore, the film thickness of the ion implantation blocking layer 25 made of an insulating film may be selected in the range of 0.1 μm to 1.5 μm according to the ion implantation conditions. When the film thickness is too thick, it is better to use a resist film as the ion implantation blocking layer 25 instead of the insulating film.

The impurity ion concentration of the offset region length l _OF shown in FIG. 2 gradually decreases from the beginning of the taper portion of the insulating film 25, and eventually becomes almost zero.
From the Gaussian distribution, the effective area length of the ion concentration that effectively functions as an offset area is 1/2 l _OF to 3/5 l
_{It is OF} . In FIG. 2, l _M is the margin area and l _L is the channel length.

Here, since the offset amount required for the TFT is 0.2 μm to 2.0 μm, if the range of the taper angle θ is 5 ° to 60 °, preferably 20 ° to 60 °,
The required offset amount can be secured by the combination of the ion implantation acceleration voltage and the ion species to be implanted.

Next, based on FIG. 3, the bottom gate type TF is shown.
An example of manufacturing T will be described. First, the gate electrode 31 is formed on the substrate 30. The substrate 30 is not particularly limited, but is a liquid crystal display (LCD) T
When manufacturing FT, a glass substrate is used, for example. Further, when manufacturing a TFT for SRAM or the like, a semiconductor substrate made of single crystal silicon or the like is used as the substrate 30. The gate electrode 31 is not particularly limited, but doped polysilicon, chromium, tantalum, aluminum or the like is used.

Next, the substrate 3 on which the gate electrode 31 is formed
A gate insulating film 32 and a semiconductor layer 33 are formed on the 0. The gate insulating film 32 is composed of, for example, a silicon oxide film formed by a thermal oxidation method, an ONO film which is a laminated film of a silicon oxide film and a silicon nitride film, or the like. The semiconductor layer 33 is composed of, for example, a non-doped polysilicon film. After forming the semiconductor layer 33, an insulating film which is the ion implantation blocking layer 36 is further formed thereon. The insulating film as the ion implantation blocking layer 36 has a structure as shown in FIGS.
Both ends thereof are tapered as in the embodiment shown in FIG. And high concentration (dose amount is 10 ¹⁴ to 10 ¹⁶ c
m ⁻² ) ion implantation 37 is performed. As a result, FIG.
As shown in (B), in the semiconductor layer 33, a high-concentration ion implantation region to be the source / drain region 34 and a low-concentration ion implantation region to be the offset region 35 are simultaneously obtained.

Then, the ion implantation blocking layer 36 formed of an insulating film is left as an etching stopper layer at the time of etching in a later step, and is turned into an island as shown in FIG. 39 is formed, and the transistor is completed. Source / drain electrode 3
In the case of TFTs, reference numerals 8 and 39 are composed of transparent electrodes such as ITO and metal electrodes such as molybdenum and titanium.
This process has almost no process increase.

The drain current characteristic with respect to the gate voltage of the TFT manufactured by the method of this Example (I _D -V _G characteristics) shown in solid line in FIG. 4. As shown in FIG. 4, the TFT obtained by the method of the present embodiment is significantly improved in leak current in the negative gate voltage region (off region) as compared with the TFT according to the comparative example having no offset region. confirmed.

Next, based on FIG. 5, the top gate type TF
An example of manufacturing T will be described. First, as shown in FIG. 5A, the semiconductor layer 41 is formed on the substrate 40. The substrate 40 is not particularly limited, but when manufacturing a TFT for a liquid crystal display (LCD), for example, a transparent glass substrate is used. In addition, T for SRAM
When manufacturing an FT or the like, a semiconductor substrate such as single crystal silicon is used as the substrate 40.

The semiconductor layer 41 is not particularly limited, but for example, a non-doped polysilicon film, a non-doped amorphous polysilicon film or the like is used. An insulating film or the like may be formed between the semiconductor layer 41 and the substrate 40. After forming the semiconductor layer 41, the ion implantation blocking layer 46 is formed by a thermal oxidation method, a CVD method, or the like. The ion implantation blocking layer 46 is formed by ion implantation in a later step.
It is a layer that functions as an ion blocking layer and is not particularly limited as long as it is a layer having a sufficient film quality as an ion implantation blocking layer, and is composed of, for example, SiO ₂ , SiN _x , SiO _x N _y , a resist, and the like. It has a film thickness sufficient to prevent injection.

Next, the ion implantation blocking layer 46 is formed as shown in FIGS.
By a method similar to that of the embodiment shown in, a photolithography process and an etching process are used to form a taper shape. This taper shape processing can be performed by either wet etching or dry etching. However, by mixing O _{2 in} the etching gas of the RIE etching apparatus and etching while ashing the resist, it is possible to easily and accurately and reproducibly. A tapered shape can be formed. Even when the ion implantation blocking layer is made of a resist, the tapered shape can be achieved by changing the exposure condition and the development condition.

Next, using the ion implantation blocking layer 46 as a mask, high-concentration (dose amount: 10 ¹⁴ to 10 ¹⁶ cm ⁻² ) ion implantation 47 is performed. As a result, as shown in FIG. 5B, in the semiconductor layer 41, a high-concentration doping region of impurity ions to be the source / drain regions 43 and a low-concentration doping region to be the offset region 44 are formed by one ion implantation. It is formed by driving.

After that, as shown in FIG. 5B, the ion implantation blocking layer 46 is removed by etching, and then the gate insulating film 42 is formed as shown in FIG. 5C.
The gate insulating film 32 is composed of, for example, a silicon oxide film formed by a thermal oxidation method, an ONO film which is a laminated film of a silicon oxide film and a silicon nitride film, or the like.

Next, after forming contact holes 48 to the source / drain regions 43 in the gate insulating film 42, the gate electrode 45 and the source / drain regions are formed on the gate insulating film 42.
Drain electrodes 46 and 47 are formed to form a top gate type TF
T is completed. The present invention is not limited to the above-mentioned embodiments, but can be modified in various ways within the scope of the present invention.

For example, in the above embodiment, the taper is formed at both ends of the ion implantation blocking layers 25, 36 and 46.
The present invention is not limited to this, and the ion implantation blocking layers 25, 36, and 46 may be formed with a taper only at least on the drain side end. However, it is easier in terms of process to form the taper at both ends of the ion implantation blocking layers 25, 36 and 46.

Further, in the above embodiment, the case of manufacturing a TFT by using the method of the present invention has been described, but the present invention is not limited to this, and source / drain regions are formed on the surface of a semiconductor substrate. It can be similarly applied to a normal MOS transistor. Normal M
This is because even in the OS transistor, it is necessary to form an offset region such as LDD.

[0041]

As described above, according to the present invention, the source / drain region and the offset region can be simultaneously formed by one ion implantation. The offset region is formed in self-alignment with the source / drain region, and its width can be easily controlled by the taper angle of the ion implantation blocking layer. Therefore, the alignment accuracy between the source / drain region and the offset region is also improved, and the parasitic capacitance of the transistor can be reduced.

Further, in the present invention, the ion-implantation blocking layer may be composed of other than a metal mask. Furthermore, if the manufacturing method of the present invention is adopted, the manufacturing process does not increase even when manufacturing a bottom gate type field effect transistor.

[Brief description of drawings]

1A to 1C are schematic cross-sectional views of a method for manufacturing a field effect transistor according to an embodiment of the present invention.

FIG. 2 is a schematic view showing the operation of the manufacturing method shown in FIG.

3A to 3C are schematic cross-sectional views showing a manufacturing process of a bottom gate type TFT according to an embodiment of the present invention.

4 is a TFT I obtained in the embodiment shown in FIG.
It is a diagram illustrating a _D -V _G characteristics.

5A to 5C are schematic cross-sectional views showing a manufacturing process of a top gate type TFT according to another embodiment of the present invention.

6A to 6C are schematic cross-sectional views showing a manufacturing process of a TFT according to a conventional example.

[Explanation of symbols]

 21, 30, 40 ... Substrate 22, 33, 41 ... Semiconductor layer 23, 34, 43 ... Source / drain region 24, 35, 44 ... Offset region 25, 36, 46 ... Ion implantation blocking layer 31, 45 ... Gate electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/266 H01L 21/265 M 9056-4M 29/78 311 G

Claims (6)

[Claims] 1. A step of forming an ion implantation blocking layer on a semiconductor layer, the ion implantation blocking layer being processed into a pattern including a channel region and an offset region, and at least the drain side end portion of the ion implantation blocking layer. A step of processing into a taper shape and a source having an offset region by ion-implanting impurities from above the ion-implantation blocking layer.
And a step of forming a drain region in the semiconductor layer. 2. The method for manufacturing a field effect transistor according to claim 1, wherein the ion implantation blocking layer is composed of a resist film. 3. The semiconductor layer is formed on a gate insulating film laminated on a gate electrode, and the ion implantation blocking layer formed on the semiconductor layer is made of an insulating film.
The method for producing a field effect transistor according to claim 1, wherein the ion implantation blocking layer also functions as an etching stopper during etching in a later step. 4. The ion implantation blocking layer is removed after an ion implantation step for forming source / drain regions, and a gate insulating film and a gate electrode are formed on the semiconductor layer. Of manufacturing a field effect transistor of. 5. The step of tapering at least the drain side end of the ion implantation blocking layer is realized by performing plasma ashing on the resist film in an atmosphere containing an oxidizing gas. 2. The method for manufacturing the field effect transistor according to 2. 6. The step of tapering at least the drain side end portion of the ion implantation blocking layer, a resist film having a predetermined pattern is formed on the ion implantation blocking layer with a weak adhesion, and the resist is formed. The method for producing a field effect transistor according to claim 1, wherein the method is implemented by performing wet etching from above the film and proceeding also from the interface between the resist film and the ion implantation blocking layer.