JPH03142418A - Image display device and production thereof - Google Patents

Image display device and production thereof

Info

Publication number
JPH03142418A
JPH03142418A JP28210889A JP28210889A JPH03142418A JP H03142418 A JPH03142418 A JP H03142418A JP 28210889 A JP28210889 A JP 28210889A JP 28210889 A JP28210889 A JP 28210889A JP H03142418 A JPH03142418 A JP H03142418A
Authority
JP
Japan
Prior art keywords
formed
regions
form
film
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28210889A
Inventor
Fumiaki Emoto
Eiji Fujii
Akira Nakamura
Koji Senda
Yasuhiro Uemoto
Atsuya Yamamoto
Original Assignee
Matsushita Electron Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electron Corp filed Critical Matsushita Electron Corp
Priority to JP28210889A priority Critical patent/JPH03142418A/en
Publication of JPH03142418A publication Critical patent/JPH03142418A/en
Application status is Pending legal-status Critical

Links

Abstract

PURPOSE: To obtain the display device having high reproducibility by constituting the drain and source regions of MOS transistors of two kinds of regions which vary in impurity concn., and setting the impurity concn. of the region near the gate lower than the concn. of the region far from the gate.
CONSTITUTION: A polysilicon film is formed on a substrate 21 and is patterned to form the TR regions 20 and is thermally oxidized in a dry O2 atmosphere to form an Si oxide film, on which a polysilicon film is formed and is added with an impurity by P diffusion to an n+ type. Gate electrodes 27 and gate oxide films 26 are then formed and P is ion-implanted over the entire surface to form the laser regions 23 and train regions 24 of an n- type. An Si oxide film 28 is formed over the entire surface and is etched to allow side wall spacers 28 to remain in the side face parts of the gate electrodes. As is ion-implanted over the entire surface with the spacers 28 and the gate electrodes 27 as a mask to form the source regions 22 and drain regions 25 of the n+ type. The Si oxide film is formed as an interlayer insulating film. An Al-Si film is formed by sputtering to form signal lines 30. An SiN film is formed and a liquid crystal 32, a common electrode 33 and an upper glass plate 34 are formed.
COPYRIGHT: (C)1991,JPO&Japio
JP28210889A 1989-10-30 1989-10-30 Image display device and production thereof Pending JPH03142418A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28210889A JPH03142418A (en) 1989-10-30 1989-10-30 Image display device and production thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28210889A JPH03142418A (en) 1989-10-30 1989-10-30 Image display device and production thereof

Publications (1)

Publication Number Publication Date
JPH03142418A true JPH03142418A (en) 1991-06-18

Family

ID=17648230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28210889A Pending JPH03142418A (en) 1989-10-30 1989-10-30 Image display device and production thereof

Country Status (1)

Country Link
JP (1) JPH03142418A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5362671A (en) * 1990-12-31 1994-11-08 Kopin Corporation Method of fabricating single crystal silicon arrayed devices for display panels
JPH07218932A (en) * 1993-09-20 1995-08-18 Semiconductor Energy Lab Co Ltd Semiconductor device and its production
US6049092A (en) * 1993-09-20 2000-04-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US6566684B1 (en) 1994-06-13 2003-05-20 Semiconductor Energy Laboratory Co., Ltd. Active matrix circuit having a TFT with pixel electrode as auxiliary capacitor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5362671A (en) * 1990-12-31 1994-11-08 Kopin Corporation Method of fabricating single crystal silicon arrayed devices for display panels
JPH07218932A (en) * 1993-09-20 1995-08-18 Semiconductor Energy Lab Co Ltd Semiconductor device and its production
US6049092A (en) * 1993-09-20 2000-04-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
US6566684B1 (en) 1994-06-13 2003-05-20 Semiconductor Energy Laboratory Co., Ltd. Active matrix circuit having a TFT with pixel electrode as auxiliary capacitor
US7161178B2 (en) 1994-06-13 2007-01-09 Semiconductor Energy Laboratory Co., Ltd. Display device having a pixel electrode through a second interlayer contact hole in a wider first contact hole formed over an active region of display switch
US7479657B2 (en) 1994-06-13 2009-01-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device including active matrix circuit

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