JPS6281763A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to perform highly accurate position alignment and to suppress dispersion in threshold voltage of an MOSFET, by forming a high concentration impurity layer at the center between a source and a drain by a self-aligning method. CONSTITUTION:On a silicon substrate 1, a Cr film 10 is deposited. A resist gate pattern 11 is formed. Etching of the Cr film 10 is performed to the surface of the substrate 10. Over-etching of 200% is carried out in the lateral direction, and the Cr film is side-etched. A thin Cr wire 10 is formed at the center of the lower surface of the resist pattern 11. Thereafter, with the resist gate pattern 11 as a mask, as ions are implanted in the silicon substrate 1. A source region 4 and a drain region 5 are formed. The resist gate pattern 11 is removed, and annealing is performed. An SiO2 film 12 is deposited, and the surface is flattened. Back etching is performed until the surface of the thin Cr wire 10 is exposed. The thin Cr wire 10 is removed, and a minute hole 13 is formed in the SiO2 film 12. B ions are implanted through a hole 14, and a high concentration impurity layer 6 is formed.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a novel MO8IE field effect transistor (hereinafter referred to as
MOSFET) and a MOS integrated circuit (hereinafter referred to as MOSFET) consisting of a plurality of MOSFETs.

The present invention relates to a manufacturing method for MOSLSI (referred to as MOSLSI), and particularly to a manufacturing method suitable for MOSFET and MOSLSI having a minute channel length.

[Background of the invention]

One of the important performances of MOSFET is the gain constant β of the transistor. These are field effect mobility μFE, gate oxide film capacitance COX, channel width W a t f, and channel length. ff is generally expressed by the following formula, β=μFt
coxWeff/ Leff +・・・・・・(1
) The larger this value is, the faster the switching operation becomes possible.

Therefore, in order to increase the gain constant β and improve the performance of the MOSFET, μ
Increase FE, Cox, and Weff, and L
It can be seen that it is sufficient to reduce eff.

μFE depends on the impurity concentration in the channel region, and also due to the CO
X is determined depending on the thickness of the gate oxide film. Therefore, in order to increase β, Leff must be decreased and welf must be increased. These. Both ff and Weff are structural constants of the MOSFET, and are determined by design. Therefore, in order to improve device performance, it is necessary to change the design of the conventional MOSFET structure itself.

By the way, FIG. 4 is a diagram showing the main part structure of a conventional general MOSFET, in which 1 is a p-type Si substrate, 2 is a gate oxide film formed by thermal oxidation, etc., and 3 is a polyurethane film containing, for example, P. Gate electrodes 4 and 5 made of crystalline SL are a source and a drain formed by dry impurity diffusion or impurity ion implantation using gate oxide film 2 and gate electrode 3 as masks, respectively, and subsequent thermal annealing. In a MOSFET with this structure, Lef of the structure constants is
As shown in the figure, f is the channel length defined by the distance between the source 4 and the drain 5, and the gate length is L9. source 4
Letting the lateral extent of both the drain and drain impurity regions be X, it is expressed as Laff=L5 2Xa . . . -(2).

That is, it can be seen that the channel length Laff, which is an important parameter that determines the performance of the MOSFET, is determined by two parameters: the processing of the gate electrode and the lateral diffusion. Therefore, when trying to obtain a MOSFET with a certain performance, the required Laff is limited by the processing level of the gate electrode and the lateral extent of the impurity diffusion region, so the size of the element is naturally determined. As a result, it is important to achieve further miniaturization and higher integration of elements while maintaining this performance.
This was not possible with SFET.

A MOSFET that solves these problems was developed in Japanese Patent Application Laid-open No. 1983.
This is proposed in the publication No.-61965.

This is achieved by partially introducing impurities into the channel portion of the MOSFET at a high concentration using a focused ion beam, thereby shortening the effective channel length Laff and achieving high gain, regardless of the above parameters. The purpose is to obtain a MOSFET with a constant β.

FIG. 5 is a sectional view showing a typical example of the configuration of the main parts of the above MOSFET. For example, a focused ion beam is used between the source 4 and drain 5, which are made of an As diffusion layer provided in the p-type Si substrate 1, to form a highly concentrated impurity layer (in this case, for example, A high-concentration B implantation layer) 6 is added. By adding this high-concentration impurity layer 6, the channel length Laff becomes substantially equal to the width of the high-concentration impurity layer 6, so that the channel length Leff is much longer than the gate length L9 described above. Can be shortened. The reason for this is that conventional gate processing,
This is because, instead of determining the channel length by lateral diffusion of the source and drain, by scanning a focused ion beam with a diameter of 0.17 m or less, an impurity concentration region with a minute width of 0.1-width can be controlled.

However, when we experimentally investigated the dependence of the threshold voltage Vth, which is an important factor in the performance of a MOSFET, on the position of the highly concentrated impurity layer using the focused ion beam, we obtained the results shown in FIG. The experiment was conducted at an accelerating voltage of 20 K e V.
A focused B ion beam with an ion beam diameter of 0.2 is connected to a MOSFET with a gate oxide film thickness of 20 nm, Le, ff O, 84
This was done by scanning the channel region. According to Figure 3,
It can be seen that when the scanning position of the focused ion beam fluctuates by ±0.151M or more, the threshold voltage V th fluctuates by ±0.1V or more. However, in view of the positioning method of the focused ion beam, deflection distortion when scanning the ion beam, etc., it is extremely difficult to control the scanning position fluctuation of the focused ion beam within ±0.15 cape. As a result, the variation in the threshold voltage V th of the device is actually ±0.
It reached as high as 3V.

As mentioned above, the MOSFET with the new structure shown in Figure 5 overcomes the drawback that the characteristics of the conventional MOSFET with the general structure shown in Figure 4 are determined by the structural constants. I can do it.

Although high performance and high integration are possible, there is a problem that it is difficult to control variations in the threshold voltage V th of the MOSFET, which is a fatal problem in constructing MO8LSI.

[Purpose of the invention]

An object of the present invention is to provide a method for manufacturing a semiconductor device that can easily manufacture and realize a high-performance MOSFET that suppresses variations in the threshold voltage Vth of the conventional MOSFET having the structure shown in FIG. It is about providing.

[Summary of the invention]

In order to achieve the above object, the method for manufacturing a semiconductor device of the present invention provides a highly concentrated impurity layer 6 with a fine width to be formed in the channel region of a MOSFET having the structure shown in FIG.
is formed in a self-aligned manner at the center between the source 4 and drain 5 using side etching technology and ion implantation technology.

A detailed explanation will be given below with reference to the drawings.

FIG. 1 is a diagram showing a typical example of the main process configuration of the method for manufacturing a semiconductor device according to the present invention. Hereinafter, the method for manufacturing a semiconductor device of the present invention will be explained step by step with reference to FIG.

In FIG. 1(a), a conductive or insulating film 7 is deposited on a silicon substrate 1, and MOS
A state in which a pattern corresponding to the gate portion of the FET is formed as a first mask film 8 using a material that can be used as a mask for ion implantation to be performed in a later step is shown.

Next, as shown in FIG. 1(b), the conductor or insulator film 7 is etched using anisotropic dry etching, and a predetermined width is etched only under the center of the lower surface of the first mask film 8. Side etching is performed until the coating 7 remains.

Thereafter, as shown in FIG. 1C, ions of a conductivity type opposite to that of the substrate 1 are implanted using the first mask film 8 as a mask to form a source region 4 and a drain region 5 in the substrate 1.

Next, after removing the first mask film 8, a second mask film 9 that can serve as a mask for ion implantation in a later step is deposited, and this is etched and planarized to form the conductor or insulator film 7. Figure 1 shows the exposed top surface of the
d).

Thereafter, as shown in FIG. 1(e), the conductor or insulator layer 7 is removed and an opening 13 is formed in the second mask film 9. Said substrate 1
Then, ions of the same conductivity type as the substrate are implanted to form a high concentration impurity layer 6 in the substrate 1 below the opening 13.

Finally, the state in which the second mask film 9 on the silicon substrate 1 is removed is shown in FIG. 1(f). A semiconductor device according to the present invention can be obtained by forming a gate oxide film, a gate electrode, a source electrode, a drain electrode, etc. thereon.

According to the present invention described above, the high-performance MO shown in FIG.
In manufacturing the 8FET, the high concentration impurity layer 6 is used as the source 4.
It is possible to form it in a self-aligned manner at the center of the drain 5 and the drain 5. As a result, it is possible to achieve highly accurate alignment between the source 4 and drain 5 of the highly concentrated impurity layer 6, which was difficult to achieve with conventional manufacturing methods using focused ion beams.
The threshold voltage Vth of MOSFET was a problem in the past.
It is possible to sufficiently control the variation in , making it possible to apply it to the manufacture of MOSFETs.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail with reference to Examples.

Embodiment 1 FIG. 2 is a diagram showing an embodiment of the method for manufacturing a semiconductor device of the present invention, and each step will be explained in order.

In FIG. 2(a), a Cr film 10 with a thickness of 500 nm is deposited on a p-type, (100) plane, 10ΩG silicon substrate 1.
Furthermore, after applying a negative resist RD-200ON (trade name of Hitachi Chemical Co., Ltd.) to a thickness of 0.5 mm, a resist gate pattern 11 with a gate length of 0.3 mm was formed by electron beam lithography. It shows.

Next, as shown in FIG. 2(b), the Cr film 10 is etched to the surface of the substrate 1 by anisotropic dry etching, and the Cr film is etched on the side by over-etching by 200% in the lateral direction. Etching is performed to form a thin Cr line 10 with a line width of 0.1 um at the center of the lower surface of the resist gate pattern 11.

Thereafter, using the resist gate pattern 11 as a mask, As ions are applied to the silicon substrate 1 at an acceleration voltage of 50 KeV.
, the implantation amount is 2×10"am-" (7), and the double-headed region of the source 4 and drain 5 is formed, as shown in FIG. 2(Q).

Next, as shown in FIG. 2(d), after removing the resist gate pattern 11 and performing annealing at 900° C. for 30 minutes, a bias sputtering method is used to deposit Sio to a uniform thickness.
The surface is flattened by stacking two films and one film, and the entire surface is back-etched by dry etching until the surface of the thin Cr wire 10 is exposed.

Next, as shown in FIG. 2(e), the Cr thin wire 10 is etched and removed using mixed acid 5N2 (trade name of Kanto Kagaku Co., Ltd.), and a minute opening 13 with a film width of 2.14 mm is formed in the SiO□ film 12. Form. Subsequently, B ions are implanted into the silicon substrate 1 through the opening 14 at an acceleration voltage of 40 KeV and an implantation amount of 8×10.
”■-2 conditions, driving width 0.1, -depth 0.15
A high concentration impurity layer 6 of 7ffi is formed.

Finally, after removing the 5in2 film 12, a gate oxide film 2 with a thickness of 20 ni is grown by dry oxidation, a polycrystalline silicon film 3 of the gate electrode material is deposited to a thickness of 0.3 - After introducing the MOSFET, gate processing is performed using photolithography or electron beam phosphorography.
FIG. 2(f) shows the completed ET.

Threshold voltage Vth of MOSFET completed in the above process
The variation in can be kept within the range of ±0.05V from the set value of 0.5V, and compared to the conventional manufacturing method using a focused ion beam, the variation is 1
It became /6. Furthermore, the gain constant is approximately twice as high and the drain breakdown voltage is approximately 1.5 times as high as that of a conventionally structured MCSFET without a high-concentration impurity layer. MOS with the structure shown in Figure 5
It turns out that the characteristics of FETs are not obvious.

Embodiment 2 FIG. 3 is a diagram showing another embodiment of the present invention, and each step will be explained in order.

First, p-type, (100) plane, 10Ω■ silicon substrate 1
A gate oxide film 2 with a thickness of 20 nm is grown on the surface of the gate electrode by dry oxidation at 1000° C. for 20 minutes, and a polycrystalline Si film 3 of 0.31 M as the gate electrode material is deposited thereon. niPOCI! P is diffused using 3 as a diffusion source. Thereafter, a Cr film 10 with a thickness of 500 layers was deposited, and the Cr film 10 was deposited.
FIG. 3(a) shows a state in which a resist pattern 11 having a width of 0.37ffi corresponding to the gate length is formed on the film 10 by electron beam phosphorography.

Next, as shown in FIG. 3(b), in the same process as in Example 1, the base Cr film 10 is etched by anisotropic dry etching using the resist pattern 11 as a mask, and further over-etched by 200%. By performing this, a line width of 0.
1- Cr thin wire 10 is formed.

Next, using the resist pattern 11 as a mask, the base polycrystalline Si film 3 and gate oxide film 2 are processed into the same shape as the resist pattern 11 by anisotropic dry etching to expose the surface of the substrate 1, and then the entire surface is etched. As ions were accelerated at an acceleration voltage of 50 KeV and an implantation amount of 2 x 10”a.
Figure 3(c) shows the state in which the source 4 and drain 5 regions are formed in the silicon substrate 1 by implantation under pr-2 conditions.
Shown below.

Next, in FIG. 3(d), the resist pattern 11 is removed, annealed at 900° C. for 30 minutes, and then a SiO□ film 12 is deposited to a thickness of one inch over the entire surface by bias sputtering. The surface is flattened and the S
i The state in which the O2 film 12 has been back-etched is shown.

Next, as shown in FIG. 3(e), the Cr thin wire 10 is etched away using mixed acid 5N2 (manufactured by Kanto Kagaku Co., Ltd.), and S
in, width 0. A micro opening 13 of the IIM is formed, and subsequently, the silicon substrate 1 is inserted through the opening 13.
B ions were accelerated at a voltage of 150 KeV and an implantation amount of 8
A high concentration impurity region 6 is formed in the substrate 1 by implantation under the implantation condition of 10''arr-''.

Finally, the SiO2 film 12 is removed, and the completed MOSFET is shown in FIG. 6(f).

Example 1 regarding the MOSFET completed in the above steps
Results were obtained regarding the variation in threshold voltage vth, gate constant, drain breakdown voltage, etc., which were comparable to those obtained in the case of .

〔Effect of the invention〕

As shown in the above embodiments, according to the present invention, a MOS
In the channel part of the FET, a highly concentrated impurity layer can be formed in a self-aligned manner at the center between the source and drain.
High-precision alignment, which was difficult with conventional ion implantation using focused ion beams, has become possible. As a result, M.O.
By suppressing the variation in the threshold voltage Vth of the SFET to a level that can withstand practical use, it has become possible to realize the inherent high performance of the MO8FET of this structure. Therefore, compared to the conventional method, it is possible to increase the density of MO5LSH and improve the reliability of the cavity, so the technical effects thereof are very large.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the concept of the method for manufacturing a semiconductor device of the present invention, FIGS. 2 and 3 are process diagrams showing an embodiment of the present invention,
Figure 4 is an explanatory diagram of the main part structure of a conventional general MO8FET,
Figure 5 shows a conventional high-performance MO8FET that is the object of the present invention.
FIG. 6 is a cross-sectional view showing a typical example of the main structure of the MOSFET, and FIG. 6 is a diagram for explaining the problems of the MOSFET having the structure shown in FIG. In the figure, 110. Substrate 2... Gate oxide film 3...
...Gate electrode 4...Source 5...Train 6...High concentration impurity layer 7...Conductor or insulator film 8.9...Ion implantation mask material layer 10...Chromium film 11...Resist pattern 12...
・Silicon oxide film

Claims (1)

[Claims] (1) forming source and drain regions by ion-implanting impurities of a conductivity type opposite to that of the substrate crystal into a predetermined region of a semiconductor substrate of at least one conductivity type, and forming the source and drain regions into a channel region between the source and drain regions; and providing an impurity region that does not contact the drain region, has the same conductivity type as the substrate crystal, and has at least a higher concentration than the substrate crystal, wherein the source and drain regions of the substrate forming a first mask film to be formed in the next step on the surface of the region and a first film made of a material that can be selectively etched with respect to the substrate; and on the first film. forming a first mask film made of a material that can serve as a mask for ion implantation on a region corresponding to the gate of the ion implantation; Etching is performed in the thickness direction and side etching is further performed in the lateral direction, so that the first mask film having a predetermined width is etched only in the center under the first mask film.
a step of leaving a film on the substrate, a step of performing ion implantation on the entire surface of the substrate region including at least the first mask film to form source and drain regions, and a step of removing the first mask film and then performing ion implantation. On the other hand, a second mask film made of a material that can be used as a mask and capable of selectively etching the first film covers an area of the substrate other than the first film remaining on the substrate. a step of removing the first film and providing an opening in the second mask film; and performing ion implantation on the entire surface of the second mask film including at least the opening, and forming an opening in the second mask film. forming the high concentration impurity layer in the substrate through the substrate.