JPH06236896A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To manufacture an asymmetrical FET high in accuracy and reproducibility through a self-aligning technique. CONSTITUTION:An acting layer 2 is formed on a semiconductor substrate 1, and a metal layer 3 and an auxiliary film layer 4 are laminated thereon. Then, the layers 4 and 3 on a drain forming region 6 are removed, a first insulating film 5 formed of material which can be selectively removed keeping the layer 4 left unremoved is formed on all the surface of the substrate 1, the insulating film 5 is anisotropically etched back, whereby a film 5a is left only on the side walls of the residual layers 3 and 4, and ions are implanted into the substrate 1 using the films 5a and 4 as a mask to form a drain region 6. Then, a second insulating layer 7 is formed on all the surface of the substrate 1, the second insulating layer 7 is etched back, the layer 3 is etched back using a side wall as a mask, and ions are implanted to form a source region, and a source electrode and a drain electrode are built.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art A Schottky junction field effect transistor (hereinafter MESFET) using a semi-insulating GaAs substrate.
Because of the high electron mobility of GaAs,
It is drawing attention as a basic element of GaAs ICs and LSIs that enables ultra-high-speed operation that cannot be achieved with integrated circuits using silicon substrates.

In order to improve the performance of such a GaAs field effect transistor, the following four items are required.

By shortening the gate length, the gate capacitance Cg is reduced and at the same time the current driving force Gm is improved.

The feedback capacitance Cgd between the input gate and the output drain is reduced.

The series resistance Rs between the gate and the source is reduced.

A breakdown voltage between the gate and the drain is ensured.

Field effect transistors (hereinafter referred to as FETs) having an asymmetric structure are known to satisfy these requirements. A cross section of this FET is shown in FIG. As shown in FIG. 9, this structure has an LDD layer 84 (Lightly Dope) having a concentration intermediate between the carrier concentration of the operating layer 82 and the carrier concentration of the source / drain regions 85a and 85b.
d Drain) only between the gate and the source, not between the gate and the drain. Thus, the resistance between the gate and the source is reduced, the capacitance between the gate and the drain is reduced, and the breakdown voltage between the gate and the drain is secured.
A well-known manufacturing method of an FET having this structure will be described with reference to FIG.

First, as shown in FIG. 10 (a), an n ^-- type layer 82 to be an FET operation layer is formed on the surface of a semi-insulating GaAs substrate 81 by a selective ion implantation method.
The thickness of the gate metal made of tungsten nitride (WN) is 5
The gate electrode 83 is formed by depositing it to have a thickness of 00 nm and performing etching.

Then, as shown in FIG. 10B, a resist pattern 8 having an opening only in the portion corresponding to the source region is formed, and Si is ion-implanted by using this as a mask, whereby the intermediate concentration layer 84 is formed. To form. At this time, the region serving as the drain of the FET is formed by the photoresist 8
Ion implantation is performed by masking with 8.

Next, as shown in FIG. 10C, the resist pattern 88 is removed, and, for example, a plasma CVD method silicon oxide film is deposited, and then reactive ion etching (R) is performed.
By anisotropic etching such as IE), the silicon oxide film 87 is left only on the side wall of the gate electrode by etching in the vertical direction by the amount corresponding to the film thickness.

Subsequently, as shown in FIG. 10D, a resist pattern 89 is formed and Si ions are ion-implanted using the resist pattern 89 as a mask to form a source region 85a and a drain region 85b.

Then, as shown in FIG. 10 (e), after removing the resist pattern 89, annealing for activating the ion implantation layer is performed, and finally, a source electrode 86a and a drain electrode 86b made of AuGe alloy are formed. Thus, the FET is completed.

In such a conventional manufacturing method, as shown in FIG. 10B, a resist mask 88 is used as a means for forming the intermediate concentration layer 84 only on the source side. That is, it is necessary to form the pattern edge of this resist on the gate electrode 83. In recent years, it has become possible to reduce the pattern conversion difference by improving the alignment accuracy of the exposure apparatus and the performance of the photoresist. However, it is difficult to say that it has sufficient reproducibility in consideration of variations in the resist mask manufacturing process.
Further, if the gate length is shortened, it becomes difficult to form a resist pattern edge on the gate. Generally, a self-aligned structure is often used in order to position a fine structure with high accuracy, and a method of forming the above-mentioned asymmetric structure by a self-aligned process is known (M. Muraguchi et al. 1986 SSDM c-7-1 pp379-382 So
lid State Device and Materials).

However, in the method of forming by this self-alignment process, the direction of the source / drain on the wafer is determined because the shadowing effect due to the implantation angle at the time of ion implantation is utilized.

On the other hand, in the multi-finger type FET, the area is reduced by repeating the source, the gate, the drain, the gate, the source, ... That is, the FET pattern is reflected. Therefore, it is difficult to reduce the area of the multi-finger type FET by the method utilizing the shadowing effect depending on the ion implantation angle.

[0017]

As described above, according to the conventional technique, it is difficult to manufacture an asymmetrical FET by a highly accurate and highly reproducible method. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a method of manufacturing a semiconductor device capable of manufacturing an asymmetrical FET with high accuracy and high reproducibility using a self-alignment technique.

[0018]

A method of manufacturing a semiconductor device according to a first aspect of the present invention comprises a step of forming an operating layer on a semiconductor substrate, a metal layer and a material which can be selectively removed from the metal layer. A step of laminating an auxiliary film layer formed on the drain formation region, a step of removing the auxiliary film layer and the metal layer on the drain formation region, and Forming on the entire surface of the substrate,
Etching back the first insulating film using anisotropic etching to leave the first insulating film only on the sidewalls of the remaining metal layer and auxiliary film layer;
Forming a drain region by implanting ions into the substrate using the remaining first insulating film and the auxiliary film as a mask; selectively removing only the auxiliary film; Forming a second insulating layer on the first insulating layer and etching back the second insulating layer using anisotropic etching to form the second insulating layer only on the side wall of the first insulating layer. A step of leaving it, a step of etching back the metal layer by anisotropic etching using the left second insulating layer as a mask, a step of forming a source region by ion implantation, and a source And a step of forming a drain electrode.

According to the method of manufacturing a semiconductor device of the second invention, a step of forming an operation layer on a semiconductor substrate,
Forming a first insulating film layer on a region of the operating layer where a drain is formed; forming a gate electrode made of a metal material on a sidewall of the first insulating film;
Forming a second insulating film so as to cover the gate electrode and the operating layer after removing the insulating film of 1), and forming a high concentration source / drain region on the surface of the substrate by ion implantation And a step of removing the second insulating film and a step of forming a source electrode and a drain electrode.

According to the method of manufacturing a semiconductor device of the third invention, a step of forming an operation layer on a semiconductor substrate,
Forming a first insulating film layer on a region of the operating layer where a drain is formed; forming a gate electrode made of a metal material on a sidewall of the first insulating film;
The step of forming a second insulating film so as to cover the gate electrode and the operating layer after removing the insulating film, and by etching back the second insulating film using anisotropic etching. A step of leaving the second insulating film only on the side wall of the gate electrode on the drain side; a step of forming a high concentration source / drain region on the surface of the substrate by ion implantation; And a step of forming a source electrode and a drain electrode after removing the second insulating film.

According to the method of manufacturing a semiconductor device of the fourth invention, a step of forming an operation layer on a semiconductor substrate,
A step of forming a first insulating film on the operating layer, a step of applying a photoresist on the first insulating film and patterning the photoresist to remove the photoresist on the gate formation region, and the patterning Removing the first insulating film on the gate formation region by using the formed photoresist as a mask, and depositing an insulating material in a direction that forms a predetermined angle with respect to the normal line of the substrate and from the gate length direction. A step of forming a second insulating layer on the gate region, and then vapor-depositing a metal to form a gate electrode in the same manner, and removing the photoresist, and then applying the photoresist again. Forming a mask for forming an intermediate concentration layer by patterning the first insulating film; and forming an intermediate concentration layer by implanting ions. And a step of forming a second insulating film on the substrate after removing the photoresist, and a step of etching back the second insulating film using anisotropic etching to form the gate electrode of the gate electrode. The step of leaving the second insulating film only on the side wall, the step of forming a source / drain high-concentration region by ion implantation after forming the resist pattern, and the step of removing the resist pattern and then the source electrode and And a step of forming a drain electrode.

[0022]

According to the first to fourth aspects of the invention configured as described above, the F having the asymmetric drain offset structure is formed.
It becomes possible to manufacture ET in a self-aligned manner. Therefore, even if the gate length is shortened for high performance, it can be manufactured with high accuracy and reproducibility.

According to the first to third aspects of the invention configured as described above, multi-finger type FETs, that is, source / gate / drain, gate / source ... it can.

Further, according to the fourth aspect of the invention configured as described above, since it is not necessary to align the pattern edge of the resist on the gate, which is an essential technique for the asymmetrical FET structure, it is possible to suppress the process variation. Reproducibility can be improved.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a method of manufacturing a semiconductor device according to the first invention will be described with reference to FIGS. First, Si ions are ion-implanted into the semi-insulating GaAs substrate 1 under the conditions of an accelerating voltage of 50 KeV and a dose amount of 2.5 × 10 ¹² cm ⁻² by using a selective ion implantation method to form an n-type operating layer 2. (See FIG. 1 (a)). After that, a metal film 3 (for example, a WN film) to be a gate electrode is deposited on the entire surface of the substrate 1 by about 500 nm by using, for example, a sputtering method. Subsequently, a film 4 made of, for example, SiO _{2 which} can be selectively removed by etching with respect to the metal film 3 is deposited to a thickness of, for example, 600 nm (see FIG. 1A). Next, the SiO ₂ film 4 and the metal film 3
The portion corresponding to the drain region is selectively removed by RIE (see FIG. 1B). afterwards,
A material that can be selectively removed from the SiO ₂ film 4, such as SiN
The film 5 made of x is formed to a thickness of about 400n by the plasma CVD method.
m (see FIG. 1B). The thickness of the SiNx film 5 is an important parameter that determines the distance between the gate electrode and the drain region, and the desired drain breakdown voltage and FET
The film thickness may be changed according to the characteristics.

Next, the entire surface of the substrate 1 is anisotropically etched, for example, the RIE method is used to etch the SiNx film 5,
The SiNx film 5a is left only on the edge sidewalls of the metal film 3 and the SiO ₂ film 4 which are previously etched (see FIG. 1C). At this time, the lateral film thickness of the SiNx film 5a slightly recedes to about 300 nm. Then, Si ions are applied to the region which will be the drain of the FET at an acceleration voltage of 120 Ke.
Ion implantation is performed under the conditions of V and a dose amount of 3 × 10 ¹³ cm ^-2 .
Then, the drain region 6 offset from the gate electrode by the film thickness of the SiNx film 5a can be formed in a self-aligned manner (see FIG. 1C). Next, as shown in FIG. 1D, only the SiO ₂ film 4 is removed by etching using, for example, an aqueous solution of hydrogen fluoride. After that, the SiO ₂ film 7 is deposited to a thickness of 300 nm on the entire surface of the substrate 1 by using, for example, the CVD method (see FIG. 1D). The thickness of the SiO ₂ film 7 is FE.
Since it is a parameter for determining the gate length of T, the film thickness may be changed according to the desired gate length. continue,
By anisotropically etching the SiO ₂ film 7, Si
The SiO ₂ film 7a is left only on the side wall of the Nx film 5a (see FIG. 2A). Then, using the remaining SiO ₂ film 7a as a mask, the metal film 3 is etched and processed into the shape of the gate electrode (see FIG. 2A). The gate length at this time is determined by the thickness of the SiO ₂ film 7a, and is 200 nm (0.2
μm). In general, the control of the film thickness in the direction perpendicular to the substrate 1 can be performed more precisely than the photolithography in which the dimension in the lateral direction is controlled, which is advantageous for miniaturization.

Next, as shown in FIG. 2A, a photoresist 8 is applied to the entire surface of the substrate 1, and then the photoresist 8 is patterned to remove the photoresist on the element region. Thereafter, the patterned photoresist 8, the SiNx film 5a, and the SiO ₂ film 7a are used as a mask to apply Si ions to the substrate 1 at an acceleration voltage of 50 Ke.
Ion implantation is performed under the conditions of V and a dose amount of 1 × 10 ¹³ cm ^-2 to form an LDD (Lightly Doped Drain) layer 9 on the source side (see FIG. 2A). At this time, the concentration of the LDD layer 9 becomes an intermediate value between the concentration of the n-type operating layer 2 and the concentration of the n ⁺ layer 12 described later. At this time, Si ions were also implanted into the drain side, but this was not a problem in terms of characteristics.

Next, after removing the photoresist 8, an insulating film, for example, a SiO ₂ film 10 is deposited on the entire surface of the substrate 1 (see FIG. 2B), and this insulating film 10 is anisotropically etched. Etching is performed to leave the insulating film 10a on the source side wall of the gate electrode (FIG. 2).
(See (c)). At this time, the insulating film 10a is also left on the side wall of the gate electrode on the drain side. Subsequently, the photoresist 11 is applied to the entire surface of the substrate 1 and patterned to remove the photoresist on the element region (see FIG. 2C). Using the patterned photoresist 11 and insulating film 10a as a mask, S
i-ion, acceleration voltage 120 KeV, dose 3 × 10
Ion implantation is performed at ¹³ cm ^-2 , and a high concentration n-type layer (n
⁺ Layer) 12 is formed (see FIG. 2C). Then, after removing the photoresist 11, a heat treatment is performed at 800 ° C. in an AsH ₃ atmosphere to activate the implanted Si ions. After that, as shown in FIG.
A source electrode 13a and a drain electrode 13b made of a material whose main component is uGe are formed.

As a result, a multi-finger (two) type drain offset asymmetric GaAs MESFET is completed. In the FET thus formed, the drain is arranged offset, so that the feedback capacitance Cgd between the gate and the drain is small, and the presence of the intermediate layer 9 causes the series resistance Rs between the source and the gate to be small and high. It was performance. Further, the withstand voltage between the gate and the drain was improved and about 10 V could be secured.

As described above, according to this embodiment, a high performance FET can be manufactured with high reproducibility by a self-aligning process. In addition, even when a fine gate electrode, for example, a gate electrode width is 0.2 μm or less,
Since alignment by photolithography or the like is not required, the manufacturing can be performed with high yield. Further, when this embodiment is applied to manufacture of a multi-finger type FET,
The FET can be arranged in a suitable direction, and the area is not increased.

In the above embodiment, the FET is LD
Although the case where the FET has the D structure has been described, the FET does not have to have the LDD structure, and in this case, the deposition of the insulating film 10 is not necessary.

Next, FIG. 3 shows a sectional structure of a multi-finger type GaAs MESFET manufactured by the manufacturing method of the second invention. In FIG. 3, each FET has a so-called asymmetric structure in which an intermediate concentration layer 24 is present between the source region 25a and the gate electrode 23 and no intermediate concentration layer is present in the drain region 25b. Reference numeral 21 is, for example, a semi-insulating GaAs substrate having a resistivity of 10 ⁷ to 10 ⁸ Ω · cm, an n-type operating layer 22 serving as a channel region is formed on the surface portion thereof, and the surface of the operating layer 22 is For example, the Schottky gate electrode 23 made of a WN film is formed. A drain region 25b is formed at a position offset from the gate electrode 23, and a source region 25a is formed.
An intermediate concentration layer 24 is formed between the gate electrode 23 and the gate electrode 23.

Next, a first embodiment of a method of manufacturing a semiconductor device according to the second invention will be described with reference to FIG. First, Si ions are selectively ion-implanted into the semi-insulating GaAs substrate 21 under the conditions of an acceleration voltage of 50 KeV and a dose amount of 3 × 10 ¹² cm ^-2 to form an n-type operating layer 22 (FIG. 4).
(See (a)). Next, an insulating film 28 made of, for example, SiO ₂ and having a predetermined width is formed on the operating layer 22 (FIG. 4B).
reference). After that, for example, WN is deposited with a thickness of about 400 nm by a sputtering method, and then the WN layer is etched by reactive ion etching (RIE) to leave the WN layer 23 only on the side wall of the insulating film 28 (FIG. 4).
(See (c)). The WN layer 23 serves as a Schottky electrode. Next, after removing the insulating film 28 using, for example, an aqueous solution of hydrogen fluoride, the SiO ₂ film 27 is formed by a method such as a plasma CVD method having excellent step coverage.
Deposit about 0 nm (see FIG. 4D). Then, in order to form the source / drain high-concentration regions 25a and 25b, for example, an acceleration voltage of 250 KeV and a dose of 1 × 10 ^{14 are used.}
Si ions are implanted into the source / drain regions of the substrate 21 through the SiO ₂ film 27 under the condition of cm ⁻² (FIG. 4D).
reference).

Next, the SiO ₂ film 27 is left only on the drain side of the gate electrode 23 by etching back by an amount corresponding to the film thickness of the SiO ₂ film 27 by anisotropic etching such as RIE (FIG. 4E). )reference). Subsequently, Si ions are ion-implanted into the substrate 1 under the conditions of an acceleration voltage of 50 KeV and a dose amount of 1 × 10 ¹³ cm ^-2 to form an intermediate concentration layer 24 between the gate electrode 23 and the source region (FIG. 4). (See (e)). Then, after anneal at 800 to 900 ° C. to activate the ion-implanted layer, the source electrode 26a and the drain electrode 26b made of, for example, AuGe alloy are formed (see FIG. 4F). This completes the FET.

As described above, according to this embodiment, the high concentration source / drain regions 25a and 25b or the intermediate concentration layer 24 are self-aligned with the gate electrode when manufacturing a multi-finger type asymmetric FET. Therefore, it is possible to avoid the variation in the patterning process of the resist, which has been a problem in the conventional manufacturing method. Further, the resist patterning step in the gate length direction becomes unnecessary, which is suitable for forming an FET having a fine gate length. As a result, the asymmetric FET can be manufactured with high accuracy and high reproducibility by using the self-alignment technique.

Next, a second embodiment of the manufacturing method of the second invention will be described with reference to FIG. The manufacturing method of this embodiment is
The steps up to the step shown in FIG. 4D are performed in the same manner as in the case of the first embodiment. The ion implantation conditions shown in FIG.
Unlike the ion implantation conditions shown in (d), the intermediate concentration layer 2
4 is not formed. After that, as shown in FIG.
The iO ₂ film 27 is selectively removed to form a source electrode 25a and a drain electrode 25b as shown in FIG. 5 (f). As a result, a multi-finger type asymmetric FET is completed. The manufacturing method of the second embodiment is different from the manufacturing method of the first embodiment in that the gate electrode 23 of the first embodiment is different.
The step of etching back the SiO ₂ film 27 so as to form the side wall and the step of forming the intermediate concentration layer 24 are unnecessary.

The manufacturing method of the second embodiment is also the first
It goes without saying that it has the same effect as that of the embodiment.

Next, a third embodiment of the manufacturing method according to the second invention will be described with reference to FIG. The manufacturing method of the third embodiment is used when the gate length is relatively long and the intermediate concentration layer is unnecessary.

First, the steps shown in FIGS. 6A to 6C are the same as the steps shown in FIGS. 4A to 4C of the first embodiment, and are similar to those of the first embodiment. Do it. Then, after removing the insulating film 28, the SiO ₂ film 27 of 300 n is formed by a method having excellent step coverage such as a plasma CVD method.
About m are deposited (see FIG. 6D). Subsequently, the SiO ₂ film 27 is left only on the drain side of the gate electrode 23 by etching back by an amount corresponding to the film thickness of the SiO ₂ film 27 using anisotropic etching such as RIE (FIG. 6).
(See (e)). By implanting Si ions into the substrate 1, high concentration source / drain regions 25a,
25b is formed (see FIG. 6E). Next, after removing the SiO ₂ film 27, the source electrode 25a and the drain electrode 25b are formed in the source region and the drain region as shown in FIG. 6F.

In the manufacturing method of the third embodiment,
After etching back the SiO ₂ film 27, a high concentration source
By forming the drain regions 25a and 25b,
The high-concentration source region 25a can be formed in the immediate vicinity of the gate electrode 23, and the source resistance can be reduced.
It goes without saying that this third embodiment also has the same effects as the first embodiment.

In the first, second and third embodiments, the GaAs MESFET has been described as an example, but the present invention is not limited to GaAs and is applicable to other compound semiconductors and further FETs using silicon. It is possible. Further, the case where the operation layer 22 on the semiconductor surface is n-type has been described, but it is also possible to use p-type or a combination of n-type and p-type.

Next, the structure of an embodiment of the manufacturing method according to the third invention will be described with reference to FIGS.

First, as shown in FIG. 7A, after an n ⁻ type layer 42 serving as an FET operation layer is formed on the surface of a semi-insulating GaAs substrate 41 by a selective ion implantation method, plasma CVD is performed. The SiO ₂ film 43 to a thickness of 40
Deposit 0 nm over the entire surface. Further, a resist film 44 is applied on the SiO ₂ film to form a resist pattern 44 having holes extending from the source region to the operation layer 42. Next, as shown in FIG. 7B, the SiO ₂ film 43 is selectively etched by RIE using the resist pattern 44 as a mask so that the resist pattern 44 has an overhang shape, and then, for example, the SIO film 45 is formed. Deposition is performed from the gate length direction at a predetermined angle (for example, a value in a certain angle range including 75 degrees) with respect to the normal direction of the wafer surface. Further, as shown in FIG. 7C, a heat-resistant metal, LaB, is used.
₆ is evaporated from the direction normal to the wafer surface, the resist pattern 44 is lifted off, and a Γ-shaped gate electrode 46 is formed. After that, as shown in FIG. 7D, a resist 47 is applied on the entire surface to form a resist pattern 47 for ion implantation of an intermediate concentration layer, and then RIE using CF ₄ + O ₂ gas is performed.
To selectively open the SiO ₂ film 43 to remove the intermediate concentration layer 4
8a and 48b are, for example, an acceleration voltage of 50 KeV and a dose amount of 1
It is formed by ion-implanting Si under the condition of × 10 ¹³ cm ^-2 . Here, in the drain region immediately near the gate, the intermediate concentration layer is not formed because it is masked by the gate metal 46. Next, as shown in FIG. 7C, the resist pattern 47 and the SiO ₂ film 43 are removed, and plasma C
After depositing the SiO ₂ film 49 or the like VD method, by etching in the vertical direction thickness equivalent only by anisotropic etching such as reactive ion etching (RIE), SiO ₂ film only on the side wall of the gate electrode 46 Let 49 remain. Subsequently, as shown in FIG. 8B, a resist pattern 50 is formed, and using this as a mask, for example, an acceleration voltage 1
Si is ion-implanted under the conditions of 00 KeV and a dose amount of 5 × 10 ¹³ cm ⁻² to form deep and high-concentration n ⁺ layers 51a and 51b. Then, as shown in FIG. 8B, after removing the resist pattern 50, annealing for activating the ion-implanted layer is performed, and finally, the source electrode 52a and the drain electrode 52b made of AuGe alloy are formed to form the FET.
Is completed.

As described above, according to the present embodiment, a Γ-shaped gate is formed by oblique vapor deposition of the insulating film and vapor deposition of the refractory metal from above, and this gate is used as a mask during ion implantation. By forming the intermediate concentration layer, the asymmetric FET can be manufactured in a self-aligned manner with high accuracy and high reproducibility.

[0045]

As described above, according to the present invention, an asymmetric FET can be manufactured with high accuracy and high reproducibility.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a first embodiment of a manufacturing method according to the first invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the first embodiment of the manufacturing method according to the first invention.

FIG. 3 is a cross-sectional view of a semiconductor device manufactured by the first embodiment of the manufacturing method of the second invention.

FIG. 4 is a cross-sectional view showing the manufacturing process of the first embodiment of the second invention.

FIG. 5 is a cross-sectional view showing the manufacturing process of the second embodiment of the second invention.

FIG. 6 is a cross-sectional view showing the manufacturing process of the third embodiment of the second invention.

FIG. 7 is a cross-sectional view showing the manufacturing process of the third embodiment of the invention.

FIG. 8 is a sectional view showing a manufacturing process of an embodiment of the third invention.

FIG. 9 is a sectional view of a semiconductor device manufactured by a conventional manufacturing method.

FIG. 10 is a cross-sectional view showing a manufacturing process of a conventional manufacturing method.

[Explanation of symbols]

1, 21, 41 GaAs substrate 2, 22 n-type operating layer 3 metal film (gate electrode) 4, 7, 10, 28, 43, 49 SiO ₂ film 5 SiNx film 6 drain region 8, 11 photoresist 9, 24, 48a, 48b Intermediate concentration layer 12 High concentration source region 23 Gate electrode 25a Source high concentration region 25b Drain high concentration region 26a, 52a Source electrode 26b, 52b Drain electrode 27 Insulating film 42 Operating layer 44, 47, 50 Resist pattern 45 SIO film 46 gates 51a, 51b high concentration layer

Continuation of the front page (51) Int.Cl. ⁵ Identification number Reference number within the agency FI Technical indication location H01L 21/266 8617-4M H01L 21/265 V 8617-4M A 8617-4M M 7376-4M 29/80 B

Claims (5)

[Claims] 1. A step of forming an operation layer on a semiconductor substrate,
Laminating a metal layer and an auxiliary film layer made of a material that can be selectively removed from the metal layer, removing the auxiliary film layer and the metal layer on the drain formation region, and forming the auxiliary film layer on the auxiliary film layer. On the other hand, a step of forming a first insulating film made of a material that can be selectively removed on the entire surface of the substrate, and etching back the first insulating film using anisotropic etching The first insulating film is left only on the side walls of the metal layer and the auxiliary film layer, and the drain region is formed by ion-implanting the left first insulating film and the auxiliary film into the substrate. A step of selectively removing only the auxiliary film, a step of forming a second insulator layer on the entire surface of the substrate, and a step of anisotropically etching the second insulator layer. Etch back, before The only on the sidewalls of the first insulating layer a second
The step of leaving the insulator layer left unetched, the step of etching back the metal layer by anisotropic etching using the left second insulator layer as a mask, and forming the source region by ion implantation. And a step of forming source and drain electrodes, a method of manufacturing a semiconductor device. 2. A step of forming an operating layer on a semiconductor substrate,
Forming a first insulating film layer on a region of the operating layer where a drain is formed; forming a gate electrode made of a metal material on a sidewall of the first insulating film;
Forming a second insulating film so as to cover the gate electrode and the operating layer after removing the insulating film of 1), and forming a high concentration source / drain region on the surface of the substrate by ion implantation And a step of removing the second insulating film, and a step of forming a source electrode and a drain electrode, the method of manufacturing a semiconductor device. 3. In the step of removing the second insulating film, the second insulating film is etched back by using anisotropic etching to remove the second insulating film only on the drain side sidewall portion of the gate electrode. 2) leaving the insulating film, and forming an intermediate concentration layer between the operating layer and the source / drain high concentration region on the source side of the gate electrode by implanting ions into the substrate, 3. The method for manufacturing a semiconductor device according to claim 2, further comprising the step of removing the remaining second insulating film. 4. A step of forming an operating layer on a semiconductor substrate,
Forming a first insulating film layer on a region of the operating layer where a drain is formed; forming a gate electrode made of a metal material on a sidewall of the first insulating film;
The step of forming a second insulating film so as to cover the gate electrode and the operating layer after removing the insulating film, and by etching back the second insulating film using anisotropic etching. A step of leaving the second insulating film only on the side wall of the gate electrode on the drain side; a step of forming a high concentration source / drain region on the surface of the substrate by ion implantation; And a step of forming a source electrode and a drain electrode after removing the second insulating film, the method for manufacturing a semiconductor device. 5. A step of forming an operating layer on a semiconductor substrate,
A step of forming a first insulating film on the operating layer, a step of applying a photoresist on the first insulating film and patterning the photoresist to remove the photoresist on the gate formation region, and the patterning Removing the first insulating film on the gate formation region by using the formed photoresist as a mask, and depositing an insulating material in a direction that forms a predetermined angle with respect to the normal line of the substrate and from the gate length direction. A step of forming a second insulating layer on the gate region, and then vapor-depositing a metal to form a gate electrode in the same manner, and removing the photoresist, and then applying the photoresist again. Forming a mask for forming an intermediate concentration layer by patterning the first insulating film; and forming an intermediate concentration layer by implanting ions. And a step of forming a second insulating film on the substrate after removing the photoresist, and a step of etching back the second insulating film using anisotropic etching to form the gate electrode of the gate electrode. The step of leaving the second insulating film only on the side wall, the step of forming a source / drain high-concentration region by ion implantation after forming the resist pattern, and the step of removing the resist pattern and then the source electrode and A step of forming a drain electrode, and a method of manufacturing a semiconductor device.