JPH06310711A - Field-effect transistor and fabrication thereof - Google Patents

Abstract

PURPOSE:To realize mass production of a sufficiently fine MOSFET. CONSTITUTION:A level difference 2 is formed on the surface of a semiconductor substrate 1 and a gate electrode 4 is formed on the wall face 2W at the level difference 2 through a gate insulation layer 3 thus forming a gate part at the level difference 2. A source region 5 and a drain region 6 are then formed, while sandwiching the gate part, on any one and the other of the upper face 2a and the bottom face 2b at the level difference 2 of the semiconductor substrate 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor, and more particularly to a MOSFET (insulated gate type field effect transistor) and its manufacturing method.

[0002]

2. Description of the Related Art Normally, in the manufacture of MOSFET,
The processing of the gate electrode that determines the channel length is performed by patterning by photolithography.

By the way, in semiconductor integrated circuits, for example, demands for miniaturization of MOSFETs and shortening of channel are increasing more and more. The miniaturization of this MOSFET reaches the limit of photolithography technology.

Therefore, in order to enable finer processing of the photolithography, the wavelength of light used for pattern exposure of the photoresist is shortened, and the exposure light is changed from the g-line to the i-line. Then, the process proceeds to the use of excimer laser (248 nm), which results in 0.
A channel length of about 25 μm has become possible.

However, there is an increasing demand for further miniaturization and lower operating voltage, and a channel length of 0.1 μm or less is needed, and patterning by light is limited. There is. Then, the pattern shift of the photoresist by electron beam scanning or X-ray scanning has been made, but as a practical problem, the use of such electron beam, X-ray, etc. is not mass-produced and the device itself is expensive. Higher costs due to price changes.

[0006]

SUMMARY OF THE INVENTION The present invention is not limited by the limit of photolithography and is sufficiently fine.
The present invention relates to a field effect transistor capable of mass-producing T and a manufacturing method thereof.

[0007]

According to the present invention, a step 2 is formed on the surface of a semiconductor substrate 1 and a gate insulating layer is formed on a wall surface 2W of the step 2 as shown in FIG. A gate electrode 4 is deposited on the layer 3 to form a gate portion on the step 2.

Then, a source region 5 and a drain region 6 are formed on either or both of the upper surface 2a and the bottom surface 2b of the step 2 of the semiconductor substrate 1 with the gate portion therebetween.

Further, in the manufacturing method of the present invention, a step 2 is formed on a part of the surface of the semiconductor substrate 1 by anisotropic etching, as shown in FIGS. A step of forming the gate insulating layer 3 on the surface of the semiconductor substrate 1 including the wall surface 2W of the step 2 (FIG. 4), and a step of forming the gate electrode layer 41 on the entire surface of the semiconductor substrate 1 (FIG. 5). , The gate electrode layer 41 is formed on the step 2 of the semiconductor substrate 1.
Of the gate electrode layer 41 is anisotropically etched to a thickness such that the upper surface 2a and the bottom surface 2b of the gate electrode 4 are exposed, and the gate electrode layer 41 is left only on the wall surface 2W of the step 2.
For forming the source region 5 and the drain region 6 on the upper surface 2a and the bottom surface 2b of the step 2 of the semiconductor substrate 1 using the gate electrode 4 as a mask (FIG. 8). To form a MOSFET.

[0010]

In the present invention, since the gate portion is formed on the wall surface 2W of the step 2, the channel length depends on the height of the step 2. That is, according to the present invention, since the height of the step 2, that is, the depth of the anisotropic etching in the manufacturing method of the present invention can be defined, this can be made sufficiently small.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An example of the present invention will be described with reference to the drawings. In this example, it is applied to a so-called LDD type MOSFET having a low concentration drain region on the drain side.

In the present invention, as shown in FIG. 2, a semiconductor substrate 1 is prepared. The semiconductor substrate 1 includes not only a semiconductor substrate made of a semiconductor but also a semiconductor substrate having a configuration in which a semiconductor thin film is formed on various substrates.

In order to form a step 2 on one main surface side of the semiconductor substrate 1 as shown in FIG. 3, first, as shown in FIG. 2, for example, a bottom surface of the step 2 is formed on one main surface of the substrate 1. A mask layer 10 having an opening 10W is formed in the portion to be formed.

The mask layer 10 can be formed by applying photoresist, exposing, and developing. In this case, the mask layer 10 is formed simply by arranging the edge portion of the opening 10W at the step forming position. Therefore, it is not necessary to form a fine pattern.

As shown in FIG. 3, the semiconductor substrate 1 is R-shaped through the opening 10W using the mask layer as an etching mask.
The step 2 is formed by anisotropically etching such as IE (reactive ion etching) to a required shallow depth, for example, 0.15 μm.

As shown in FIG. 4, the gate insulating layer 3 having a thickness of, for example, 4 nm is entirely formed on at least the wall surface 2W of the step 2 and the bottom surface 2b adjacent thereto by surface thermal oxidation or the like.
To form.

As shown in FIG. 5, for example, a thickness of 1
A so-called polycide layer, i.e., a polycrystalline silicon layer, and a gate electrode layer 41, which is formed by stacking a silicide layer, that is, a compound layer of silicon and a refractory metal, is deposited on the so-called polycide layer at 50 nm.

As shown in FIG. 6, the gate electrode layer 41 remains as a so-called side wall only on the wall surface 2W of the step 2 by anisotropic etching by RIE or the like, and the gate electrode 4 is thereby formed. To do. In other words, the thickness and etching amount of the gate electrode layer 41 are selected in advance so that such a side wall is formed.

As shown in FIG. 7, with the gate electrode 4 as a mask, n ⁺ or p-type impurities such as As ⁺ of n-type impurities are added to the substrate 1 at 10 keV and 5 × 10 ¹³ ions / cm 2.
30 with a dose of ² perpendicular to the substrate surface
Ions are implanted while being tilted and rotated to form the low concentration region 7.

As shown in FIG. 8, a sidewall-shaped gate is used.
On the side surface of the gate electrode 4, for example, SiO ₂Different from CVD of film
The width w is, for example, 0.03 μm or more due to the anisotropic etching.
The marginal sidewalls 8 are formed, and these sidewalls are formed.
8 and the gate electrode 4 as a mask to the semiconductor substrate 1.
Then, an impurity of the same conductivity type as the region 7 such as As⁺15k
2 x 10 in eV¹⁵ions / cm²With a dose of
Source regions on the top surface 2a and bottom surface 2b of the step 2
5 and the drain region 6 are formed.

Thereafter, for example, irradiation with excimer laser light,
For example, a pulse width of 44 nsec by a XeCl laser
In, 800 mJ · cm ^- performing self-alignment annealing to mask the ^second gate electrode.

In this way, as shown in FIG. 1, the gate electrode 4 is formed mainly through the wall surface 2W gate insulating layer 3 of the step 2, and the low concentration region 7 is formed on the bottom surface 2b of the step 2 with the gate electrode 4 sandwiched therebetween. A high-concentration drain region 6 is formed via the low-concentration drain region, and the drain region 5 is formed on the upper surface 2a.
And a MOSFET according to the present invention is formed.

[0023] Then, an insulating layer for example interlayer insulating layer such as SiO ₂ (not shown) is formed by CVD or the like, if necessary, the source and drain each area on, performs electrodes Apertures further on the gate electrode 4 Then, for example, Al electrodes or wirings are deposited and formed through these windows.

In the MOSFET having this structure, the low-concentration region 7 of the drain is formed by oblique implantation as described above at the time of ion implantation, so that the gate electrode 4 is formed in the state after the region 7 is annealed. Since the channel length can be formed by penetrating below, the channel length is determined almost corresponding to the depth of the step 2. Therefore, by making the depth of the step 2 sufficiently small, a sufficiently short channel length can be obtained. Can be formed regardless of the pattern of the photoresist.

[0025]

As described above, in the present invention, since the gate portion is formed on the wall surface 2W of the step 2, the channel length depends on the height of the step 2. That is, according to the present invention, since the height of the step 2, that is, the depth of the anisotropic etching in the manufacturing method of the present invention can be defined, this can be made sufficiently small.

Further, since the photolithography technique by electron beam scanning, X-ray scanning and the like is avoided, the mass productivity is excellent.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view of an example of a field effect transistor according to the present invention.

FIG. 2 is a schematic cross-sectional view in a step of an example of the manufacturing method of the present invention.

FIG. 3 is a schematic cross-sectional view in a step of an example of the production method of the present invention.

FIG. 4 is a schematic cross-sectional view in a step of an example of the manufacturing method of the present invention.

FIG. 5 is a schematic cross-sectional view in a step of an example of the production method of the present invention.

FIG. 6 is a schematic cross-sectional view in a step of an example of the production method of the present invention.

FIG. 7 is a schematic cross-sectional view in a step of an example of the production method of the present invention.

FIG. 8 is a schematic cross-sectional view in a step of an example of the manufacturing method of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 step 2W wall surface 3 gate insulating layer 4 gate electrode 41 gate electrode layer

Claims (2)

[Claims] 1. A step is formed on a surface of a semiconductor substrate, and a gate electrode is formed on a wall surface of the step via a gate insulating layer to form a gate portion on the step. A field effect transistor comprising a source region and a drain region formed on an upper surface and a bottom surface with the gate portion therebetween, respectively. 2. A step of forming a step by anisotropic etching on a part of the surface of the semiconductor substrate, a step of forming a gate insulating layer on the surface of the semiconductor substrate including a wall surface of the step, and the entire surface of the semiconductor substrate. A step of forming a gate electrode layer selectively, and the gate electrode layer is anisotropically etched to a wall thickness of the step so that the top and bottom surfaces of the step of the semiconductor substrate are exposed. And a step of forming a gate electrode having a gate electrode layer left in a limited manner, and a step of forming a source region and a drain region on the upper surface and the bottom surface of the step of the semiconductor substrate with the gate electrode as a mask. The manufacturing method of the characteristic field effect transistor.