JP2011061094A - Method of manufacturing field effect transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a field effect transistor in which the field effect transistor having a short gate length can be manufactured at low cost. <P>SOLUTION: The method of manufacturing the field effect transistor includes the steps of: forming a semiconductor layer including a channel layer made of a nitride-based compound and an upper layer laminated on the channel layer on a substrate; forming a level difference part including a part of a surface of the channel layer as a bottom surface part and a side face of the semiconductor layer exposed by etching as a side wall part by etching at least a partial region of the semiconductor layer from the upper layer to a depth reaching the channel layer; forming a mask layer so as to cover a surface of the semiconductor layer including the level difference part and etching back the mask layer to form a mask part where the mask layer of the level difference part is left; forming a contact region in a region except the mask part of the bottom surface part by an ion implantation method; and sequentially forming a gate insulating film and a gate electrode so as to cover at least the bottom surface part and side wall part of the level difference part after removing the mask part. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a field effect transistor made of a nitride compound semiconductor used as a power electronics device or a high frequency amplification device.

Formula _{Al x In y Ga 1-xy} As u P v N 1-uv ( although, 0 ≦ x ≦ 1,0 ≦ y ≦ 1, x + y ≦ 1,0 ≦ u <1,0 ≦ v <1, u + v < Wide band gap semiconductors represented by III-V group nitride compounds represented by 1) have high dielectric breakdown voltage, good electron transport properties, and good thermal conductivity. It is very attractive as a material for semiconductor devices for high frequency or high frequency applications. For example, in a field effect transistor (FET) having an AlGaN / GaN heterojunction structure, a two-dimensional electron gas is generated at the heterojunction interface due to the piezoelectric effect. Since this two-dimensional electron gas has a high electron mobility and carrier density, a heterojunction FET (HFET) using an AlGaN / GaN heterostructure has a low on-resistance and a high switching speed, and operates at a high temperature. Is possible. These features are very suitable for power switching applications.

  A normal AlGaN / GaN HFET is a normally-on type device in which a current flows when a bias is not applied to the gate, and the current is interrupted by applying a negative potential to the gate. On the other hand, in power switching applications, in order to ensure safety when the device breaks, a normally-off type device in which no current flows when no bias is applied to the gate and a current flows by applying a positive potential to the gate Is preferred. Therefore, a field effect transistor (MOSFET) employing a MOS structure to realize a normally-off device has been disclosed (see Non-Patent Document 1 and Patent Document 1).

  Incidentally, the gate length of a MOS FET (MOSFET) made of a nitride compound semiconductor is, for example, about 20 μm (see Patent Document 2). In order to realize low on-resistance and high-speed operation, it is preferable that the gate length be much shorter.

JP 2008-311392 A JP 2007-250727 A

Matocha. K, Chow. T.P, Gutmann. R.J., “High-voltage normally off GaN MOSFETs on sapphire substrates”, IEEE Transaction on Electron Devices. Vol. 52, No. 1 2005 pp. 6-10

  However, in the conventional technique, it is difficult to make the gate length shorter than the minimum line width of the exposure pattern of the exposure apparatus for forming the pattern of the device. Therefore, when it is desired to shorten the gate length, an expensive exposure apparatus with a narrower minimum line width is required, which raises a problem that the manufacturing cost increases.

  The present invention has been made in view of the above, and an object of the present invention is to provide a method of manufacturing a field effect transistor capable of manufacturing a field effect transistor having a short gate length at low cost.

  In order to solve the above-described problems and achieve the object, a method of manufacturing a field effect transistor according to the present invention is a method of manufacturing a field effect transistor having a MOS structure and made of a nitride-based compound semiconductor. A semiconductor layer forming step of forming a semiconductor layer including a channel layer made of a nitride-based compound semiconductor and an upper layer laminated on the channel layer; and a partial region of the semiconductor layer from at least the upper layer to the channel Etching to a depth reaching the layer, forming a step portion having a part of the surface of the channel layer as a bottom portion and a side portion of the side surface of the semiconductor layer exposed by etching as a side portion; and A mask layer is formed so as to cover the surface of the semiconductor layer including the portion, and the mask layer is etched back to form a mask portion in which the mask layer of the step portion remains. A contact region forming step of forming a contact region in a region excluding the mask portion of the bottom surface portion by ion implantation, and at least the bottom surface portion of the stepped portion after removing the mask portion And a gate part forming step of sequentially forming a gate insulating film and a gate electrode so as to cover the side wall part.

In the field effect transistor manufacturing method according to the present invention, in the above invention, in the mask portion forming step, the mask layer made of SiO ₂ is formed by a PCVD method, and the mask layer is etched by anisotropic dry etching. It is characterized by doing.

  The field effect transistor manufacturing method according to the present invention is characterized in that, in the above invention, the mask layer has a thickness of 250 to 3750 nm.

  According to the present invention, a field effect transistor having a short gate length can be produced at low cost without depending on the minimum line width of the exposure apparatus.

FIG. 1 is a schematic cross-sectional view of a MOSFET manufactured by the manufacturing method according to the embodiment. FIG. 2 is a diagram for explaining a method of manufacturing the MOSFET shown in FIG. FIG. 3 is a diagram for explaining a method of manufacturing the MOSFET shown in FIG. FIG. 4 is a diagram for explaining a method of manufacturing the MOSFET shown in FIG. FIG. 5 is a diagram for explaining a method of manufacturing the MOSFET shown in FIG. FIG. 6 is a diagram for explaining a method of manufacturing the MOSFET shown in FIG. FIG. 7 is a diagram for explaining a method of manufacturing the MOSFET shown in FIG. FIG. 8 is a diagram for explaining a method of manufacturing the MOSFET shown in FIG.

  Embodiments of a method for producing a field effect transistor according to the present invention will be described below in detail with reference to the drawings. Note that the present invention is not limited to the embodiments.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view of a MOSFET manufactured by a manufacturing method according to an embodiment of the present invention. The MOSFET 100 includes a buffer layer 2 in which an AlN layer is a bottom layer and an AlN layer and a GaN layer are alternately stacked on a substrate 1 made of GaN, sapphire, SiC, Si having a (111) plane as a main surface, and the like. A channel layer 3 made of undoped u-GaN and an electron supply layer 4 as an upper layer made of AlGaN are sequentially formed. The channel layer 3 and the electron supply layer 4 form an AlGaN / GaN heterostructure, and a two-dimensional electron gas is generated near the interface of the channel layer 3.

In this MOSFET 100, the semiconductor layer from the electron supply layer 4 to the depth reaching the channel layer 3 is removed in a part of the region, and a part of the surface of the channel layer 3 is a bottom surface portion 5a, which is exposed by the above removal. A step portion 5 having a side wall portion 5b is formed. A contact region 6 made of n ⁺ -GaN is formed in a part of the bottom surface portion 5 a of the step portion 5 over the inside of the channel layer 3. A gate insulating film 7 is formed from the surface of the channel layer 3 to the stepped portion 5 and the surface of the electron supply layer 4. On the gate insulating film 7, a gate electrode 8 is formed so as to cover a part of the electron supply layer 4, the side wall 5b of the stepped portion 5, and the region between the contact region 6 and the side wall 5b. A gate portion G is formed. A source electrode 9 is formed so as to contact the contact region 6. A drain electrode 10 is formed on the electron supply layer 4.

  In this MOSFET 100, a region between the contact region 6 and the side wall portion 5 b of the step portion 5 in the channel layer 3 becomes the channel region 11. This MOSFET 100 can reduce the width of the channel region 11, that is, the gate length, without depending on the minimum line width of the exposure apparatus, by the manufacturing method according to the present embodiment described below.

Hereinafter, the manufacturing method according to the present embodiment will be specifically described with reference to FIGS. First, as shown in FIG. 2, a buffer layer 2, a channel layer 3, and an electron supply layer 4 that is an upper layer stacked on the channel layer 3 are sequentially epitaxially grown on the substrate 1 by, for example, MOCVD. Note that TMGa, TMAl, NH _{3 and the} like are used in appropriate combinations as raw materials for each layer. Thereafter, a mask layer M1 made of a dielectric film such as SiO ₂ is formed on the electron supply layer 4. The mask layer M1 is formed with a thickness of 500 nm by plasma enhanced chemical vapor deposition (PCVD) using, for example, SiH ₄ and N ₂ O.

  Next, a resist R is applied on the mask layer M1, and patterning for forming the stepped portion 5 is performed on the resist R by photolithography. Then, as shown in FIG. 3, with this patterned resist R as a mask, the mask layer M1 and the surface of the electron supply layer 4 reach a depth greater than the thickness of the electron supply layer 4, that is, at least the channel layer 3. Etching is removed to a depth to form a stepped portion 5 including a bottom surface portion 5a and a side wall portion 5b. Note that buffer hydrofluoric acid or the like is preferably used for etching the mask layer M1. The electron supply layer 4 and the channel layer 3 are etched using a dry etching method such as ICP (Inductively Coupled Plasma) -RIE (Reactive Ion Etching) using a chlorine-based gas. Is preferred.

After removing the resist R, a mask layer M2 made of a dielectric film such as SiO ₂ is formed as shown in FIG. The mask layer M2 is formed on the entire surface, covers the step portion 5, and covers the electron supply layer 4 via the mask layer M1. Further, the thickness of the mask layer M2 is, for example, 750 nm. In forming the mask layer M2, the conditions for film formation are appropriately set so that the thickness of the mask layer M2 is substantially the same on the bottom surface portion 5a and the side wall portion 5b of the stepped portion 5 and the surface of the electron supply layer 4. Is preferably set.

Next, as shown in FIG. 5, the mask layer M2 is etched back by ICP-RIE using, for example, CF ₄ gas. This etch back is performed until at least the bottom surface portion 5a of the step portion 5 is exposed.

  Here, since the pressure is low in the etching by RIE, the etching ions are incident on the substrate surface substantially perpendicularly. When viewed from the incident direction of the etching gas, the thickness of the portion of the mask layer M2 formed along the side wall portion 5b of the stepped portion 5 is a thickness obtained by adding the length of the side wall portion 5b to 750 nm. Yes. On the other hand, the thickness of the other part of the mask layer M2 is 750 nm. Therefore, when etching back is performed until the bottom surface portion 5a of the stepped portion 5 is exposed, a portion of the mask layer M2 having a thickness of 750 nm with respect to the main surface of the substrate is removed, but the sidewall portion 5b The portion formed along the following (hereinafter referred to as mask portion M2a) remains. Therefore, the mask portion M2a covers the partial region 5aa and the side wall portion 5b of the bottom surface portion 5a of the step portion 5. Since etching ions hardly enter from the side surface side of the substrate, the width of the mask portion M2a in the direction along the bottom surface 5a (the width of the region 5aa) is about 600 nm, which is substantially equal to the thickness of the mask layer M2, 750 nm. It becomes.

Next, as shown in FIG. 6, a screen oxide film M3 made of, for example, SiO ₂ is formed to a thickness of 20 nm on the entire surface. Thereafter, Si ions, which are n-type dopants, are implanted into the entire surface. The implantation energy is set so that the interface between the screen oxide film M3 and the bottom surface 5a has the highest concentration, and the dose amount is, for example, 1 × 10 ¹⁵ cm ⁻² . At this time, since the mask portion M2a serves as a mask for ion implantation, Si ions are implanted into the channel layer 3 in the region other than the region 5aa covered with the mask portion M2a in the bottom surface 5a. Note that ion implantation into the electron supply layer 4 is prevented by the mask layer M1.

Thereafter, a SiO ₂ film is formed to a thickness of 500 nm, and this is used as a protective film for annealing, and heat treatment is performed at 1000 ° C. for 4 minutes as activation annealing of the implanted Si ions. As a result, a contact region 6 made of n ⁺ -GaN is formed in the bottom surface portion 5 a across the channel layer 3. Since the contact region 6 is substantially a part of the source electrode, the region between the contact region 6 and the side wall portion 5 b becomes the channel region 11. The width of the channel region 11, that is, the gate length is substantially the same as the width of the mask portion M 2 a, that is, the thickness of the mask layer M 2 to be formed, and therefore the minimum line width of the exposure apparatus used in other processes and the like. It can be shortened without depending on it.

Next, the screen oxide film M3, the mask layer M1, and the mask portion M2a are removed with hydrofluoric acid or the like, and RCA cleaning is performed. Thereafter, as shown in FIG. 7, a gate insulating film 7 made of SiO _{2 is} formed on the entire surface with a thickness of 60 nm, for example.

  Next, the gate insulating film 7 in the region where the source electrode 9 and the drain electrode 10 are to be formed is removed by photolithography and etching using buffered hydrofluoric acid. Then, as shown in FIG. 8, the source electrode 9 and the drain electrode 10 are formed in the removed portion using a sputtering method and a lift-off method. The source electrode 9 and the drain electrode 10 are ohmic electrodes having a structure of, for example, Ti / Al = 25 nm / 200 nm, and are baked by performing a heat treatment at 600 ° C. for 10 minutes, for example.

  Thereafter, the gate electrode 8 is formed on the gate insulating film 7 by using the sputtering method and the lift-off method, and the gate portion G is formed. Thereby, the MOSFET 100 is completed. The gate electrode 8 is a Schottky electrode having a structure of Ni / Au = 50 nm / 100 nm, for example.

  As described above, according to the manufacturing method according to the present embodiment, the gate length of MOSFET 100 can be set to a gate length substantially corresponding to the width of mask portion M2a, that is, the thickness of mask layer M2. The gate length can be made short regardless of the minimum line width of the exposure apparatus used in the process. As a result, MOSFET 100 having a shorter gate length than the conventional one can be manufactured at low cost without preparing an expensive exposure apparatus. Since the process for forming the channel region 11 is a self-alignment process, the position accuracy is high regardless of the accuracy of the exposure apparatus, and the length of the parasitic region between the source and the channel is made substantially zero. be able to. Therefore, the MOSFET 100 is less affected by the parasitic capacitance between the source and the channel, and can perform a high-speed switching operation.

  In the above embodiment, the thickness of the mask layer M2 is set to 750 nm. However, this thickness can be formed in the range of 250 to 3750 nm using, for example, a normal PCVD method. Therefore, the gate length that can be formed can be approximately 200 to 3000 nm. Note that it is preferable that the gate length is 200 nm or more because the electric field at the gate portion does not become too strong, which prevents the punch-through phenomenon and reduces the leakage current when the gate is in the OFF state. In addition, since a gate length of 3 μm or less is difficult to manufacture by a conventional method using a contact aligner, the manufacturing method according to the present invention is particularly suitable.

The field effect transistor that can be manufactured by the manufacturing method according to the present invention is not limited to that shown in FIG. For example, in the structure shown in FIG. 1, a field effect transistor having a structure in which the material of the channel layer is replaced with p-GaN or the electron supply layer is replaced with a contact layer made of n ⁺ -GaN, and the gate length is short is manufactured. You can also
Furthermore, the semiconductor layer of the MOSFET of the present invention may further include a drift layer made of p-GaN or undoped GaN between the channel layer and the electron supply layer.

In the above embodiment, GaN as a nitride-based compound semiconductor, AlGaN, but using AlN or the like, the present invention is not limited to this, the chemical formula _{Al x In y Ga 1-xy} As u P v N 1 A nitride compound semiconductor represented by _−uv (where 0 ≦ x ≦ 1, 0 ≦ y ≦ 1, x + y ≦ 1, 0 ≦ u <1, 0 ≦ v <1, u + v <1) is appropriately used. be able to.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3 Channel layer 4 Electron supply layer 5 Step part 5a Bottom part 5aa area 5b Side wall part 6 Contact area 7 Gate insulating film 8 Gate electrode 9 Source electrode 10 Drain electrode 11 Channel area M1, M2 Mask layer M2a Mask part M3 Screen oxide film R Resist

Claims (3)

A method of manufacturing a field effect transistor having a MOS structure and made of a nitride compound semiconductor,
Forming a semiconductor layer including a channel layer made of a nitride-based compound semiconductor and an upper layer stacked on the channel layer on a substrate; and
Etching a partial region of the semiconductor layer at least to a depth from the upper layer to the channel layer, using a part of the surface of the channel layer as a bottom surface, and side surfaces of the semiconductor layer exposed by the etching as side walls A step forming step for forming a step with
Forming a mask layer so as to cover the surface of the semiconductor layer including the stepped portion, and forming a mask portion by etching back the mask layer to leave the mask layer of the stepped portion; and
A contact region forming step of forming a contact region in a region excluding the mask portion of the bottom portion by ion implantation;
A gate portion forming step of sequentially forming a gate insulating film and a gate electrode so as to cover at least the bottom surface portion and the side wall portion of the stepped portion after removing the mask portion;
A method of manufacturing a field effect transistor comprising: _{2. The} method of manufacturing a field effect transistor according to claim 1, wherein, in the mask portion forming step, the mask layer made of SiO2 is formed by a PCVD method, and the mask layer is etched by anisotropic dry etching. .   3. The method of manufacturing a field effect transistor according to claim 1, wherein the mask layer has a thickness of 250 to 3750 nm.

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