JPH0834224B2 - Method for manufacturing field effect transistor - Google Patents

Method for manufacturing field effect transistor

Info

Publication number
JPH0834224B2
JPH0834224B2 JP62082314A JP8231487A JPH0834224B2 JP H0834224 B2 JPH0834224 B2 JP H0834224B2 JP 62082314 A JP62082314 A JP 62082314A JP 8231487 A JP8231487 A JP 8231487A JP H0834224 B2 JPH0834224 B2 JP H0834224B2
Authority
JP
Japan
Prior art keywords
gate electrode
field effect
effect transistor
low resistance
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP62082314A
Other languages
Japanese (ja)
Other versions
JPS63248178A (en
Inventor
一孝 上武
浅光 東坂
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP62082314A priority Critical patent/JPH0834224B2/en
Publication of JPS63248178A publication Critical patent/JPS63248178A/en
Publication of JPH0834224B2 publication Critical patent/JPH0834224B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電界効果トランジスタの製造方法に関し、特
にゲート電極上に低抵抗金属が被せられた電界効果トラ
ンジスタの製造方法に関する。
TECHNICAL FIELD The present invention relates to a method for manufacturing a field effect transistor, and more particularly to a method for manufacturing a field effect transistor in which a low resistance metal is covered on a gate electrode.

〔従来の技術〕[Conventional technology]

電界効果トランジスタは低電力,高速なスイッチング
素子として古くから開発が進められており、特にn型砒
化ガリウム(GaAs)を動作層とするGaAsショットキ障壁
ゲート型電界効果トランジスタ(以下GaAsMESFETと称
す)は、次世代の超高速コンピュータのキー・デバイス
として注目されている。GaAsMESFETの特性を特徴できる
最も重要なパラメータは伝達コンダクタンス(gm)であ
り、gmを向上する為に種々なデバイスプロセス上の工夫
が成されている。
Field effect transistors have been developed as a low-power, high-speed switching element for a long time. In particular, a GaAs Schottky barrier gate type field effect transistor (hereinafter referred to as GaAs MESFET) using n-type gallium arsenide (GaAs) as an operating layer is It is attracting attention as a key device for next-generation ultra-high speed computers. The most important parameter that can characterize the characteristics of GaAs MESFETs is the transfer conductance (gm), and various device processes have been devised to improve gm.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

第3図はいわゆる自己整合法を用いたGaAsMESFETの断
面形状を示すものであり、半絶縁性基板11中にイオン注
入法により半導体動作層12を形成したるあと、高融点金
属、例えばタングステンシリサイド(Wsi)より成るゲ
ート電極13を形成し、それをマスクとして高濃度のイオ
ンを注入し、ゲート電極のソース電極14,ドレイン電極1
5側に低抵抗領域16を形成している。ゲート電極として
高融点金属を用いているのは注入イオンの活性化の為の
アニーリング処理(通常700℃以上)に耐える必要が有
る為である。本構造においては、ゲート電極の両側に低
抵抗領域が設けられている為、直列寄生抵抗が小さく、
高いgmを得ることが可能であるが、一般に高融点金属は
比抵抗が高い為、ゲート抵抗が増大するという欠点が有
った。ゲート抵抗の低減の為に、第4図の如く、Au−Ti
N−Wsiの3層金属31を用いる方法も提案されているが、
この場合には、低抵抗金属である(TiN)−AuがWsiゲー
ト電極の上面にしか接していないため、接着度が弱く、
低抵抗金属が高融点金属から剥離するという事故もしば
しば発生した。
FIG. 3 shows a cross-sectional shape of a GaAs MESFET using the so-called self-alignment method. After the semiconductor operating layer 12 is formed in the semi-insulating substrate 11 by the ion implantation method, a refractory metal such as tungsten silicide ( Wsi) gate electrode 13 is formed, high concentration ions are implanted using it as a mask, and source electrode 14 and drain electrode 1 of the gate electrode are formed.
A low resistance region 16 is formed on the 5 side. The reason why the refractory metal is used as the gate electrode is that it is necessary to withstand the annealing treatment (usually 700 ° C. or higher) for activating the implanted ions. In this structure, since the low resistance region is provided on both sides of the gate electrode, the series parasitic resistance is small,
Although high gm can be obtained, refractory metals generally have high specific resistance and thus have a drawback of increasing gate resistance. In order to reduce the gate resistance, as shown in Fig. 4, Au-Ti
A method using N-Wsi three-layer metal 31 is also proposed,
In this case, since the low resistance metal (TiN) -Au is in contact with only the upper surface of the Wsi gate electrode, the adhesion is weak,
Accidents in which the low-resistance metal peeled off from the high-melting metal also often occurred.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は従来の電界効果トランジスタにおける上記の
如き欠点に鑑みて成されたものであり、その目的は、ゲ
ート抵抗が低い、しかも機械的強度も強いゲート電極を
有する電界効果トランジスタの製造方法を提供すること
にある。
The present invention has been made in view of the above-mentioned drawbacks of conventional field effect transistors, and an object thereof is to provide a method for manufacturing a field effect transistor having a gate electrode having low gate resistance and high mechanical strength. To do.

本発明の電界効果トランジスタの製造方法は、半絶縁
性基板に設けられた半導体動作層上に高融点金属からな
るゲート電極を形成する工程と、全面にホトレジストを
塗布し、つづけて全面をドライエッチングを行い前記ホ
トレジストを所定量エッチングすることにより前記ゲー
ト電極の上面部及び側面の一部を露出する工程と、次に
全面に蒸着により低抵抗金属を形成する工程と、前記低
抵抗金属を前記露出した前記ゲート電極の上面部及び側
面部を包み込む形状にパターニングする工程と、前記ホ
トレジストを除去する工程とを有し、前記ゲート電極の
上面部から所定側面部にまで接する帽子状の低抵抗金属
を形成する。
The method for manufacturing a field effect transistor of the present invention comprises a step of forming a gate electrode made of a refractory metal on a semiconductor operating layer provided on a semi-insulating substrate, a photoresist is applied to the entire surface, and then the entire surface is dry-etched. And exposing a portion of the upper surface and side surfaces of the gate electrode by etching the photoresist by a predetermined amount, and then forming a low resistance metal on the entire surface by vapor deposition, and exposing the low resistance metal. And a step of removing the photoresist, the step of patterning the upper surface and the side surface of the gate electrode so as to wrap it, and a hat-shaped low resistance metal contacting from the upper surface of the gate electrode to a predetermined side surface is formed. Form.

〔実施例〕〔Example〕

次に本発明につき、図面を参照して説明する。第1図
は本発明の一実施例の断面図であり、比抵抗107So−cm
以上の半絶縁性GaAs基板11上に、n型GaAs半導体動作層
12(キャリア密度2×1017cm-3,厚み0.1μm)がイオン
注入法により設けられている。該半導体動作層12の表面
にAuGe合金よりなるソース電極14,ドレイン電極15が設
けられ、かつWsi高融点金属より成るゲート電極13がソ
ース電極14とドレイン電極15の間に設けられている。ゲ
ート電極の両側には直列寄生抵抗を減じるための低抵抗
領域(厚み0.3μm,キャリア密度5×1017cm-3)16が設
けられている。図においてゲート電極厚み,長さはとも
に例えば0.5μmである。本発明による電界効果トラン
ジスタの骨子はゲート電極13の上面17および側面の1部
18に亘って形成されている帽子状の低抵抗金属(Ti−Pt
−Au)19である。低抵抗金属の厚みは0.5μmであり、
ゲート電極の上面17および肩から0.2μm下がった側面1
8においてゲート電極に接している。
Next, the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view of one embodiment of the present invention, showing a specific resistance of 10 7 So-cm.
An n-type GaAs semiconductor operating layer is formed on the above semi-insulating GaAs substrate 11.
12 (carrier density 2 × 10 17 cm −3 , thickness 0.1 μm) are provided by the ion implantation method. A source electrode 14 and a drain electrode 15 made of an AuGe alloy are provided on the surface of the semiconductor operating layer 12, and a gate electrode 13 made of a Wsi refractory metal is provided between the source electrode 14 and the drain electrode 15. A low resistance region (thickness 0.3 μm, carrier density 5 × 10 17 cm −3 ) 16 is provided on both sides of the gate electrode to reduce series parasitic resistance. In the figure, the gate electrode thickness and length are both 0.5 μm. The essence of the field-effect transistor according to the present invention is the upper surface 17 and a part of the side surface of the gate electrode 13.
Hat-shaped low resistance metal (Ti-Pt) formed over 18
-Au) 19. The thickness of the low resistance metal is 0.5 μm,
The upper surface 17 of the gate electrode and the side surface 0.2 μm down from the shoulder 1
It is in contact with the gate electrode at 8.

次に第1図に示す電界効果トランジスタの製作方法の
1例を第2図を用いて説明する。第2図(A)は通常の
方法で半絶縁性基板上にソース14,ドレイン15,ゲート13
の各電極を設けた状態を示す。WSiゲート電極のゲート
長は0.5μm,ゲート電極も0.5μmとなっている。次に第
2図(B)で全面にホトレジスト21を塗布し、つづいて
同図(C)のように全面を垂直方向からドライエッチン
グすると、ゲート電極13の頭部22が露出してくる。次に
同図(D)において全面にTi(200Å)−Pt(200Å)−
Au(5000Å)19を連結蒸着し、(E)の如く所定のホト
レジストマスク23を設け上記Ti−Pt−Au膜をエッチング
し、最后に不要となったホトレジストを除去すると、第
1図に示した電界効果トランジスタが得られる。
Next, one example of a method of manufacturing the field effect transistor shown in FIG. 1 will be described with reference to FIG. FIG. 2A shows a source 14, a drain 15 and a gate 13 on a semi-insulating substrate by a usual method.
3 shows a state in which each electrode is provided. The gate length of the WSi gate electrode is 0.5 μm, and the gate electrode is also 0.5 μm. Next, a photoresist 21 is applied to the entire surface in FIG. 2B, and then the entire surface is dry-etched from the vertical direction as shown in FIG. 2C, so that the head 22 of the gate electrode 13 is exposed. Next, in the same figure (D), Ti (200Å) -Pt (200Å)-
Au (5000Å) 19 is vapor-deposited, a predetermined photoresist mask 23 is provided as shown in (E), the above Ti-Pt-Au film is etched, and the unnecessary photoresist is removed at the end, as shown in FIG. A field effect transistor is obtained.

〔発明の効果〕〔The invention's effect〕

以上説明したように本発明による電界効果トランジス
タにおいては、高融点金属ゲート電極の頭部に帽子状に
低抵抗金属を設けてあるので、ゲート抵抗の低減が可能
であり高周波特性の良い電界効果トランジスタが得られ
る。さらに、該低抵抗金属は、ゲート電極の上面のみで
なく、側面にも亘って接しているため、機械的強度も十
分である。
As described above, in the field effect transistor according to the present invention, the high-melting-point metal gate electrode has the hat-shaped low resistance metal provided on the head thereof, so that the gate resistance can be reduced and the high-frequency characteristic is excellent. Is obtained. Further, since the low resistance metal is in contact not only with the upper surface of the gate electrode but also with the side surface thereof, the mechanical strength is sufficient.

尚、本発明における実施例ではGaAsMESFETについて示
したが、電界効果トランジスタとしてはGaAsMESFETに限
ることなく、高融点ゲート金属を用いる他の電界効果ト
ランジスタ(MOSFET含む)にも適用できることは言うま
でもない。
Although the GaAs MESFET is shown in the embodiment of the present invention, it is needless to say that the field effect transistor is not limited to the GaAs MESFET and can be applied to other field effect transistors (including MOSFET) using a high melting point gate metal.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の1実施例の断面図、第2図(A)〜
(E)はその製造方法の1例を示す工程断面図、第3
図,第4図は従来の電界効果トランジスタの断面図であ
る。 11……半絶縁性基板、12……半導体動作層、13……ゲー
ト電極、14……ソース電極、15……ドレイン電極、16…
…低抵抗領域、17……ゲート電極上面、18……側面、19
……低抵抗金属、21……ホトレジスト、22……ゲート電
極頭部、23……ホトレジストパターン、31……Ti−Pt−
Au膜。
FIG. 1 is a sectional view of one embodiment of the present invention, and FIG.
(E) is a process sectional view showing an example of the manufacturing method,
FIG. 4 and FIG. 4 are sectional views of a conventional field effect transistor. 11 ... Semi-insulating substrate, 12 ... Semiconductor operating layer, 13 ... Gate electrode, 14 ... Source electrode, 15 ... Drain electrode, 16 ...
… Low resistance region, 17 …… Gate electrode top surface, 18 …… Side surface, 19
...... Low resistance metal, 21 ...... Photoresist, 22 ...... Gate electrode head, 23 ...... Photoresist pattern, 31 ...... Ti-Pt-
Au film.

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】半絶縁性基板に設けられた半導体動作層上
に高融点金属からなるゲート電極を形成する工程と、全
面にホトレジストを塗布し、つづけて全面をドライエッ
チングを行い前記ホトレジストを所定量エッチングする
ことにより前記ゲート電極の上面部及び側面の一部を露
出する工程と、次に全面に蒸着により低抵抗金属を形成
する工程と、前記低抵抗金属を前記露出した前記ゲート
電極の上面部及び側面部を包み込む形状にパターニング
する工程と、前記ホトレジストを除去する工程とを有
し、前記ゲート電極の上面部から所定側面部にまで接す
る帽子状の低抵抗金属を形成することを特徴とする電界
効果トランジスタの製造方法。
1. A step of forming a gate electrode made of a refractory metal on a semiconductor operating layer provided on a semi-insulating substrate, a photoresist is applied to the entire surface, and then the entire surface is dry-etched to leave the photoresist. A step of exposing a part of an upper surface portion and a side surface of the gate electrode by quantitative etching; a step of forming a low resistance metal on the entire surface by vapor deposition; and a step of exposing the low resistance metal to the upper surface of the gate electrode. And forming a hat-shaped low-resistance metal in contact with a predetermined side surface portion from the upper surface portion of the gate electrode, and a step of patterning the portion and the side surface portion so as to enclose the portion and the side surface portion. Of manufacturing a field effect transistor having
JP62082314A 1987-04-02 1987-04-02 Method for manufacturing field effect transistor Expired - Lifetime JPH0834224B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62082314A JPH0834224B2 (en) 1987-04-02 1987-04-02 Method for manufacturing field effect transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62082314A JPH0834224B2 (en) 1987-04-02 1987-04-02 Method for manufacturing field effect transistor

Publications (2)

Publication Number Publication Date
JPS63248178A JPS63248178A (en) 1988-10-14
JPH0834224B2 true JPH0834224B2 (en) 1996-03-29

Family

ID=13771106

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62082314A Expired - Lifetime JPH0834224B2 (en) 1987-04-02 1987-04-02 Method for manufacturing field effect transistor

Country Status (1)

Country Link
JP (1) JPH0834224B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237192A (en) * 1988-10-12 1993-08-17 Mitsubishi Denki Kabushiki Kaisha MESFET semiconductor device having a T-shaped gate electrode

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6155967A (en) * 1984-08-28 1986-03-20 Toshiba Corp Manufacture of field-effect transistor
JPS6167272A (en) * 1984-09-10 1986-04-07 Matsushita Electronics Corp Manufacture of field effect transistor
JPS61236167A (en) * 1985-04-12 1986-10-21 Nec Corp Manufacture of semiconductor device
JPS62274673A (en) * 1986-05-22 1987-11-28 Mitsubishi Electric Corp Manufacture of semiconductor device

Also Published As

Publication number Publication date
JPS63248178A (en) 1988-10-14

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