JP2664935B2 - Method for manufacturing field effect transistor - Google Patents
Method for manufacturing field effect transistorInfo
- Publication number
- JP2664935B2 JP2664935B2 JP63148635A JP14863588A JP2664935B2 JP 2664935 B2 JP2664935 B2 JP 2664935B2 JP 63148635 A JP63148635 A JP 63148635A JP 14863588 A JP14863588 A JP 14863588A JP 2664935 B2 JP2664935 B2 JP 2664935B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- resist
- heat
- effect transistor
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、電界効果トランジスタの製造方法に関す
るものである。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a field effect transistor.
従来の耐熱性材料上に低抵抗化のために低抵抗材料を
形成してゲート電極とするショットキ障壁ゲート電界効
果トランジスタの作製プロセスを第２図に示す。FIG. 2 shows a manufacturing process of a conventional Schottky barrier gate field-effect transistor in which a low-resistance material is formed on a heat-resistant material to reduce the resistance and is used as a gate electrode.
前記従来の耐熱性材料上に低抵抗材料を形成したゲー
ト電極を有するMESFETの作製プロセスは第２図に示すよ
うに、 ａ）半絶縁性GaAs基板１上に形成した活性層２上にショ
ットキー接触が可能な耐熱性材料のゲート電極３加工を
行う。ここで耐熱性材料としてはWSix（ダングステンシ
リサイド）,WNx（タングステンナイトライド）,W−Al
（タングステンアルミ）,W（タングステン）,WSiN（タ
ングステンシリコンナイトライド）等が可能である。As shown in FIG. 2, a process for fabricating a MESFET having a gate electrode in which a low-resistance material is formed on a conventional heat-resistant material is as follows: a) A Schottky is formed on an active layer 2 formed on a semi-insulating GaAs substrate 1. The gate electrode 3 is made of a heat-resistant material that can be contacted. Here, WSix (dungsten silicide), WNx (tungsten nitride), W-Al
(Tungsten aluminum), W (tungsten), WSiN (tungsten silicon nitride) and the like are possible.
ｂ）〜ｃ）前記耐熱性材料のゲート電極３の段差をなく
すために、SiO,SiO2,SiON,SiN等の絶縁性材料６による
平坦化を行う。b) to c) In order to eliminate the step of the gate electrode 3 made of the heat-resistant material, flattening is performed with an insulating material 6 such as SiO, SiO 2 , SiON, SiN or the like.
ｄ）前記ゲート電極３上のみに開口部を有するレジスト
パターン７を形成する。d) A resist pattern 7 having an opening only on the gate electrode 3 is formed.
ｅ）主にAuを含む多層膜（Ti/Au,Ti/Mo/Au,Ti/Pt/Au,Au
のみ等）あるいはAlを含む多層膜（Ti/Al等）等の低抵
抗材料８を全面蒸着する。e) Multilayer film mainly containing Au (Ti / Au, Ti / Mo / Au, Ti / Pt / Au, Au
Only) or a low-resistance material 8 such as a multilayer film containing Al (Ti / Al or the like) is deposited on the entire surface.
ｆ）リフトオフを行い、その後通常のリフトオフプロセ
スにより、即ち絶縁膜６を選択的にエッチングした後蒸
着，リフトオフを行うことにより、Au/Ge等のソース，
ドレイン電極を形成し、続いて必要に応じ通常300〜400
℃，数〜10数分のシンタリングを行なってソース，ドレ
インを形成する。f) Lift-off is performed, and thereafter, by a normal lift-off process, that is, by selectively etching the insulating film 6 and then performing deposition and lift-off, a source such as Au / Ge is formed.
Form a drain electrode, followed by usually 300-400 as needed
Sintering is performed at a temperature of several degrees to several tens of degrees to form a source and a drain.
となっている。It has become.
前記従来の電界効果トランジスタの作製プロセスは、
通常サブミクロン長に形成した耐熱性材料上にマスク合
わせ露光によりレジスト開口部を形成する方法であるた
め、パターンずれが生じやすく、これによるゲート形状
ばらつきのために完成後のMESFET特性がばらつく等の問
題点があった。The manufacturing process of the conventional field effect transistor,
This is a method in which a resist opening is formed by mask alignment exposure on a heat resistant material that is usually formed to a submicron length, so that pattern misalignment is likely to occur, resulting in variations in gate shape and variations in MESFET characteristics after completion. There was a problem.
この発明は上記のような問題点を解消するためになさ
れたもので、耐熱性材料のゲート電極上にセルフアライ
ンにより低抵抗材料を形成することにより、完成後のME
SFET特性がばらつくことのない電界効果トランジスタの
製造方法を得ることを目的とする。The present invention has been made in order to solve the above-described problems, and by forming a low-resistance material by self-alignment on a gate electrode made of a heat-resistant material, the ME after completion is completed.
It is an object of the present invention to provide a method for manufacturing a field effect transistor in which SFET characteristics do not vary.
この発明に係る電界効果トランジスタの製造方法は、
半導体基板に形成した活性層上に耐熱性材料からなる耐
熱性ゲート電極を形成し、上記半導体基板上の全面にレ
ジストを塗布し、上記塗布されたレジストをエッチング
して、耐熱性ゲート電極の上面を露出させ、上記上面を
露出させた耐熱性ゲート電極を選択的にエッチングし
て、該ゲート電極の厚みを減少させ、上記耐熱性ゲート
電極及び上記レジスト上に低抵抗材料層を形成し、上記
レジスト，及び該レジスト上の低抵抗材料層を除去する
ようにしたものである。The method for manufacturing a field-effect transistor according to the present invention includes:
A heat-resistant gate electrode made of a heat-resistant material is formed on an active layer formed on a semiconductor substrate, a resist is applied to the entire surface of the semiconductor substrate, and the applied resist is etched to form an upper surface of the heat-resistant gate electrode. Exposed, selectively etching the heat-resistant gate electrode exposing the upper surface, reducing the thickness of the gate electrode, forming a low-resistance material layer on the heat-resistant gate electrode and the resist, The resist and the low-resistance material layer on the resist are removed.
この発明においては、耐熱性ゲート電極上にセルフア
ラインにより低抵抗材料層が形成され、その２層ゲート
電極形状の制御性，均一性が格段に向上するので、電界
効果トランジスタの制御性、均一性の向上、さらには歩
留りの向上を図ることができる。According to the present invention, the low-resistance material layer is formed on the heat-resistant gate electrode by self-alignment, and the controllability and uniformity of the shape of the two-layer gate electrode are remarkably improved. , And further, the yield can be improved.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図（ａ）〜（ｆ）はこの発明の一実施例を説明す
るための工程断面図である。まず第１図（ａ）に示すよ
うに、半導体基板、例えば半絶縁性GaAs基板１上に比較
的低濃度のｎ型GaAs単結晶層２を形成する。次に第１図
（ｂ）に示すように、前記ｎ層２の表面処理を行った
後、WSix（ダングステンシリサイド）,WNx（タングステ
ンナイトライド）,W−Al（タングステンアルミ）,W（タ
ングステン）,WSiN（タングステンシリコンナイトライ
ド）等の、特にWSixの耐熱性ゲート電極材料をGaAsウエ
ハー上全面に形成し、CF4系ガス，あるいはSF6系ガス，
あるいはNF3系ガスを用いたドライエッチング法でゲー
ト電極パターン３を形成する。次いで第１図（ｃ）に示
すようにウエハー全面にレジスト４を塗布する。次に第
１図（ｄ）に示すようにO2ガスを用いたドライエッチン
グ法でエッチバックを行ない、耐熱性材料ゲート３部の
頭出しを行なう。次いで第１図（ｅ）に示すように前記
耐熱性材料３のみを選択的にエッチングする条件でCF4
系ガス，あるいはSF6系ガス，あるいはNF3系ガスを用い
たドライエッチングを行ない、耐熱性材料３の途中まで
エッチングする。そして第１図（ｆ）に示すようにTi/A
uあるいはTi/Al等の低抵抗材料５を全面に蒸着して、リ
フトオフする。1 (a) to 1 (f) are process cross-sectional views for explaining an embodiment of the present invention. First, as shown in FIG. 1A, an n-type GaAs single crystal layer 2 having a relatively low concentration is formed on a semiconductor substrate, for example, a semi-insulating GaAs substrate 1. Next, as shown in FIG. 1 (b), after performing a surface treatment on the n-layer 2, WSix (dungsten silicide), WNx (tungsten nitride), W-Al (tungsten aluminum), W (tungsten aluminum) ), Heat-resistant gate electrode material such as WSiN (tungsten silicon nitride), especially WSix, is formed on the entire surface of the GaAs wafer, and CF 4 gas or SF 6 gas,
Or to form a gate electrode pattern 3 by dry etching using NF 3 series gas. Next, as shown in FIG. 1C, a resist 4 is applied to the entire surface of the wafer. Next, as shown in FIG. 1 (d), etch back is performed by a dry etching method using an O 2 gas to locate three portions of the heat resistant material gate. Then, as shown in FIG. 1 (e), CF 4 is applied under the condition that only the heat resistant material 3 is selectively etched.
Dry etching using a system gas, SF 6 system gas, or NF 3 system gas is performed to etch halfway through the heat resistant material 3. Then, as shown in FIG. 1 (f), Ti / A
A low-resistance material 5 such as u or Ti / Al is deposited on the entire surface and lift-off is performed.
このような本発明では第１図に示すように、耐熱性ゲ
ート電極３上にセルフアラインにより低抵抗材料５を形
成することができるので、完成される２層ゲート電極形
状の制御性，均一性を従来作製プロセスによるゲート形
状に比し格段に向上させることが可能となり、完成した
FETの特性（RF特性等）の制御性、均一性の向上を達成
でき、さらには歩留りの向上を達成できる。In the present invention, as shown in FIG. 1, since the low-resistance material 5 can be formed on the heat-resistant gate electrode 3 by self-alignment, the controllability and uniformity of the shape of the completed two-layer gate electrode can be improved. Can be significantly improved compared to the gate shape by the conventional manufacturing process, and the completed
Controllability and uniformity of FET characteristics (RF characteristics, etc.) can be improved, and further, yield can be improved.
なお、上記実施例では砒素ガリウム半導体を用いた場
合について述べたが、MESFET作製に際してはInP等の半
導体を用いてもよく、さらにはSi−MOSFETに対してもこ
の発明を適用することができる。Although the arsenic gallium semiconductor is used in the above embodiment, a semiconductor such as InP may be used for fabricating the MESFET, and the present invention can be applied to a Si-MOSFET.
以上のようにこの発明によれば、電界効果トランジス
タの製造方法において、半導体基板に形成した活性層上
に耐熱性材料からなる耐熱性ゲート電極を形成し、上記
半導体基板上の全面にレジストを塗布し、上記塗布され
たレジストをエッチングして、耐熱性ゲート電極の上面
を露出させ、上記上面を露出させた耐熱性ゲート電極を
選択的にエッチングして、該ゲート電極の厚みを減少さ
せ、上記耐熱性ゲート電極及び上記レジスト上に低抵抗
材料層を形成し、上記レジスト，及び該レジスト上の低
抵抗材料層を除去するようにしたので、その２層ゲート
電極形状の制御性，均一性，さらには歩留りを大幅に向
上できる効果がある。As described above, according to the present invention, in a method for manufacturing a field-effect transistor, a heat-resistant gate electrode made of a heat-resistant material is formed on an active layer formed on a semiconductor substrate, and a resist is applied on the entire surface of the semiconductor substrate. Then, the applied resist is etched to expose the upper surface of the heat-resistant gate electrode, and the heat-resistant gate electrode exposing the upper surface is selectively etched to reduce the thickness of the gate electrode. Since a low-resistance material layer is formed on the heat-resistant gate electrode and the resist, and the resist and the low-resistance material layer on the resist are removed, controllability and uniformity of the shape of the two-layer gate electrode are improved. Further, there is an effect that the yield can be greatly improved.
第１図（ａ）〜（ｆ）はこの発明の一実施例による電界
効果トランジスタの製造方法を説明するための各工程に
おけるMESFETの概略断面図、第２図は従来の作製プロセ
スにおける２層ゲート形成部分のプロセスフロー図であ
る。 図において１は半絶縁性GaAs基板、２はｎ型GaAs単結晶
層、３は耐熱性材料によるゲート電極、４はレジスト、
５は低抵抗材料、６は絶縁性材料、７はレジスト、８は
低抵抗材料である。1A to 1F are schematic sectional views of a MESFET in respective steps for explaining a method of manufacturing a field effect transistor according to an embodiment of the present invention, and FIG. 2 is a two-layer gate in a conventional manufacturing process. It is a process flow figure of a formation part. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n-type GaAs single crystal layer, 3 is a gate electrode made of a heat-resistant material, 4 is a resist,
5 is a low resistance material, 6 is an insulating material, 7 is a resist, and 8 is a low resistance material.
Claims (1)
て、 半導体基板に形成した活性層上に耐熱性材料からなるゲ
ート電極を形成する工程と、 上記半導体基板上の全面にレジストを塗布する工程と、 上記塗布されたレジストをエッチングして、ゲート電極
の上面を露出させる工程と、 上記上面を露出させたゲート電極を選択的にエッチング
して、該ゲート電極の厚みを減少させる工程と、 上記ゲート電極及び上記レジスト上に低抵抗材料層を形
成する工程と、 上記レジスト，及び該レジスト上の低抵抗材料層を除去
する工程とを含むことを特徴とする電界効果トランジス
タの製造方法。1. A method for manufacturing a field effect transistor, comprising: a step of forming a gate electrode made of a heat-resistant material on an active layer formed on a semiconductor substrate; and a step of applying a resist on the entire surface of the semiconductor substrate. Etching the applied resist to expose the upper surface of the gate electrode; selectively etching the gate electrode with the exposed upper surface to reduce the thickness of the gate electrode; and A method for manufacturing a field effect transistor, comprising: forming a low-resistance material layer on the resist; and removing the low-resistance material layer on the resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63148635A JP2664935B2 (en) | 1988-06-15 | 1988-06-15 | Method for manufacturing field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63148635A JP2664935B2 (en) | 1988-06-15 | 1988-06-15 | Method for manufacturing field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH022639A JPH022639A (en) | 1990-01-08 |
| JP2664935B2 true JP2664935B2 (en) | 1997-10-22 |
Family
ID=15457202
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63148635A Expired - Lifetime JP2664935B2 (en) | 1988-06-15 | 1988-06-15 | Method for manufacturing field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2664935B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH048374A (en) * | 1990-04-25 | 1992-01-13 | Sumitomo Rubber Ind Ltd | Rubber composition for hollow core of non-pressure tennis ball |
| JP2696145B2 (en) * | 1990-08-23 | 1998-01-14 | 大阪瓦斯株式会社 | Wastewater and sludge treatment methods |
| JP2696146B2 (en) * | 1990-08-23 | 1998-01-14 | 大阪瓦斯株式会社 | Wastewater and sludge treatment methods |
| JPH05299441A (en) * | 1992-04-24 | 1993-11-12 | Matsushita Electric Ind Co Ltd | Manufacture of field effect transistor |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6292481A (en) * | 1985-10-18 | 1987-04-27 | Nec Corp | Manufacture of semiconductor device |
-
1988
- 1988-06-15 JP JP63148635A patent/JP2664935B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH022639A (en) | 1990-01-08 |
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